From patchwork Wed Feb 27 04:51:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 159259 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp4002811jad; Tue, 26 Feb 2019 20:51:17 -0800 (PST) X-Google-Smtp-Source: AHgI3IY0EFB1CrA7k9w39Vq/FjMA8/DfJvEwWq0n7/PBLnN5ePBMoJwtnnQCN6cA3hr9qG1TOs9s X-Received: by 2002:aa7:8186:: with SMTP id g6mr29991044pfi.138.1551243077433; Tue, 26 Feb 2019 20:51:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551243077; cv=none; d=google.com; s=arc-20160816; b=bF/zBBzK4bUW2eN3pRaIVrZQek+GR64BSg2hCLBNIti2SUbVtbs1yZHDNiG4k7+JK2 araTMkFX+oRdigu4/gO+HxO2zilFchijjcXGWnkDZ9ZEcBS6o4mEZ8sV3kj2soxRoT0H yiVAwREOF2mg6PFlkCAiHv057/BTlYdGiTFLazNvZg8s5NJwoG+t2cstjChjLUEocAVT IOHz95q3+XkkNlFZyQkND9tb9rQOV5xfQCd72qtJhQ6hxVROnrExLNVOfO5oD5CP9kdT QiWN5YRqX4PeHSsDulm52Muuzpi2zOUj92nH2RcPpsmpZ+PxRAC7uza0n1EshTqb50az Uoyw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=6DlJUg6IdiLF7gTILSJH+0w7MmsoeqZA9rDoFwZ+iF4=; b=NMqyCAiXJh4ZbZSnU6XNJWkeEXi3NxQYFMMx/lvE+Ik5KCQ7L18mAY1gR8v3ZxtleI zs8VUdzIvCdbhjghRkf0foySBG0djL0qtphGYEsKtj2TnvVMmUYzWN9m8YdUhsEDnagO zSWUm7k6v7tUq75hSz9whINfKiYU2dqBHedDQdOmNcx2r302DbtsHYeU1EuW86SJx4iX p+9XoxzvJOqbyP4CqyNnb1YdutnlrwHSqqtoZAleKiIOxXSOxiVa3/U3BN5EWsE9JKsv cRfonV2BGJooFtB/Sp3n03ivTxP0KcRku2kwEj5REasFvAN/bH5Xo4STyrFpHxhMjTAF UXRw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 3si2477061plz.116.2019.02.26.20.51.17; Tue, 26 Feb 2019 20:51:17 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729570AbfB0EvQ (ORCPT + 7 others); Tue, 26 Feb 2019 23:51:16 -0500 Received: from mx.socionext.com ([202.248.49.38]:30980 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729274AbfB0EvQ (ORCPT ); Tue, 26 Feb 2019 23:51:16 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 27 Feb 2019 13:51:14 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 62FB96117D; Wed, 27 Feb 2019 13:51:14 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 27 Feb 2019 13:51:14 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id BE4751A04E1; Wed, 27 Feb 2019 13:51:13 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 5B7E3121B6C; Wed, 27 Feb 2019 13:51:13 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v4 01/10] dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram Date: Wed, 27 Feb 2019 13:51:49 +0900 Message-Id: <1551243109-10559-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Milbeaut M10V SoC needs a part of sram for smp, so this adds the M10V sram compatible and binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt new file mode 100644 index 0000000..194f6a3 --- /dev/null +++ b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt @@ -0,0 +1,24 @@ +Milbeaut SRAM for smp bringup + +Milbeaut SoCs use a part of the sram for the bringup of the secondary cores. +Once they get powered up in the bootloader, they stay at the specific part +of the sram. +Therefore the part needs to be added as the sub-node of mmio-sram. + +Required sub-node properties: +- compatible : should be "socionext,milbeaut-smp-sram" + +Example: + + sram: sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; From patchwork Wed Feb 27 04:52:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 159260 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp4002985jad; Tue, 26 Feb 2019 20:51:36 -0800 (PST) X-Google-Smtp-Source: AHgI3IZ6QI0mPMNqYnnHs6nJMV0C3kf7Kx7iZgKqUZnI9Bsc3IWPCPg1LsdiZfybf6J29vqDvb4G X-Received: by 2002:a62:bd17:: with SMTP id a23mr29447580pff.233.1551243096645; Tue, 26 Feb 2019 20:51:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551243096; cv=none; d=google.com; s=arc-20160816; b=yruKpbLVdDq8zKtc++X7HGVJz4i8B6qo3c7kHJRbRtCOOAdyL9kD+vAJWVpCvdUmM8 3kP9+EBztd4mRWo8J5pcV73r3Ii4Lvrv5+fpFzPxXVk6YnaI04Qw4E766/PPBrmxerp5 RwkQ+8rrrOIIpw11e0ynliR1w87zY9W3VTyiYj4SzutmAhTmDVlK9X3CFtAteBvEiwkF eXBZOd6eyBKu1bT/P75zROJmxnRPAaMiHca6NmLdbkcgKc6kR6haxHpg3lrqik2oBQcb jvVVvvfuRbYAA/Fy7oLF0GWRdOO4TLZpF+8EyQbnQHT2mi1VSwE9mD0nh+5hpRZnpbve BijA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=cra6Gkzbx5OZOvqRw6LwZ4blCHVIjetAMy5avtTHJiA=; b=mKSLfPs3WqMKJhwJLhZ5d1IyhLGsB0RKfM1isy7KWh7FR/3MSN9aweNo7004YURjEP J9xflNrAUZ1kUH0ct/wUtNe1wL50U/hLLLYYXEEmUPuFwGYPLpCLEiiow4zd0bsN5ki5 fjeMCNrXa3C7PSys5U6poR/WPV2wywHUlzT2IYfZI9eRil2vYRBkrmE0jzhDT2QT3Ekf d9sifpHtQMCOLKIYUEuHzXijOOLzmjM2LlAGwx1IdQEHQhQ10mIFlPZ3A3XCwzUXuJ8V McWy9HErJfV4hwzd9+EbPo8ZL4j8i8FBB8RMX33OR4QedtxdlkBek9jHXgexKDtcM71J 36+w== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 10si14045674pgn.558.2019.02.26.20.51.36; Tue, 26 Feb 2019 20:51:36 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729658AbfB0Evf (ORCPT + 7 others); Tue, 26 Feb 2019 23:51:35 -0500 Received: from mx.socionext.com ([202.248.49.38]:30986 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729654AbfB0Evf (ORCPT ); Tue, 26 Feb 2019 23:51:35 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 27 Feb 2019 13:51:33 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 038E16117D; Wed, 27 Feb 2019 13:51:34 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 27 Feb 2019 13:51:33 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 5DB3C40392; Wed, 27 Feb 2019 13:51:33 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 34614121B6C; Wed, 27 Feb 2019 13:51:33 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v4 02/10] dt-bindings: arm: Add SMP enable-method for Milbeaut Date: Wed, 27 Feb 2019 13:52:05 +0900 Message-Id: <1551243125-10597-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a compatible string "socionext,milbeaut-m10v-smp" for Milbeaut M10V to the 32 bit ARM CPU device tree binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 298c17b..365dcf3 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -228,6 +228,7 @@ patternProperties: - renesas,r9a06g032-smp - rockchip,rk3036-smp - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp - ste,dbx500-smp cpu-release-addr: From patchwork Wed Feb 27 04:52:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 159261 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp4003118jad; Tue, 26 Feb 2019 20:51:51 -0800 (PST) X-Google-Smtp-Source: AHgI3IaDatgSQK7GrffAnilHeKuZE2phdfhR+Rfzqi6JUUj5YWQM4LTnmZoEuF/i5E0AWEySrmq1 X-Received: by 2002:a63:e410:: with SMTP id a16mr1179915pgi.28.1551243111094; Tue, 26 Feb 2019 20:51:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551243111; cv=none; d=google.com; s=arc-20160816; b=o88mUc8td68jS+W/UsdQSr9IB/6prTr5QTQIdSYTUqDdTQB7adu/fKD04PE4lIhhlf +7nJ5IxjSt2f5U50a4HpQ+P/5tAPJ5OZ4+G7Xk7y8Nx/jnozhmoWYLol4vLufLehT3d+ vhhI0zDHa58cpOqW7DKmm+7A0UPCdo6OaE1rb1iMLN09mpcSHaZl0Nl2EXodQfP/Jp2l zco7K1kdFn9E5EO+/u4Uya/Mo2dfcrXIwJeYQYkujVpiVggdkqqCZve2IxmLmAaRlluF tSbJ381a9QgVpEhKaCQO90FuZ/0KghTKj0TlVT3dkPh4twhTeqCAon04T+Vovw0Chbky ahzg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=ob8vd0NC1uJ8wh4UCuNQWxo3uKSoxNyRnWhSX+L/+Q4=; b=SfDO+22zkSJt970pcvrDHP/2mHI+K8hbt/MJQGEPxjjZbpU1tMdQfkTzoBm3F7G7MQ b+7ybJM6E8q4ffsGDWd0WZWjE0ltCQFrBflgyKwG4j877xIV85NR18nuhyN8IYmT8wKE Qom/tTwXkCiVvIAZiNo8Zcr2ijq+ZLBT3Tz28QEOMSXCv6gAUo2vQkPWhUfmUNb7PHbE Wwstyjx5TKLIkeOFuXTg5FQoNLt7brk1nWbRtkKMk4WQxRXvNoyUtjIWoQCWo0dQjplU SM3c00gy2Ezipyf7UstvJZByVytsfnLRqMB8Kfe7Kj3aca2ULCBRCmVIZ7LX9PY/pYd5 4rtQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id s2si13802623plq.345.2019.02.26.20.51.50; Tue, 26 Feb 2019 20:51:51 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729420AbfB0Evu (ORCPT + 7 others); Tue, 26 Feb 2019 23:51:50 -0500 Received: from mx.socionext.com ([202.248.49.38]:30998 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729310AbfB0Evu (ORCPT ); Tue, 26 Feb 2019 23:51:50 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 27 Feb 2019 13:51:48 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id F2D93180D46; Wed, 27 Feb 2019 13:51:48 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 27 Feb 2019 13:51:48 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id BCEC340392; Wed, 27 Feb 2019 13:51:48 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id A49E5121B6C; Wed, 27 Feb 2019 13:51:48 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v4 03/10] dt-bindings: Add documentation for Milbeaut SoCs Date: Wed, 27 Feb 2019 13:52:25 +0900 Message-Id: <1551243145-10635-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- .../bindings/arm/socionext/milbeaut.yaml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml new file mode 100644 index 0000000..aae53fc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/milbeaut.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Milbeaut platforms device tree bindings + +maintainers: + - Taichi Sugaya + - Takao Orito + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - socionext,milbeaut-m10v-evb + - const: socionext,sc2000a +... From patchwork Wed Feb 27 04:52:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 159263 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp4003295jad; Tue, 26 Feb 2019 20:52:13 -0800 (PST) X-Google-Smtp-Source: AHgI3IYmFqJlafFKuy1qs3Hvz8gc/pqIDoSRbauRArsBSWnPyrJvwagpBjq3B8i7BvL4nQ2lDx0N X-Received: by 2002:a63:ea52:: with SMTP id l18mr1116505pgk.317.1551243133426; Tue, 26 Feb 2019 20:52:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551243133; cv=none; d=google.com; s=arc-20160816; b=mhOWlqAq954E4lagjMA3mc+VYDIWwxjpBulOENf2o7k9RMXqPRdexXZww/TVkU0Pkv nVaWo/SNNQIg0u5tffGDR502SJYnf3eJdkgO2QuFH9D7dT+Bu31ZnhAo2FdonmqerHvy pUTj2lF7vKzvErROz/BZIx62XMf2+WE3dVWqO+Nt6+CPoCCEmkHCp/DdBJBMrjJVNP6U 0/AYidT71zTbJXR7Mv5F/8vfCWrOJJiUljXG8KC8bVjTtpAxydK5hcoQrAvuqXYy8lqB 28/C/KJfZ4kXR/0Gduy64UnXP82YFYKf5i5hjHZ/50Z+8q/tHwA3gT+uYhB5JzfoMfNE mknQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=K7UIx7/GIKREL+gm9Whnn5IMWi9A/6HG9N52pVuOFBA=; b=pbMueUimsBNB+T68gdkduAM6a97jJwAm5dOGkMrhVi5HoiianSEyt4Qs7FUvSi9+Sl Ri7jnIJsSxBCT9xSWNW+hfuls84qmrTI8adnsB7Cvv71lgLJCXTcjGbH4NA6fJzZpTYp O8kYTwNx8mkkYThhqny/yVh35BM713mn5wV1X4EZZH4foinwivExLN+9HAmoQx0Y94vU 4POK4ti/K9iY1OHbgM7+PjLTF2iPSLPSeVSiz6iYz0wYrDpJDx6UIr7005tJXPafRDNz GXzmyiuOtgG8KWzPg4OY+nHpmq9I9qP4KaLe6FKjfgUSSXDNpvowASGeKjkUxlR9pE4W 3wzg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id r6si14340232plo.269.2019.02.26.20.52.13; Tue, 26 Feb 2019 20:52:13 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729794AbfB0EwM (ORCPT + 7 others); Tue, 26 Feb 2019 23:52:12 -0500 Received: from mx.socionext.com ([202.248.49.38]:31010 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729310AbfB0EwM (ORCPT ); Tue, 26 Feb 2019 23:52:12 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 27 Feb 2019 13:52:10 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 47AB16117D; Wed, 27 Feb 2019 13:52:10 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 27 Feb 2019 13:52:10 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 9A2FC403E2; Wed, 27 Feb 2019 13:52:09 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 510EC121B6C; Wed, 27 Feb 2019 13:52:09 +0900 (JST) From: Sugaya Taichi To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, soc@kernel.org Cc: Daniel Lezcano , Thomas Gleixner , Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v4 05/10] dt-bindings: timer: Add Milbeaut M10V timer description Date: Wed, 27 Feb 2019 13:52:41 +0900 Message-Id: <1551243161-10712-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings document for Milbeaut M10V timer. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../bindings/timer/socionext,milbeaut-timer.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt new file mode 100644 index 0000000..ac44c4b --- /dev/null +++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt @@ -0,0 +1,17 @@ +Milbeaut SoCs Timer Controller + +Required properties: + +- compatible : should be "socionext,milbeaut-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : The interrupt of the first timer. +- clocks: phandle to the input clk. + +Example: + +timer { + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20> + interrupts = <0 91 4>; + clocks = <&clk 4>; +}; From patchwork Wed Feb 27 04:53:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 159265 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp4003830jad; Tue, 26 Feb 2019 20:52:59 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia80J8DpUdDeHlUMOjWN8QfOe34Rkf2zdesDdwmwGIgpm/HC2mL4NlxTGaxqs7xMFlgSBO3 X-Received: by 2002:a62:ee0e:: with SMTP id e14mr30000766pfi.201.1551243179551; Tue, 26 Feb 2019 20:52:59 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551243179; cv=none; d=google.com; s=arc-20160816; b=I1K6bOevzVElxGyYblHZxKckeemzzuUs7djGMDBHVJtLXOovvrt70sX8KuNXWGW2l2 jRUAdQ6O8gaapwxDZVl/cC2SSGrpQ5+2OAi3evaoyy/NDaxyobyUspXdsTeIlnYLHi0m Lxbeix2PGmLY7XZdFc00ZK71HUP9TREU1q5Mbd14lwb56bmBrTYuPeuSisQL3P7Q7aJB Mc7b66leNdjqL/rvRP366PtpnfM1GhneJT+RlGs3vWfNf3sR397VTlt3qkBS+VHoYvdF rZAorFMuBlDJU6agHWadt/bkKuQFdGp68DeoCwnl8QOSXkPOK0UMRD+NjNNSmqHtouuy hxWA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=QVYVtYGvyY+sGC5kBfpUqnMBy3pyTizivWEJiX6oj8Y=; b=mX/XPBl756D0MSDLjD73vawl2T0z6xPTlakEz9dHP1FjZcqJwaZTMRHtBKNFoBEroq ixXJPdp7q83ihxiEx6ORXqXOSqekKT63KFKeDBWp+OJRX3/Mg3YvFpZ7fOQxZlnixrR4 m4QGZN0dt9cE/nVrglPKOcaD61pCjpLVNWKf5S2z2CkubmuskajjII8XIa45RsEXKm/u FVm3kEfd5SgD5JS74WF9zM5JzLEOxBMy5hSIJZLrJpvdBAFWEasTvE3zzXIhaYmhVs3G I0LA4KCwCRiytIgVdDMh61loXGYUo1OmgW4Ye962RJw5V2yTNtlwh//LRxG9pzvtEkbX ZvFg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g130si13377346pgc.204.2019.02.26.20.52.59; Tue, 26 Feb 2019 20:52:59 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729435AbfB0Ew6 (ORCPT + 7 others); Tue, 26 Feb 2019 23:52:58 -0500 Received: from mx.socionext.com ([202.248.49.38]:31042 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729310AbfB0Ew6 (ORCPT ); Tue, 26 Feb 2019 23:52:58 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 27 Feb 2019 13:52:56 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id 202C16117E; Wed, 27 Feb 2019 13:52:56 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 27 Feb 2019 13:52:56 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 84A901A04E1; Wed, 27 Feb 2019 13:52:55 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 527AC121B6C; Wed, 27 Feb 2019 13:52:55 +0900 (JST) From: Sugaya Taichi To: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, soc@kernel.org Cc: Greg Kroah-Hartman , Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v4 07/10] dt-bindings: serial: Add Milbeaut serial driver description Date: Wed, 27 Feb 2019 13:53:30 +0900 Message-Id: <1551243210-10826-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings document for Milbeaut serial driver. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../devicetree/bindings/serial/milbeaut-uart.txt | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 Documentation/devicetree/bindings/serial/milbeaut-uart.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/serial/milbeaut-uart.txt b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt new file mode 100644 index 0000000..3d2fb1a --- /dev/null +++ b/Documentation/devicetree/bindings/serial/milbeaut-uart.txt @@ -0,0 +1,21 @@ +Socionext Milbeaut UART controller + +Required properties: +- compatible: should be "socionext,milbeaut-usio-uart". +- reg: offset and length of the register set for the device. +- interrupts: two interrupts specifier. +- interrupt-names: should be "rx", "tx". +- clocks: phandle to the input clock. + +Optional properties: +- auto-flow-control: flow control enable. + +Example: + usio1: usio_uart@1e700010 { + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + clocks = <&clk 2>; + auto-flow-control; + }; From patchwork Wed Feb 27 04:53:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 159266 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp4003923jad; Tue, 26 Feb 2019 20:53:07 -0800 (PST) X-Google-Smtp-Source: AHgI3IZmovK4VhDqHbzpxBQe9z6s2gk6M2CeC9oVcCD2eDy3jWdHbarRLSX6Ez3NKMfh2vavlyEu X-Received: by 2002:a65:64d6:: with SMTP id t22mr1184187pgv.52.1551243187858; Tue, 26 Feb 2019 20:53:07 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1551243187; cv=none; d=google.com; s=arc-20160816; b=HhFwVDb9cB5+qVRqRbGPB8+WbtJ0yKVYO7CLtQgeToKQUnQDGxq5u0q7Ab44kB7cdk 2UMRbIBRwkFoKbhXYUYoPTvbA62qrlPtiGe5UdISTXMzFb2EvisU2XHYjEeX6/MEg5a+ LrP689wxNXADqnly3QwIpgPMByxTyg/5PZwSLgiGtOQ/JV+QelllRZDvjFAlNlVQfzPC alK/iJdQlyHgKlEL/U0R5MfncpR4cVl+1t8oxZGOkKnFX3qwb6wIUhY938zTyClRL19f jXKcvMMQ4QkWS/1OKzQQ1/xzEgiQMWreDGivyB/XvRGqxSVcWpxWYjw0LeOcV1yk0+eY aJ4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=OY+ztoZajuLytihlukaHddPZ2VPdYxlcaeLam1fvCJM=; b=TN4KzlVDZZHUZthjnOjjFOs7HCa7yfiP4aEyio36UE7j/I+nWR93hJbRSm3pl1iMEQ NEZgpNT1VB+BLrOnkVKlHC5UVqo8mBYfWbz2tSMYzTnbFCtv/Y0aqN7uhkciWVAVWpj4 Wj/5NVakOlMK5x3sor861VNbi0TIUV87mlhE5rv8ryMjDVqxceyvDtuWmnxyMIutcMRg O8k4nJkL8LKOpx0VELMfn4pOvk1vH4XXfFy/uiPGWuDAPNEaUti3l/i5M2GwWAZhHbM6 Yiuh5hEc3LHK225A8U/SITicOkqVQYRNW99ZfPGSOtRK13W/pYO6f1ri6x5S6NdIVoWz SF2A== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id a73si13744847pge.5.2019.02.26.20.53.07; Tue, 26 Feb 2019 20:53:07 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729595AbfB0ExH (ORCPT + 7 others); Tue, 26 Feb 2019 23:53:07 -0500 Received: from mx.socionext.com ([202.248.49.38]:31047 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729310AbfB0ExH (ORCPT ); Tue, 26 Feb 2019 23:53:07 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 27 Feb 2019 13:53:05 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 65972180D46; Wed, 27 Feb 2019 13:53:05 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 27 Feb 2019 13:53:05 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id D364A40392; Wed, 27 Feb 2019 13:53:04 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id B1B47121B6C; Wed, 27 Feb 2019 13:53:04 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, soc@kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v4 08/10] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board Date: Wed, 27 Feb 2019 13:53:40 +0900 Message-Id: <1551243220-10864-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree for Milbeaut M10V SoC and M10V Evaluation board. Signed-off-by: Sugaya Taichi --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/milbeaut-m10v-evb.dts | 32 +++++++++++ arch/arm/boot/dts/milbeaut-m10v.dtsi | 95 +++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi -- 1.9.1 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148..f697d87 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1233,6 +1233,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb +dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/milbeaut-m10v-evb.dts new file mode 100644 index 0000000..614f60c --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Socionext Milbeaut M10V Evaluation Board */ +/dts-v1/; +#include "milbeaut-m10v.dtsi" + +/ { + model = "Socionext M10V EVB"; + compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "rootwait earlycon"; + stdout-path = "serial0:115200n8"; + }; + + clocks { + uclk40xi: uclk40xi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + +}; diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi new file mode 100644 index 0000000..aa7c6ca --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include + +/ { + compatible = "socionext,sc2000a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,milbeaut-m10v-smp"; + cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + }; + cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + }; + cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + }; + }; + + timer { /* The Generic Timer */ + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <40000000>; + always-on; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&gic>; + + gic: interrupt-controller@1d000000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1d001000 0x1000>, + <0x1d002000 0x1000>; /* CPU I/f base and size */ + }; + + timer@1e000050 { /* 32-bit Reload Timers */ + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20>; + interrupts = <0 91 4>; + }; + + uart1: serial@1e700010 { /* PE4, PE5 */ + /* Enable this as ttyUSI0 */ + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + }; + + }; + + sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; +};