From patchwork Sun Oct 9 18:13:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 613670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E3B8C4332F for ; Sun, 9 Oct 2022 18:14:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230217AbiJISOX (ORCPT ); Sun, 9 Oct 2022 14:14:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35846 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230192AbiJISOR (ORCPT ); Sun, 9 Oct 2022 14:14:17 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E2E12408E; Sun, 9 Oct 2022 11:14:14 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id j16so14099567wrh.5; Sun, 09 Oct 2022 11:14:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gvv29k/7rm7wh832tCEYi58dsefWyN9On5tLmaa0KiA=; b=qCM+U5l0TVhCfxR6XbES7e15P3vufJhKHPqObEfvyb2LP+DXM2v4edG+cN+EM2c+y1 LPSoc/Lcxt4WBHyKvzaLfsaId+26ycFgDh/hHsya8ChWHspx7JkPZGLpWo7Cr5zd9fxo kQlg0PPFct14g6davRBJzmtv6GG8Sw2wtt5M/7rw/h2UfbYlrGSkInyKMXTgPP/8FNyk pBjwJn+nMylvzL9vd010HWEUygo5ZJRz6M4BynZJjuDKR/ecOPPhWXyFZ4ZQjRLU4BMr RZLpb3061y3ZYDJck9rdrwGMtGg1iv1ivrALqY3JM10A5mSf6maoflzkuA/KdAS/ntAJ 7qGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gvv29k/7rm7wh832tCEYi58dsefWyN9On5tLmaa0KiA=; b=zYyV0+mVwBQnaCOHOs/5db79tdmGmhHR+FdpEMnSBvOwiTGZq/IBF/mWTslkvkeNo1 oPORn8YTn2Ak9K1cuBic5MI8MklSSziBeFQqfL3eMV8vFVdv1U25OvSfgPKQjATUoXcV jhhFshucYs+dQm0pt3PpX6ksD9xCQDBscMTVwrN+zYgwrBVSJAiJWA8/8AopMgGKbpFD DfhYDUM1FrLp8IkwIgPu6Dr0WGIJGwYsa9NPjU/F/CizcwdQ9/fW/q7LbArpedtz9Fnc miApiBD2xZ4jAl75qzoNqQa/Al+ra/Nzx7kaHfvfhGuI9Rd86g1YEF6i4rvR/oIma7qE GD6g== X-Gm-Message-State: ACrzQf1P04YRmU7EywPmncsTblge7lb/84TUPVwwbzqFBTJ8bzAStXaE tEK2VIrTqCmFZNF32DgfD8M= X-Google-Smtp-Source: AMsMyM7UkQGGE+cCIG7lmuwBzQMxflhPdy9JuNWipV9xcgCd0Vl9q3hSgBDg4Tnt5T1ycGSTsbyFTg== X-Received: by 2002:a05:6000:2c9:b0:22f:e7b5:bc26 with SMTP id o9-20020a05600002c900b0022fe7b5bc26mr2940042wry.149.1665339253502; Sun, 09 Oct 2022 11:14:13 -0700 (PDT) Received: from hp-power-15.localdomain (mm-190-37-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.37.190]) by smtp.gmail.com with ESMTPSA id k16-20020adfe8d0000000b0022cd0c8c696sm6860581wrn.103.2022.10.09.11.14.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Oct 2022 11:14:13 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Greg Kroah-Hartman , Paul Cercueil , Thomas Bogendoerfer , Linus Walleij , Jiri Slaby , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-serial@vger.kernel.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 1/8] dt-bindings: ingenic: Add support for the JZ4755 SoC Date: Sun, 9 Oct 2022 21:13:30 +0300 Message-Id: <20221009181338.2896660-2-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221009181338.2896660-1-lis8215@gmail.com> References: <20221009181338.2896660-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org JZ4755 is a low-power SoC similar to JZ4725B which is already here. The patch adds compatibles for parts which aren't implemented yet and they are subject of this patch serie. Signed-off-by: Siarhei Volkau Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/clock/ingenic,cgu.yaml | 2 ++ Documentation/devicetree/bindings/dma/ingenic,dma.yaml | 1 + Documentation/devicetree/bindings/serial/ingenic,uart.yaml | 4 ++++ 3 files changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml index aa1df03ef..df256ebcd 100644 --- a/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml +++ b/Documentation/devicetree/bindings/clock/ingenic,cgu.yaml @@ -22,6 +22,7 @@ select: enum: - ingenic,jz4740-cgu - ingenic,jz4725b-cgu + - ingenic,jz4755-cgu - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu @@ -51,6 +52,7 @@ properties: - enum: - ingenic,jz4740-cgu - ingenic,jz4725b-cgu + - ingenic,jz4755-cgu - ingenic,jz4760-cgu - ingenic,jz4760b-cgu - ingenic,jz4770-cgu diff --git a/Documentation/devicetree/bindings/dma/ingenic,dma.yaml b/Documentation/devicetree/bindings/dma/ingenic,dma.yaml index 3b0b3b919..e42b8ce94 100644 --- a/Documentation/devicetree/bindings/dma/ingenic,dma.yaml +++ b/Documentation/devicetree/bindings/dma/ingenic,dma.yaml @@ -18,6 +18,7 @@ properties: - enum: - ingenic,jz4740-dma - ingenic,jz4725b-dma + - ingenic,jz4755-dma - ingenic,jz4760-dma - ingenic,jz4760-bdma - ingenic,jz4760-mdma diff --git a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml index 9ca7a18ec..315ceb722 100644 --- a/Documentation/devicetree/bindings/serial/ingenic,uart.yaml +++ b/Documentation/devicetree/bindings/serial/ingenic,uart.yaml @@ -20,6 +20,7 @@ properties: oneOf: - enum: - ingenic,jz4740-uart + - ingenic,jz4750-uart - ingenic,jz4760-uart - ingenic,jz4780-uart - ingenic,x1000-uart @@ -31,6 +32,9 @@ properties: - items: - const: ingenic,jz4725b-uart - const: ingenic,jz4740-uart + - items: + - const: ingenic,jz4755-uart + - const: ingenic,jz4750-uart reg: maxItems: 1 From patchwork Sun Oct 9 18:13:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 613989 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 715CDC4167E for ; Sun, 9 Oct 2022 18:14:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230251AbiJISOY (ORCPT ); Sun, 9 Oct 2022 14:14:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230222AbiJISOV (ORCPT ); Sun, 9 Oct 2022 14:14:21 -0400 Received: from mail-wr1-x42b.google.com (mail-wr1-x42b.google.com [IPv6:2a00:1450:4864:20::42b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2151C2495C; Sun, 9 Oct 2022 11:14:17 -0700 (PDT) Received: by mail-wr1-x42b.google.com with SMTP id a3so14158696wrt.0; Sun, 09 Oct 2022 11:14:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6FJ7/YP2hXS1vCrLDjBwuedubr0y59mrPeF+JZZ90fI=; b=HOQsCG7/5sEuE+sXETwrV0GdnbxNu1rYLJhzlV67aXmNgjs6EEnKcBlzzIlsFlC1c0 xpwabvivtRl9cr8ry8UC56ONOxIXjyBcslf3jP65BHGvbtORGNFLcZONPxJssg+PjeGi VY/TUFawu1hwdAB+FtS2pEH2XLGYP7AeHMuS6WD9QLLcgTiHkYdjVHPpVj3rOHFbtIYi aViizom8bwaOcl6c7Vf1Yv5ik8zuDGFSilF7coAjOiBEj7Pfwzdt19/j6kFFQH9dD0Nx gAkQC0Jiztqw+ciu8K+32J+5WaIXLa+I2xBnXhQUU6B/MomE1VEOtXnbs1Vt4sQlx3un ccKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6FJ7/YP2hXS1vCrLDjBwuedubr0y59mrPeF+JZZ90fI=; b=27Hl18ZCeVA+i8cEPHLoTWgW6hPkicM8hPG34QoMV/x5qFtRQZJ+54jRol0jlal6nn nPUKivORSd6gPW00xi6/nxtNsv3ID7NYEtEfK0OMPEdnjDHk9C08C8u8NN1ltzSpzLNY XKyQU3/M/KgYhbFjgKxXtlVQ1D5iiR4wUhsL5KQASBTTlxmCBw1D5RY5qmIsNwjjsrvY T5mMQ0VJOrA3Sgqeb60qX+Hv12Gu2lO/QZYrNCaT6rGBS9E1H2eJVKjBKi4H0QKdX4gn o4EGSkoZ9+mOj3BkWSvSqP3+xp/drV6OiwiCw6//sOTz8CKwPVxnckq48GTn7wiaG/yl Gj0g== X-Gm-Message-State: ACrzQf0lCKfRi1CiRc90ZI28r68EWVwuO3pUvCpOuztyTyFFChnBa0Nn S0g8Qha4aKxv1AIS6dqGCPg= X-Google-Smtp-Source: AMsMyM5F541hi01H5pJzigVsnUROtGbwwQfwT6y0mpnuHDAIezsFEFLBed7xExdy9xDzskCWxXPehw== X-Received: by 2002:adf:e109:0:b0:225:4ca5:80d5 with SMTP id t9-20020adfe109000000b002254ca580d5mr9140902wrz.465.1665339256338; Sun, 09 Oct 2022 11:14:16 -0700 (PDT) Received: from hp-power-15.localdomain (mm-190-37-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.37.190]) by smtp.gmail.com with ESMTPSA id k16-20020adfe8d0000000b0022cd0c8c696sm6860581wrn.103.2022.10.09.11.14.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Oct 2022 11:14:15 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Greg Kroah-Hartman , Paul Cercueil , Thomas Bogendoerfer , Linus Walleij , Jiri Slaby , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-serial@vger.kernel.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 2/8] MIPS: ingenic: add new machine type MACH_JZ4755 Date: Sun, 9 Oct 2022 21:13:31 +0300 Message-Id: <20221009181338.2896660-3-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221009181338.2896660-1-lis8215@gmail.com> References: <20221009181338.2896660-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org which is close to jz4725b because it is actually a low price successor of the jz4755. It has the same MIPS32r1 core with Xburst(R) extension MXU version 1 release 2. Signed-off-by: Siarhei Volkau --- arch/mips/ingenic/Kconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/mips/ingenic/Kconfig b/arch/mips/ingenic/Kconfig index f595b339a..edd84cf13 100644 --- a/arch/mips/ingenic/Kconfig +++ b/arch/mips/ingenic/Kconfig @@ -4,6 +4,7 @@ config MACH_INGENIC_GENERIC bool select MACH_INGENIC select MACH_JZ4740 + select MACH_JZ4755 select MACH_JZ4725B select MACH_JZ4770 select MACH_JZ4780 @@ -53,6 +54,10 @@ config MACH_JZ4740 bool select SYS_HAS_CPU_MIPS32_R1 +config MACH_JZ4755 + bool + select SYS_HAS_CPU_MIPS32_R1 + config MACH_JZ4770 bool select MIPS_CPU_SCACHE From patchwork Sun Oct 9 18:13:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 613669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36974C38A05 for ; Sun, 9 Oct 2022 18:14:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230269AbiJISO1 (ORCPT ); Sun, 9 Oct 2022 14:14:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230237AbiJISOX (ORCPT ); Sun, 9 Oct 2022 14:14:23 -0400 Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CE9BE24BD4; Sun, 9 Oct 2022 11:14:20 -0700 (PDT) Received: by mail-wr1-x431.google.com with SMTP id n12so14080798wrp.10; Sun, 09 Oct 2022 11:14:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Z2QEPdO6PsCVuF/mW/121ufzLvPL8MU/4rRXsN1QWts=; b=bMuaJ85gtHfYIlAiEvzbRVp/4afACs8FvoRuQ4Ql2ia6fqPXo2ASKqRn1ESwnpptN9 fvh/zdnX/QHbgiCHsXLXVZVxiwx8I/78J2IX4C+hAvxj+Pzu+UZUcpgAfUICNDas3rRs Q0zA+fusiGxQz0zHQXSWhGaCPQqAaQOpEiFhcsu6AqPAaxMp9u912LaE117SqiBBuEIV RQX8rjPXGz2+zQs8jK1O2076gywqh8RtIITn110gDN64EsOOUE3lRgdv2j9dRc/8xGuU FhrKb4UTDYCK0EEmT4XKIXCar4sP3+3FH4u1iSPJQyg5jKnwLmbXVMtAPwyIj3+ddArp sfEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Z2QEPdO6PsCVuF/mW/121ufzLvPL8MU/4rRXsN1QWts=; b=s8ahV4DVHicaGSLqy3/Nu4h/NRrN0h8HCa6b2GKv29WgRfOoKSXTxCPAIZWGkoXV1x UO65G1b9PjySCSa12x4xY7ChG0w7dX5dYadHlfayTX2qjw3lxmrk01gVVVbcfhjamNPs oJYR18w5QP95eDHzMYPEwGyjjrbGdLF/WgK+885l5DBF8du3/2/+kvaY9yGj5GATXQiB +GuIuLNjeJJZzztbbY28RPDOqRlgZOIjF/AmoQ75oj0WQECp5NdCf9JvN8K1IO7zM+0v VUckdiGe60z0v6mChlzEPgO6VWQ7uGAN1b673zl79jrif4JLUn4KdG7YQP3SXKKMvoOz w+Pg== X-Gm-Message-State: ACrzQf2iutoOxSuK2T9vI/zaWhp0738vXE7ipX7UX/3KxFe0N3tUFgde zs69997w93f6w0RPgAa0mss= X-Google-Smtp-Source: AMsMyM4Xz69Xa/lHS04ZpSnTpGZcIlJj+f56cX0ujPGoFycMW4Vj/7wx7XzbWfJU/hOndUBITMmc6Q== X-Received: by 2002:adf:eecc:0:b0:22e:3e6d:fb62 with SMTP id a12-20020adfeecc000000b0022e3e6dfb62mr9203290wrp.302.1665339259207; Sun, 09 Oct 2022 11:14:19 -0700 (PDT) Received: from hp-power-15.localdomain (mm-190-37-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.37.190]) by smtp.gmail.com with ESMTPSA id k16-20020adfe8d0000000b0022cd0c8c696sm6860581wrn.103.2022.10.09.11.14.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Oct 2022 11:14:18 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Greg Kroah-Hartman , Paul Cercueil , Thomas Bogendoerfer , Linus Walleij , Jiri Slaby , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-serial@vger.kernel.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 3/8] dt-bindings: clock: Add Ingenic JZ4755 CGU header Date: Sun, 9 Oct 2022 21:13:32 +0300 Message-Id: <20221009181338.2896660-4-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221009181338.2896660-1-lis8215@gmail.com> References: <20221009181338.2896660-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This will be used from the devicetree bindings to specify the clocks that should be obtained from the jz4755-cgu driver. Signed-off-by: Siarhei Volkau --- .../dt-bindings/clock/ingenic,jz4755-cgu.h | 49 +++++++++++++++++++ 1 file changed, 49 insertions(+) create mode 100644 include/dt-bindings/clock/ingenic,jz4755-cgu.h diff --git a/include/dt-bindings/clock/ingenic,jz4755-cgu.h b/include/dt-bindings/clock/ingenic,jz4755-cgu.h new file mode 100644 index 000000000..32307f68c --- /dev/null +++ b/include/dt-bindings/clock/ingenic,jz4755-cgu.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * This header provides clock numbers for the ingenic,jz4755-cgu DT binding. + */ + +#ifndef __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ +#define __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ + +#define JZ4755_CLK_EXT 0 +#define JZ4755_CLK_OSC32K 1 +#define JZ4755_CLK_PLL 2 +#define JZ4755_CLK_PLL_HALF 3 +#define JZ4755_CLK_EXT_HALF 4 +#define JZ4755_CLK_CCLK 5 +#define JZ4755_CLK_H0CLK 6 +#define JZ4755_CLK_PCLK 7 +#define JZ4755_CLK_MCLK 8 +#define JZ4755_CLK_H1CLK 9 +#define JZ4755_CLK_UDC 10 +#define JZ4755_CLK_LCD 11 +#define JZ4755_CLK_UART0 12 +#define JZ4755_CLK_UART1 13 +#define JZ4755_CLK_UART2 14 +#define JZ4755_CLK_DMA 15 +#define JZ4755_CLK_MMC 16 +#define JZ4755_CLK_MMC0 17 +#define JZ4755_CLK_MMC1 18 +#define JZ4755_CLK_EXT512 19 +#define JZ4755_CLK_RTC 20 +#define JZ4755_CLK_UDC_PHY 21 +#define JZ4755_CLK_I2S 22 +#define JZ4755_CLK_SPI 23 +#define JZ4755_CLK_AIC 24 +#define JZ4755_CLK_ADC 25 +#define JZ4755_CLK_TCU 26 +#define JZ4755_CLK_BCH 27 +#define JZ4755_CLK_I2C 28 +#define JZ4755_CLK_TVE 29 +#define JZ4755_CLK_CIM 30 +#define JZ4755_CLK_AUX_CPU 31 +#define JZ4755_CLK_AHB1 32 +#define JZ4755_CLK_IDCT 33 +#define JZ4755_CLK_DB 34 +#define JZ4755_CLK_ME 35 +#define JZ4755_CLK_MC 36 +#define JZ4755_CLK_TSSI 37 +#define JZ4755_CLK_IPU 38 + +#endif /* __DT_BINDINGS_CLOCK_JZ4755_CGU_H__ */ From patchwork Sun Oct 9 18:13:33 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 613988 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 48C54C4167B for ; Sun, 9 Oct 2022 18:14:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230300AbiJISOh (ORCPT ); Sun, 9 Oct 2022 14:14:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230268AbiJISO1 (ORCPT ); Sun, 9 Oct 2022 14:14:27 -0400 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F74524BFB; Sun, 9 Oct 2022 11:14:23 -0700 (PDT) Received: by mail-wm1-x330.google.com with SMTP id c3-20020a1c3503000000b003bd21e3dd7aso7323867wma.1; Sun, 09 Oct 2022 11:14:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d8JDCvOfAUYBoTb9WVUDpMWqNhtytW5zy/of+CIG+g8=; b=TeFvgL4ElFVj6WZmL3D9VKpuhy6jBpxhYqoXci7LkiQ4klhOuKV2kgc9PzqFmCXmlu GMIQVQ6EVn8IbBtSp2kz6BTYNwaN57DR1kRfA1sNq4NoKMMnEDyga5g0fM5FovQ/Yy57 qa5dDNiyvCXK1eY4hkuWnji8amW4ede7nICo5tCvNX9U5DNzAB5Z1dsi0nIs9dNh/QLT UH51SmKug/PS8f9coKJuYuhXO17Uc+5gxR5R1m8LrlZ5yLV2qIS0md19QHKDcjoXY0yk blEmSKizOS2iYJGJgPI7xT4FDraNLieRTiDW8SiKJDmqRjtRmVnh9yQmONVKedFtYodG ZlSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d8JDCvOfAUYBoTb9WVUDpMWqNhtytW5zy/of+CIG+g8=; b=wYhOdkAPiyU9p7YcP1zjU7Si2wWbzmEHPav8xySSvzQvXwrotyNON2ueKAYYhBWUcn CXQ6x+sSxlM5I/YH5fN1pSoqnkpHMxd7LiojzQ3ejH95T+nw1Dc+GeVXeXIByKHqEVCn QTJU4Q/uFs7puLE7MwR8nxEKHjzWkhU7YpNrurkumr2dlO4SAghHytFDHZIKfJHvSkGU 0wfxc+iXZ7E8p0+P8P4vUfn8N2HbL/EbcVteGby01usQPTsMV/YXEgGEwCadgPn8ftPq haSwjI8zmt9Hr1+zkypcFpu6a+fPYvj3T68mD7CkaIfRhJG+RTcvcjdhd9fyoNIRxptu IBqw== X-Gm-Message-State: ACrzQf37WHn5XBGDqzxVIqCJKUq1Bus4pcOfQGiH+CZsbliC/HXz6S8p KL1xXjV94lVyV0RcAlKBj1E= X-Google-Smtp-Source: AMsMyM6704QGcCx5yOv/BBDznaXz1RNLs4hoLIkTJ5xyUZrQfU3iLDfcAizNWhCAVNnbcdoFn3c/tA== X-Received: by 2002:a05:600c:3492:b0:3b4:9fcc:cbb6 with SMTP id a18-20020a05600c349200b003b49fcccbb6mr17773574wmq.42.1665339262182; Sun, 09 Oct 2022 11:14:22 -0700 (PDT) Received: from hp-power-15.localdomain (mm-190-37-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.37.190]) by smtp.gmail.com with ESMTPSA id k16-20020adfe8d0000000b0022cd0c8c696sm6860581wrn.103.2022.10.09.11.14.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Oct 2022 11:14:21 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Greg Kroah-Hartman , Paul Cercueil , Thomas Bogendoerfer , Linus Walleij , Jiri Slaby , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-serial@vger.kernel.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 4/8] clk: Add Ingenic JZ4755 CGU driver Date: Sun, 9 Oct 2022 21:13:33 +0300 Message-Id: <20221009181338.2896660-5-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221009181338.2896660-1-lis8215@gmail.com> References: <20221009181338.2896660-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add support for the clocks provided by the CGU in the Ingenic JZ4755 SoC. Signed-off-by: Siarhei Volkau --- drivers/clk/ingenic/Kconfig | 10 + drivers/clk/ingenic/Makefile | 1 + drivers/clk/ingenic/jz4755-cgu.c | 350 +++++++++++++++++++++++++++++++ 3 files changed, 361 insertions(+) create mode 100644 drivers/clk/ingenic/jz4755-cgu.c diff --git a/drivers/clk/ingenic/Kconfig b/drivers/clk/ingenic/Kconfig index 898f1bc47..f80ac4f29 100644 --- a/drivers/clk/ingenic/Kconfig +++ b/drivers/clk/ingenic/Kconfig @@ -15,6 +15,16 @@ config INGENIC_CGU_JZ4740 If building for a JZ4740 SoC, you want to say Y here. +config INGENIC_CGU_JZ4755 + bool "Ingenic JZ4755 CGU driver" + default MACH_JZ4755 + select INGENIC_CGU_COMMON + help + Support the clocks provided by the CGU hardware on Ingenic JZ4755 + and compatible SoCs. + + If building for a JZ4755 SoC, you want to say Y here. + config INGENIC_CGU_JZ4725B bool "Ingenic JZ4725B CGU driver" default MACH_JZ4725B diff --git a/drivers/clk/ingenic/Makefile b/drivers/clk/ingenic/Makefile index 9edfaf461..81d8e23c2 100644 --- a/drivers/clk/ingenic/Makefile +++ b/drivers/clk/ingenic/Makefile @@ -1,6 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_INGENIC_CGU_COMMON) += cgu.o pm.o obj-$(CONFIG_INGENIC_CGU_JZ4740) += jz4740-cgu.o +obj-$(CONFIG_INGENIC_CGU_JZ4755) += jz4755-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4725B) += jz4725b-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4760) += jz4760-cgu.o obj-$(CONFIG_INGENIC_CGU_JZ4770) += jz4770-cgu.o diff --git a/drivers/clk/ingenic/jz4755-cgu.c b/drivers/clk/ingenic/jz4755-cgu.c new file mode 100644 index 000000000..98887f20b --- /dev/null +++ b/drivers/clk/ingenic/jz4755-cgu.c @@ -0,0 +1,350 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Ingenic JZ4755 SoC CGU driver + * Heavily based on JZ4725b CGU driver + * + * Copyright (C) 2022 Siarhei Volkau + * Author: Siarhei Volkau + */ + +#include +#include +#include + +#include + +#include "cgu.h" +#include "pm.h" + +/* CGU register offsets */ +#define CGU_REG_CPCCR 0x00 +#define CGU_REG_LCR 0x04 +#define CGU_REG_CPPCR 0x10 +#define CGU_REG_CLKGR 0x20 +#define CGU_REG_OPCR 0x24 +#define CGU_REG_I2SCDR 0x60 +#define CGU_REG_LPCDR 0x64 +#define CGU_REG_MSCCDR 0x68 +#define CGU_REG_SSICDR 0x74 +#define CGU_REG_CIMCDR 0x7C + +/* bits within the LCR register */ +#define LCR_SLEEP BIT(0) + +static struct ingenic_cgu *cgu; + +static const s8 pll_od_encoding[4] = { + 0x0, 0x1, -1, 0x3, +}; + +static const u8 jz4755_cgu_cpccr_div_table[] = { + 1, 2, 3, 4, 6, 8, +}; + +static const u8 jz4755_cgu_pll_half_div_table[] = { + 2, 1, +}; + +static const struct ingenic_cgu_clk_info jz4755_cgu_clocks[] = { + + /* External clocks */ + + [JZ4755_CLK_EXT] = { "ext", CGU_CLK_EXT }, + [JZ4755_CLK_OSC32K] = { "osc32k", CGU_CLK_EXT }, + + [JZ4755_CLK_PLL] = { + "pll", CGU_CLK_PLL, + .parents = { JZ4755_CLK_EXT, -1, -1, -1 }, + .pll = { + .reg = CGU_REG_CPPCR, + .rate_multiplier = 1, + .m_shift = 23, + .m_bits = 9, + .m_offset = 2, + .n_shift = 18, + .n_bits = 5, + .n_offset = 2, + .od_shift = 16, + .od_bits = 2, + .od_max = 4, + .od_encoding = pll_od_encoding, + .stable_bit = 10, + .bypass_reg = CGU_REG_CPPCR, + .bypass_bit = 9, + .enable_bit = 8, + }, + }, + + /* Muxes & dividers */ + + [JZ4755_CLK_PLL_HALF] = { + "pll half", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 21, 1, 1, -1, -1, -1, 0, + jz4755_cgu_pll_half_div_table, + }, + }, + + [JZ4755_CLK_EXT_HALF] = { + "ext half", CGU_CLK_DIV, + .parents = { JZ4755_CLK_EXT, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 30, 1, 1, -1, -1, -1, 0, + 0, + }, + }, + + [JZ4755_CLK_CCLK] = { + "cclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 0, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_H0CLK] = { + "hclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 4, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_PCLK] = { + "pclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 8, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_MCLK] = { + "mclk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 12, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_H1CLK] = { + "h1clk", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL, -1, -1, -1 }, + .div = { + CGU_REG_CPCCR, 16, 1, 4, 22, -1, -1, 0, + jz4755_cgu_cpccr_div_table, + }, + }, + + [JZ4755_CLK_UDC] = { + "udc", CGU_CLK_MUX | CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 }, + .mux = { CGU_REG_CPCCR, 29, 1 }, + .div = { CGU_REG_CPCCR, 23, 1, 6, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 10 }, + }, + + [JZ4755_CLK_LCD] = { + "lcd", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_LPCDR, 0, 1, 11, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 9 }, + }, + + [JZ4755_CLK_MMC] = { + "mmc", CGU_CLK_DIV, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_MSCCDR, 0, 1, 5, -1, -1, -1 }, + }, + + [JZ4755_CLK_I2S] = { + "i2s", CGU_CLK_MUX | CGU_CLK_DIV, + .parents = { JZ4755_CLK_EXT_HALF, JZ4755_CLK_PLL_HALF, -1, -1 }, + .mux = { CGU_REG_CPCCR, 31, 1 }, + .div = { CGU_REG_I2SCDR, 0, 1, 9, -1, -1, -1 }, + }, + + [JZ4755_CLK_SPI] = { + "spi", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_SSICDR, 0, 1, 4, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 4 }, + }, + + [JZ4755_CLK_TVE] = { + "tve", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4755_CLK_LCD, JZ4755_CLK_EXT, -1, -1 }, + .mux = { CGU_REG_LPCDR, 31, 1 }, + .gate = { CGU_REG_CLKGR, 18 }, + }, + + [JZ4755_CLK_RTC] = { + "rtc", CGU_CLK_MUX | CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT512, JZ4755_CLK_OSC32K, -1, -1 }, + .mux = { CGU_REG_OPCR, 2, 1}, + .gate = { CGU_REG_CLKGR, 2 }, + }, + + [JZ4755_CLK_CIM] = { + "cim", CGU_CLK_DIV | CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF, -1, -1, -1 }, + .div = { CGU_REG_CIMCDR, 0, 1, 8, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 8 }, + }, + + /* Gate-only clocks */ + + [JZ4755_CLK_UART0] = { + "uart0", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 0 }, + }, + + [JZ4755_CLK_UART1] = { + "uart1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 14 }, + }, + + [JZ4755_CLK_UART2] = { + "uart2", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 15 }, + }, + + [JZ4755_CLK_ADC] = { + "adc", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 7 }, + }, + + [JZ4755_CLK_AIC] = { + "aic", CGU_CLK_GATE, + .parents = { JZ4755_CLK_I2S, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 5 }, + }, + + [JZ4755_CLK_I2C] = { + "i2c", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 3 }, + }, + + [JZ4755_CLK_BCH] = { + "bch", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MCLK/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 11 }, + }, + + [JZ4755_CLK_TCU] = { + "tcu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 1 }, + }, + + [JZ4755_CLK_DMA] = { + "dma", CGU_CLK_GATE, + .parents = { JZ4755_CLK_PCLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 12 }, + }, + + [JZ4755_CLK_MMC0] = { + "mmc0", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MMC, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 6 }, + }, + + [JZ4755_CLK_MMC1] = { + "mmc1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_MMC, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 16 }, + }, + + [JZ4755_CLK_AUX_CPU] = { + "aux_cpu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 24 }, + }, + + [JZ4755_CLK_AHB1] = { + "ahb1", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 23 }, + }, + + [JZ4755_CLK_IDCT] = { + "idct", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 22 }, + }, + + [JZ4755_CLK_DB] = { + "db", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 21 }, + }, + + [JZ4755_CLK_ME] = { + "me", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 20 }, + }, + + [JZ4755_CLK_MC] = { + "mc", CGU_CLK_GATE, + .parents = { JZ4755_CLK_H1CLK, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 19 }, + }, + + [JZ4755_CLK_TSSI] = { + "tssi", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 17 }, + }, + + [JZ4755_CLK_IPU] = { + "ipu", CGU_CLK_GATE, + .parents = { JZ4755_CLK_PLL_HALF/* not sure */, -1, -1, -1 }, + .gate = { CGU_REG_CLKGR, 13 }, + }, + + [JZ4755_CLK_EXT512] = { + "ext/512", CGU_CLK_FIXDIV, + .parents = { JZ4755_CLK_EXT }, + + /* JZ4725b doc calls it EXT512, but it seems to be /256... + * Not sure if it applied to JZ4755 too, and which actual + * source is used EXT or EXT_HALF + */ + .fixdiv = { 256 }, + }, + + [JZ4755_CLK_UDC_PHY] = { + "udc_phy", CGU_CLK_GATE, + .parents = { JZ4755_CLK_EXT_HALF, -1, -1, -1 }, + .gate = { CGU_REG_OPCR, 6, true }, + }, +}; + +static void __init jz4755_cgu_init(struct device_node *np) +{ + int retval; + + cgu = ingenic_cgu_new(jz4755_cgu_clocks, + ARRAY_SIZE(jz4755_cgu_clocks), np); + if (!cgu) { + pr_err("%s: failed to initialise CGU\n", __func__); + return; + } + + retval = ingenic_cgu_register_clocks(cgu); + if (retval) + pr_err("%s: failed to register CGU Clocks\n", __func__); + + ingenic_cgu_register_syscore_ops(cgu); +} +CLK_OF_DECLARE_DRIVER(jz4755_cgu, "ingenic,jz4755-cgu", jz4755_cgu_init); From patchwork Sun Oct 9 18:13:34 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 613668 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0687C4332F for ; Sun, 9 Oct 2022 18:14:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230316AbiJISOw (ORCPT ); Sun, 9 Oct 2022 14:14:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230286AbiJISOd (ORCPT ); Sun, 9 Oct 2022 14:14:33 -0400 Received: from mail-wm1-x32c.google.com (mail-wm1-x32c.google.com [IPv6:2a00:1450:4864:20::32c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8470B24F27; Sun, 9 Oct 2022 11:14:26 -0700 (PDT) Received: by mail-wm1-x32c.google.com with SMTP id r3-20020a05600c35c300b003b4b5f6c6bdso5223933wmq.2; Sun, 09 Oct 2022 11:14:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m6MWLfpMgm36Hh1hdddoNd7Zm9YtO8WyrpQujvG1QVw=; b=djHQqmiknPzKppm8tgLpEvoh0YV4JZ3I80KoovZK9iSYJhvUv+pLG9JgkrzzxP2kJM ffxL4m4b0GrT3gw/vBLHkn/KK4r94giSXADx4Np9jil5YYcZK1RmRl1wrMxg2Lcz94CU x0bObo3u4JfRG4KTUG1cLx2+bUqiKXpucrFkpe/6t3EfpOlleEY8fJ4jsrZSgeBZ+3hn hRFTjAAEMu875nBQXODYeAeL1dTQ/ZrWWDw6jRzYVdzJaIioZxq5WWeOEq/SKHhBtY32 LPti9r6MPCPCQfgBZH+D5wP0mn1mQpsbp70GX3nDblIQYSuAah+MQgr4/wrjSfY7flQh wOtA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m6MWLfpMgm36Hh1hdddoNd7Zm9YtO8WyrpQujvG1QVw=; b=Nd2y6IYjiKMvhJTKn/5P1m2B7LPTC4BUNSOocai8Lckom/QyP5PZA8wP2BDvodkXQr dda2ed3XAJYgW1Qg8NbiG9TxjlnExkM2vQ9YHK3pUTFFj6d1ozZvJGfXXAqvfW2neybu BuSog3E/vuPR6E6Vnzxcxst/rA5iSA6wNZs2y8dLnHJ5g4zDVIMvnq+wrfwMnLHqVWFv mNs8248DrFmmDo1hUIBvCsgoiRKYjbW9TqmKoWYzMJ5Ir8hsUNZkuGt5ze8CsJLUbhOm TuXp/Gx1dr0OYuXkvusjcweixxd4QCk0o7IvfvYnIQcIPfiUV5gvn0bH6qgPgNoSFa47 HDJw== X-Gm-Message-State: ACrzQf3EIVZI2neLjD+azwqi8RnahXcqrEba9pZVIewOdxEMrVpjIMH+ 3Vo0xKf9iwlAuc3ygJOYSBc= X-Google-Smtp-Source: AMsMyM7pssZHnhz/cFPK8Be1Wjt1f5ZwipfpiRdfOpcSN7gLSVrOu+bXwV+yX5avGUESQrBuPuZSiQ== X-Received: by 2002:a05:600c:281:b0:3b5:a5:7c9c with SMTP id 1-20020a05600c028100b003b500a57c9cmr16894980wmk.202.1665339265036; Sun, 09 Oct 2022 11:14:25 -0700 (PDT) Received: from hp-power-15.localdomain (mm-190-37-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.37.190]) by smtp.gmail.com with ESMTPSA id k16-20020adfe8d0000000b0022cd0c8c696sm6860581wrn.103.2022.10.09.11.14.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Oct 2022 11:14:24 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Greg Kroah-Hartman , Paul Cercueil , Thomas Bogendoerfer , Linus Walleij , Jiri Slaby , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-serial@vger.kernel.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 5/8] pinctrl: ingenic: JZ4755 minor bug fixes Date: Sun, 9 Oct 2022 21:13:34 +0300 Message-Id: <20221009181338.2896660-6-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221009181338.2896660-1-lis8215@gmail.com> References: <20221009181338.2896660-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Fixes UART1 function bits and mmc groups typo. For pins 0x97,0x99 function 0 is designated to PWM3/PWM5 respectively, function is 1 designated to the UART1. Tested-by: Siarhei Volkau Signed-off-by: Siarhei Volkau --- drivers/pinctrl/pinctrl-ingenic.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ingenic.c b/drivers/pinctrl/pinctrl-ingenic.c index 3a9ee9c8a..2991fe0bb 100644 --- a/drivers/pinctrl/pinctrl-ingenic.c +++ b/drivers/pinctrl/pinctrl-ingenic.c @@ -667,7 +667,7 @@ static u8 jz4755_lcd_24bit_funcs[] = { 1, 1, 1, 1, 0, 0, }; static const struct group_desc jz4755_groups[] = { INGENIC_PIN_GROUP("uart0-data", jz4755_uart0_data, 0), INGENIC_PIN_GROUP("uart0-hwflow", jz4755_uart0_hwflow, 0), - INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 0), + INGENIC_PIN_GROUP("uart1-data", jz4755_uart1_data, 1), INGENIC_PIN_GROUP("uart2-data", jz4755_uart2_data, 1), INGENIC_PIN_GROUP("ssi-dt-b", jz4755_ssi_dt_b, 0), INGENIC_PIN_GROUP("ssi-dt-f", jz4755_ssi_dt_f, 0), @@ -721,7 +721,7 @@ static const char *jz4755_ssi_groups[] = { "ssi-ce1-b", "ssi-ce1-f", }; static const char *jz4755_mmc0_groups[] = { "mmc0-1bit", "mmc0-4bit", }; -static const char *jz4755_mmc1_groups[] = { "mmc0-1bit", "mmc0-4bit", }; +static const char *jz4755_mmc1_groups[] = { "mmc1-1bit", "mmc1-4bit", }; static const char *jz4755_i2c_groups[] = { "i2c-data", }; static const char *jz4755_cim_groups[] = { "cim-data", }; static const char *jz4755_lcd_groups[] = { From patchwork Sun Oct 9 18:13:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 613987 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5C397C433F5 for ; Sun, 9 Oct 2022 18:15:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230340AbiJISPP (ORCPT ); Sun, 9 Oct 2022 14:15:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36190 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230308AbiJISOj (ORCPT ); Sun, 9 Oct 2022 14:14:39 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E27B625585; Sun, 9 Oct 2022 11:14:29 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id e10-20020a05600c4e4a00b003b4eff4ab2cso7314849wmq.4; Sun, 09 Oct 2022 11:14:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=neMO/Xv6+/M8nxm7VBGkm586LqlZgH70RZd7S709kIk=; b=KwDJ6RXnWX8FBRYCwyMKFMioyd7aKSjSZbTr0pdA8dRLrBqv/LVTf4eFz9VdbZgHPY aNhWuOV0ExDv8xAszdAjmAsxQCVuTrA38c1sFTxo2lDeCIuPh4dpND/7//rqn6UyLSpb DjjgRZxJhCT/y9Q3iob9eRxg0ZxokdBp9fSxFICfcVucyh5YSFhDTUuSFo21quWKt1jB +PWCjwA4gqNurBrAVEoxl2C6wAjgwNBOhf9kSlg0btd00ASzAnkyZxYNS0kFbBZAcq1n eG1y9/oiiCL6D+eN/lJreruvvJQgnZw9EdOx5hq7fj/6GqbBesBnk/KnFbujzqx8HU0o aP1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=neMO/Xv6+/M8nxm7VBGkm586LqlZgH70RZd7S709kIk=; b=uPv61sl3ESESKo0G/Kuf7inZhkf6D4tPWQ08kLv+zNrvCh/PZxTi/R5wsxg4meYNLE Tgl53s8sTpq6iTliRzMG3NNTVIrPZn7ge2RfHko4dpmjy5vaQX+uwagWAAiMyHOONuYA wVpHWbCwk3ycWLrfLbf07cNKhFH/dP6crf1dmmXGiAxqbf21uvocXq6f7j/6SxiEC5pC VW0QU9eZ7YbEg/HLjUmCIU/1NHFpXUloauufcW3zO+EwmLbHoxE0qrDYhjJzfmCOVks5 SxJlzFVyGZowPBIack/H6U46MVv4xTGZLGINnHnfR9aqvE9HZvm7e8XRfhdnW5IrOw7l csEw== X-Gm-Message-State: ACrzQf296hA53wF7eiZT3dEe5qbLtiiyn4B/IEcOus7HJ4xsyaepraAg Rico78UWZXZiC/7x6/VUCAI= X-Google-Smtp-Source: AMsMyM7HqocwrUtk98mJbiSx2PpDDdWbQLQCvcQ2JoyZhMGa1/R6iNMH5wbDT1jn7fOGaTTnYA5n8A== X-Received: by 2002:a05:600c:2104:b0:3c6:b7f0:cfd0 with SMTP id u4-20020a05600c210400b003c6b7f0cfd0mr310489wml.128.1665339267904; Sun, 09 Oct 2022 11:14:27 -0700 (PDT) Received: from hp-power-15.localdomain (mm-190-37-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.37.190]) by smtp.gmail.com with ESMTPSA id k16-20020adfe8d0000000b0022cd0c8c696sm6860581wrn.103.2022.10.09.11.14.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Oct 2022 11:14:27 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Greg Kroah-Hartman , Paul Cercueil , Thomas Bogendoerfer , Linus Walleij , Jiri Slaby , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-serial@vger.kernel.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 6/8] dmaengine: JZ4780: Add support for the JZ4755. Date: Sun, 9 Oct 2022 21:13:35 +0300 Message-Id: <20221009181338.2896660-7-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221009181338.2896660-1-lis8215@gmail.com> References: <20221009181338.2896660-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org The JZ4755 has 4 DMA channels per DMA unit, two idential DMA units. The JZ4755 has the similar DMA engine to JZ4725b, so I assume it has the same bug as JZ4725b, see commit a40c94be2336. Signed-off-by: Siarhei Volkau --- drivers/dma/dma-jz4780.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/dma/dma-jz4780.c b/drivers/dma/dma-jz4780.c index 2a483802d..9c1a6e9a9 100644 --- a/drivers/dma/dma-jz4780.c +++ b/drivers/dma/dma-jz4780.c @@ -1038,6 +1038,13 @@ static const struct jz4780_dma_soc_data jz4725b_dma_soc_data = { JZ_SOC_DATA_BREAK_LINKS, }; +static const struct jz4780_dma_soc_data jz4755_dma_soc_data = { + .nb_channels = 4, + .transfer_ord_max = 5, + .flags = JZ_SOC_DATA_PER_CHAN_PM | JZ_SOC_DATA_NO_DCKES_DCKEC | + JZ_SOC_DATA_BREAK_LINKS, +}; + static const struct jz4780_dma_soc_data jz4760_dma_soc_data = { .nb_channels = 5, .transfer_ord_max = 6, @@ -1101,6 +1108,7 @@ static const struct jz4780_dma_soc_data x1830_dma_soc_data = { static const struct of_device_id jz4780_dma_dt_match[] = { { .compatible = "ingenic,jz4740-dma", .data = &jz4740_dma_soc_data }, { .compatible = "ingenic,jz4725b-dma", .data = &jz4725b_dma_soc_data }, + { .compatible = "ingenic,jz4755-dma", .data = &jz4755_dma_soc_data }, { .compatible = "ingenic,jz4760-dma", .data = &jz4760_dma_soc_data }, { .compatible = "ingenic,jz4760-mdma", .data = &jz4760_mdma_soc_data }, { .compatible = "ingenic,jz4760-bdma", .data = &jz4760_bdma_soc_data }, From patchwork Sun Oct 9 18:13:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 613667 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3646CC433F5 for ; Sun, 9 Oct 2022 18:15:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230367AbiJISPT (ORCPT ); Sun, 9 Oct 2022 14:15:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36212 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230219AbiJISOk (ORCPT ); Sun, 9 Oct 2022 14:14:40 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D62C227B38; Sun, 9 Oct 2022 11:14:32 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id bi26-20020a05600c3d9a00b003c1e11f54d2so4085273wmb.2; Sun, 09 Oct 2022 11:14:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=sPcH8XLgYo97PzQXFtpwVWSfZRsC44f58GQxeG6ib0I=; b=hveY9X6fVgK8vgULKzBvaI0i7YZyvK+LsJKNz+UwLxo0zTkq+2pJ8YYVJK2vAwpFpd ln+KSsIg4gPq4RkzQeFJzjCNmo2n/IgmZc1u1neT04cZ/ibRCCfR9SpIkF2I6D7ZQ4d9 UHf0MAskrHAq+UcQ4rizNNek/3RYuD4OYyL1xA6r4ZV6cZ+hMlLu65goT3eXKH7MCj3F kolAyqncmGWobuAMeHEpXaufp+96+Esu4noatAKItlRpXzryY6HajrRhIzyZbiMSR79X uHhUpWmsJNpuwN3i9CdQehCbI+QCvQ2ivg4T2wZ8R+v5xbEg47gjBCv5mQe/EPXm9N61 R8tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=sPcH8XLgYo97PzQXFtpwVWSfZRsC44f58GQxeG6ib0I=; b=esQo0I16D19uY4edk/n+124EWSbkcL41IzW7M5C3i0MvDwrVKyKzEo9P/lIpvPuy5c O6RovshysId+BaC7FpaA+leCj+sEj09bOmgGM92Y4Bv1KxmXafS4a0Vj3sAbd7Mvd17B fmhiM88RimgOpV3lp+VNceKl4NU/ytn7dXnHuOn/Sq0oHjY81GXvs0QUpmImifL745AK oQwwLnuX6gP5dlVc/6SJCbJquggXDMlpG4AJAsceGY1DO4EUywlBw8Xqr6JX9zbKKXNW /sWWOpu1ElAynJO4pmjVJOjomMscZw20a7gtZ/yzwIrVx5FBmyxPhVItwx0wtuJBi2Wm B9yQ== X-Gm-Message-State: ACrzQf266xTpcM02Noqh0bk1MZWJWfIfRhYC3mRIVUTN//CyeJB+eTcJ L6Kf+cyfUplGUAYaJAUjuBA= X-Google-Smtp-Source: AMsMyM47EiytB9HzkrV6vSyhEHN1+zmsPNAc4IhXeuL35QtRv39Lzvcj4LllqDnFpD/p8fh8OxGs1g== X-Received: by 2002:a05:600c:4849:b0:3c6:7e82:a9d7 with SMTP id j9-20020a05600c484900b003c67e82a9d7mr1631928wmo.75.1665339270638; Sun, 09 Oct 2022 11:14:30 -0700 (PDT) Received: from hp-power-15.localdomain (mm-190-37-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.37.190]) by smtp.gmail.com with ESMTPSA id k16-20020adfe8d0000000b0022cd0c8c696sm6860581wrn.103.2022.10.09.11.14.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Oct 2022 11:14:30 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Greg Kroah-Hartman , Paul Cercueil , Thomas Bogendoerfer , Linus Walleij , Jiri Slaby , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-serial@vger.kernel.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 7/8] serial: 8250/ingenic: Add support for the JZ4750/JZ4755 SoCs Date: Sun, 9 Oct 2022 21:13:36 +0300 Message-Id: <20221009181338.2896660-8-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221009181338.2896660-1-lis8215@gmail.com> References: <20221009181338.2896660-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org These SoCs are close to others but they have a clock divisor /2 for low clock peripherals, thus to set up a proper baud rate we need to take this into account. The divisor bit is located in CGU area, unfortunately the clk framework can't be used at early boot steps, so it's checked by direct readl() call. Signed-off-by: Siarhei Volkau --- drivers/tty/serial/8250/8250_ingenic.c | 39 ++++++++++++++++++++++---- 1 file changed, 34 insertions(+), 5 deletions(-) diff --git a/drivers/tty/serial/8250/8250_ingenic.c b/drivers/tty/serial/8250/8250_ingenic.c index 2b2f5d8d2..f2662720d 100644 --- a/drivers/tty/serial/8250/8250_ingenic.c +++ b/drivers/tty/serial/8250/8250_ingenic.c @@ -70,7 +70,8 @@ static void ingenic_early_console_write(struct console *console, ingenic_early_console_putc); } -static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev) +static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev, + int clkdiv) { void *fdt = initial_boot_params; const __be32 *prop; @@ -84,11 +85,11 @@ static void __init ingenic_early_console_setup_clock(struct earlycon_device *dev if (!prop) return; - dev->port.uartclk = be32_to_cpup(prop); + dev->port.uartclk = be32_to_cpup(prop) / clkdiv; } -static int __init ingenic_early_console_setup(struct earlycon_device *dev, - const char *opt) +static int __init ingenic_earlycon_setup_common(struct earlycon_device *dev, + const char *opt, int clkdiv) { struct uart_port *port = &dev->port; unsigned int divisor; @@ -103,7 +104,7 @@ static int __init ingenic_early_console_setup(struct earlycon_device *dev, uart_parse_options(opt, &baud, &parity, &bits, &flow); } - ingenic_early_console_setup_clock(dev); + ingenic_early_console_setup_clock(dev, clkdiv); if (dev->baud) baud = dev->baud; @@ -129,9 +130,31 @@ static int __init ingenic_early_console_setup(struct earlycon_device *dev, return 0; } +static int __init ingenic_early_console_setup(struct earlycon_device *dev, + const char *opt) +{ + return ingenic_earlycon_setup_common(dev, opt, 1); +} + +static int __init jz4750_early_console_setup(struct earlycon_device *dev, + const char *opt) +{ +#define CGU_REG_CPCCR ((void *)CKSEG1ADDR(0x10000000)) +#define CPCCR_ECS BIT(30) + u32 cpccr = readl(CGU_REG_CPCCR); + int clk_div = (cpccr & CPCCR_ECS) ? 2 : 1; +#undef CGU_REG_CPCCR +#undef CPCCR_ECS + + return ingenic_earlycon_setup_common(dev, opt, clk_div); +} + OF_EARLYCON_DECLARE(jz4740_uart, "ingenic,jz4740-uart", ingenic_early_console_setup); +OF_EARLYCON_DECLARE(jz4750_uart, "ingenic,jz4750-uart", + jz4750_early_console_setup); + OF_EARLYCON_DECLARE(jz4770_uart, "ingenic,jz4770-uart", ingenic_early_console_setup); @@ -311,6 +334,11 @@ static const struct ingenic_uart_config jz4740_uart_config = { .fifosize = 16, }; +static const struct ingenic_uart_config jz4750_uart_config = { + .tx_loadsz = 16, + .fifosize = 32, +}; + static const struct ingenic_uart_config jz4760_uart_config = { .tx_loadsz = 16, .fifosize = 32, @@ -328,6 +356,7 @@ static const struct ingenic_uart_config x1000_uart_config = { static const struct of_device_id of_match[] = { { .compatible = "ingenic,jz4740-uart", .data = &jz4740_uart_config }, + { .compatible = "ingenic,jz4750-uart", .data = &jz4750_uart_config }, { .compatible = "ingenic,jz4760-uart", .data = &jz4760_uart_config }, { .compatible = "ingenic,jz4770-uart", .data = &jz4760_uart_config }, { .compatible = "ingenic,jz4775-uart", .data = &jz4760_uart_config }, From patchwork Sun Oct 9 18:13:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Siarhei Volkau X-Patchwork-Id: 613986 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A131CC4332F for ; Sun, 9 Oct 2022 18:15:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230323AbiJISPm (ORCPT ); Sun, 9 Oct 2022 14:15:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230290AbiJISOy (ORCPT ); Sun, 9 Oct 2022 14:14:54 -0400 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E0C262DC; Sun, 9 Oct 2022 11:14:35 -0700 (PDT) Received: by mail-wr1-x436.google.com with SMTP id r13so14082460wrj.11; Sun, 09 Oct 2022 11:14:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6gl5E4rKbJFpFDbpqJhrmR71zChEONYs60mlVSNxv7Q=; b=Hf9xV59KNbiJmIeFb0v3W7hbvyktDzOgWDut5dkFFR/ntdnFPdjwz7lqmem2b8qvBl ialUKm9BQi1bglOo0qQJk38aY2KzDdk2LF+yp9YPP+pkUmVcq3Lv1nSz4Mhkq5h26Wfy WZQv9AOo5pL+lfeTTj5JiwBeX8qt12JspyIHE1AOwvv4zdnf3WrijB6JzxRKJDCNE8fU wkZNyTMfbr99mctiICPPaIdofvcyFEfzx33X4qFuWKfDPHjZq4hIUYF6sY+oTH+U+X8w 7/l/pxlpSWue3AxzRqnOPa0Yf7MspZoYV7RfHtjDUNjlFON84pmWecpB+60kjclXvDlS Wi5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6gl5E4rKbJFpFDbpqJhrmR71zChEONYs60mlVSNxv7Q=; b=Qmbq9grrwr0Q2b/V+GHygLCYED0crjKAkZaCRdax03qc6gebW+RqqURB9HWovP89OC WSy4dZ6HSRMBc/taAd6F1rlQKAIk6uFbDWFWAkiZ212qfCGO2+xoA6Nl1qGDhl/bWHvC wEgOy2uKjZGhd/59PSGmT/5fFZnj+39pNMMWfCx/IwTa0mQz8APcPAh59oSHKuymc7Jq f8bsVWiUFDmzLtqXHjpHlYjKQfjBOQ9VNDDx8fDcPyxusjGDdyOc1tnR2E2ng96NpyVR LvNugsAJ5UHVEUtjN6bOGfXwSQKWwToS7+BQFsagggZnBORHUsNtQe+ekTtPD/EMZb97 ndkA== X-Gm-Message-State: ACrzQf3Cu4NqZym/fv5SdlhhkFLPat1jOleLw9i+xylp9pWbLynRoB/Y xCa7pQN70eXdHxTO1rOaVp4= X-Google-Smtp-Source: AMsMyM4/vuN5Kazlk+Wovuvb1wFgsBiEW7cVEXIFXI645ABmIMQKTxjbIbuy7UceELlyuplkY/LJBw== X-Received: by 2002:a5d:6384:0:b0:22e:6027:9da4 with SMTP id p4-20020a5d6384000000b0022e60279da4mr8859991wru.686.1665339273441; Sun, 09 Oct 2022 11:14:33 -0700 (PDT) Received: from hp-power-15.localdomain (mm-190-37-212-37.vitebsk.dynamic.pppoe.byfly.by. [37.212.37.190]) by smtp.gmail.com with ESMTPSA id k16-20020adfe8d0000000b0022cd0c8c696sm6860581wrn.103.2022.10.09.11.14.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Oct 2022 11:14:33 -0700 (PDT) From: Siarhei Volkau Cc: Siarhei Volkau , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Vinod Koul , Greg Kroah-Hartman , Paul Cercueil , Thomas Bogendoerfer , Linus Walleij , Jiri Slaby , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, dmaengine@vger.kernel.org, linux-serial@vger.kernel.org, linux-mips@vger.kernel.org, linux-gpio@vger.kernel.org Subject: [PATCH 8/8] MIPS: DTS: Ingenic: Add support for the JZ4755 SoC Date: Sun, 9 Oct 2022 21:13:37 +0300 Message-Id: <20221009181338.2896660-9-lis8215@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20221009181338.2896660-1-lis8215@gmail.com> References: <20221009181338.2896660-1-lis8215@gmail.com> MIME-Version: 1.0 To: unlisted-recipients:; (no To-header on input) Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Add preliminary support for boards based on the JZ4755 SoC from Ingenic. It is a low-power SoC with a MIPS32r1 SoC running at ~432 MHz, and no FPU. The JZ4755 SoC is supposed to be newer than the JZ4725B SoC, but its internals are very close to each other. So JZ4755 DT is reusing many JZ4725b drivers because JZ4725b support in the kernel appears earlier. Signed-off-by: Siarhei Volkau --- arch/mips/boot/dts/ingenic/jz4755.dtsi | 439 +++++++++++++++++++++++++ 1 file changed, 439 insertions(+) create mode 100644 arch/mips/boot/dts/ingenic/jz4755.dtsi diff --git a/arch/mips/boot/dts/ingenic/jz4755.dtsi b/arch/mips/boot/dts/ingenic/jz4755.dtsi new file mode 100644 index 000000000..e1630e0fe --- /dev/null +++ b/arch/mips/boot/dts/ingenic/jz4755.dtsi @@ -0,0 +1,439 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "ingenic,jz4755"; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "ingenic,xburst-mxu1.1"; + reg = <0>; + + clocks = <&cgu JZ4755_CLK_CCLK>; + clock-names = "cpu"; + }; + }; + + cpuintc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + compatible = "mti,cpu-interrupt-controller"; + }; + + intc: interrupt-controller@10001000 { + compatible = "ingenic,jz4725b-intc", "ingenic,jz4740-intc"; + reg = <0x10001000 0x14>; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&cpuintc>; + interrupts = <2>; + }; + + ext: ext { + compatible = "fixed-clock"; + #clock-cells = <0>; + }; + + osc32k: osc32k { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <32768>; + }; + + cgu: clock-controller@10000000 { + compatible = "ingenic,jz4755-cgu"; + reg = <0x10000000 0x100>; + + clocks = <&ext>, <&osc32k>; + clock-names = "ext", "osc32k"; + + #clock-cells = <1>; + }; + + uart0: serial@10030000 { + compatible = "ingenic,jz4755-uart", "ingenic,jz4750-uart"; + reg = <0x10030000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <9>; + + clocks = <&cgu JZ4755_CLK_EXT_HALF>, <&cgu JZ4755_CLK_UART0>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart1: serial@10031000 { + compatible = "ingenic,jz4755-uart", "ingenic,jz4750-uart"; + reg = <0x10031000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <8>; + + clocks = <&cgu JZ4755_CLK_EXT_HALF>, <&cgu JZ4755_CLK_UART1>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + uart2: serial@10032000 { + compatible = "ingenic,jz4755-uart", "ingenic,jz4750-uart"; + reg = <0x10032000 0x100>; + + interrupt-parent = <&intc>; + interrupts = <7>; + + clocks = <&cgu JZ4755_CLK_EXT_HALF>, <&cgu JZ4755_CLK_UART2>; + clock-names = "baud", "module"; + + status = "disabled"; + }; + + rtc_dev: rtc@10003000 { + compatible = "ingenic,jz4725b-rtc", "ingenic,jz4740-rtc"; + reg = <0x10003000 0x40>; + + interrupt-parent = <&intc>; + interrupts = <6>; + + clocks = <&cgu JZ4755_CLK_RTC>; + clock-names = "rtc"; + }; + + pinctrl: pinctrl@10010000 { + compatible = "ingenic,jz4755-pinctrl"; + reg = <0x10010000 0x600>; + + #address-cells = <1>; + #size-cells = <0>; + + gpa: gpio@0 { + compatible = "ingenic,jz4755-gpio"; + reg = <0>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 0 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <16>; + }; + + gpb: gpio@1 { + compatible = "ingenic,jz4755-gpio"; + reg = <1>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 32 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <15>; + }; + + gpc: gpio@2 { + compatible = "ingenic,jz4755-gpio"; + reg = <2>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 64 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <14>; + }; + + gpd: gpio@3 { + compatible = "ingenic,jz4755-gpio"; + reg = <3>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 96 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <13>; + }; + + gpe: gpio@4 { + compatible = "ingenic,jz4755-gpio"; + reg = <4>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 128 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <12>; + }; + + gpf: gpio@5 { + compatible = "ingenic,jz4755-gpio"; + reg = <5>; + + gpio-controller; + gpio-ranges = <&pinctrl 0 160 32>; + #gpio-cells = <2>; + + interrupt-controller; + #interrupt-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <11>; + }; + }; + + mmc0: mmc@10021000 { + compatible = "ingenic,jz4725b-mmc"; + reg = <0x10021000 0x1000>; + + clocks = <&cgu JZ4755_CLK_MMC0>; + clock-names = "mmc"; + + interrupt-parent = <&intc>; + interrupts = <25>; + + dmas = <&dmac1 27 0xffffffff>, <&dmac1 26 0xffffffff>; + dma-names = "rx", "tx"; + + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + }; + + mmc1: mmc@10022000 { + compatible = "ingenic,jz4725b-mmc"; + reg = <0x10022000 0x1000>; + + clocks = <&cgu JZ4755_CLK_MMC1>; + clock-names = "mmc"; + + interrupt-parent = <&intc>; + interrupts = <24>; + + dmas = <&dmac1 31 0xffffffff>, <&dmac1 30 0xffffffff>; + dma-names = "rx", "tx"; + + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + }; + + dmac0: dma-controller@13020000 { + compatible = "ingenic,jz4755-dma"; + reg = <0x13020000 0xd0>, <0x13020300 0x14>; + + #dma-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <29>; + + clocks = <&cgu JZ4755_CLK_DMA>; + }; + + dmac1: dma-controller@13020100 { + compatible = "ingenic,jz4755-dma"; + reg = <0x13020100 0xd0>, <0x13020400 0x14>; + + #dma-cells = <2>; + + interrupt-parent = <&intc>; + interrupts = <28>; + + clocks = <&cgu JZ4755_CLK_DMA>; + }; + + tcu: timer@10002000 { + compatible = "ingenic,jz4725b-tcu", "simple-mfd"; + reg = <0x10002000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10002000 0x1000>; + + #clock-cells = <1>; + + clocks = <&cgu JZ4755_CLK_RTC>, + <&cgu JZ4755_CLK_EXT>, + <&cgu JZ4755_CLK_PCLK>, + <&cgu JZ4755_CLK_TCU>; + clock-names = "rtc", "ext", "pclk", "tcu"; + + interrupt-controller; + #interrupt-cells = <1>; + + interrupt-parent = <&intc>; + interrupts = <23>, <22>, <21>; + + watchdog: watchdog@0 { + compatible = "ingenic,jz4725b-watchdog", "ingenic,jz4740-watchdog"; + reg = <0x0 0xc>; + + clocks = <&tcu TCU_CLK_WDT>; + clock-names = "wdt"; + }; + + pwm: pwm@60 { + compatible = "ingenic,jz4725b-pwm"; + reg = <0x60 0x40>; + + #pwm-cells = <3>; + + clocks = <&tcu TCU_CLK_TIMER0>, <&tcu TCU_CLK_TIMER1>, + <&tcu TCU_CLK_TIMER2>, <&tcu TCU_CLK_TIMER3>, + <&tcu TCU_CLK_TIMER4>, <&tcu TCU_CLK_TIMER5>; + clock-names = "timer0", "timer1", "timer2", + "timer3", "timer4", "timer5"; + }; + + ost: timer@e0 { + compatible = "ingenic,jz4725b-ost"; + reg = <0xe0 0x20>; + + clocks = <&tcu TCU_CLK_OST>; + clock-names = "ost"; + + interrupts = <15>; + }; + }; + + aic: audio-controller@10020000 { + compatible = "ingenic,jz4725b-i2s", "ingenic,jz4740-i2s"; + reg = <0x10020000 0x38>; + + #sound-dai-cells = <0>; + + clocks = <&cgu JZ4755_CLK_AIC>, + <&cgu JZ4755_CLK_I2S>, + <&cgu JZ4755_CLK_EXT>, + <&cgu JZ4755_CLK_PLL_HALF>; + clock-names = "aic", "i2s", "ext", "pll half"; + + interrupt-parent = <&intc>; + interrupts = <10>; + + dmas = <&dmac0 25 0xffffffff>, <&dmac0 24 0xffffffff>; + dma-names = "rx", "tx"; + }; + + codec: audio-codec@100200a4 { + compatible = "ingenic,jz4725b-codec"; + reg = <0x100200a4 0x8>; + + #sound-dai-cells = <0>; + + clocks = <&cgu JZ4755_CLK_AIC>; + clock-names = "aic"; + }; + + adc: adc@10070000 { + compatible = "ingenic,jz4725b-adc"; + #io-channel-cells = <1>; + + reg = <0x10070000 0x30>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x10070000 0x30>; + + clocks = <&cgu JZ4755_CLK_ADC>; + clock-names = "adc"; + + interrupt-parent = <&intc>; + interrupts = <18>; + }; + + nemc: memory-controller@13010000 { + compatible = "ingenic,jz4725b-nemc", "ingenic,jz4740-nemc"; + reg = <0x13010000 0x10000>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <1 0 0x18000000 0x4000000>, <2 0 0x14000000 0x4000000>, + <3 0 0x0c000000 0x4000000>, <4 0 0x08000000 0x4000000>; + + clocks = <&cgu JZ4755_CLK_MCLK>; + }; + + udc: usb@13040000 { + compatible = "ingenic,jz4725b-musb", "ingenic,jz4740-musb"; + reg = <0x13040000 0x10000>; + + interrupt-parent = <&intc>; + interrupts = <27>; + interrupt-names = "mc"; + + clocks = <&cgu JZ4755_CLK_UDC>; + clock-names = "udc"; + }; + + lcd: lcd-controller@13050000 { + compatible = "ingenic,jz4725b-lcd"; + reg = <0x13050000 0x1000>; + + interrupt-parent = <&intc>; + interrupts = <31>; + + clocks = <&cgu JZ4755_CLK_LCD>; + clock-names = "lcd_pclk"; + + lcd_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + + port@8 { + reg = <8>; + + ipu_output: endpoint { + remote-endpoint = <&ipu_input>; + }; + }; + }; + }; + + ipu: ipu@13080000 { + compatible = "ingenic,jz4725b-ipu"; + reg = <0x13080000 0x64>; + + interrupt-parent = <&intc>; + interrupts = <30>; + + clocks = <&cgu JZ4755_CLK_IPU>; + clock-names = "ipu"; + + port { + ipu_input: endpoint { + remote-endpoint = <&ipu_output>; + }; + }; + }; + + bch: ecc-controller@130d0000 { + compatible = "ingenic,jz4725b-bch"; + reg = <0x130d0000 0x44>; + + clocks = <&cgu JZ4755_CLK_BCH>; + }; +};