From patchwork Sat Oct 8 12:59:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 613447 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1C4DEC433F5 for ; Sat, 8 Oct 2022 13:00:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229580AbiJHNAC (ORCPT ); Sat, 8 Oct 2022 09:00:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229605AbiJHNAB (ORCPT ); Sat, 8 Oct 2022 09:00:01 -0400 Received: from mout.gmx.net (mout.gmx.net [212.227.15.19]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5368620193; Sat, 8 Oct 2022 05:59:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gmx.net; s=badeba3b8450; t=1665233991; bh=wzkOTYnJQKJYkJPxnzoMHSSdhcxZrVekKaBn/Bl517U=; h=X-UI-Sender-Class:From:To:Cc:Subject:Date; b=jfO4Bz9BadsN2h/gVBAIYdevJ6yX7eIooph61TA5UAEvfaNlMiGmB4NIYcL16Yemk x1Jn03lTvopT1nCsUJlxMhRAA/wdmVORhAwJ7DmBEfC19CwnEjV8oOpXQbMW5VBLzW r98QGcOEFgzDNy6TD7st3ZEbag6WZx91yiILfV3I= X-UI-Sender-Class: 01bb95c1-4bf8-414a-932a-4f6e2808ef9c Received: from probook ([78.35.76.13]) by mail.gmx.net (mrgmx005 [212.227.17.190]) with ESMTPSA (Nemesis) id 1MoO6M-1pVqL10f8a-00ojil; Sat, 08 Oct 2022 14:59:51 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-i2c@vger.kernel.org, openbmc@lists.ozlabs.org Cc: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , linux-kernel@vger.kernel.org Subject: [PATCH 1/2] i2c: npcm7xx: Group bank 0/1 registers together for readability Date: Sat, 8 Oct 2022 14:59:23 +0200 Message-Id: <20221008125924.1220203-1-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-Provags-ID: V03:K1:vLFtaXSUpnsPqk8nKHwmrlqL/rgkq/uCsXKdEwerEcLTrnaAezt QaPocI9atXsckbUe1sgysEnMY0VSdrGd+NeMe0OSOZ0x0lZi9BMLozPbX0uQXwLohCg4+7O sh2oY6fXBamsjeGn2VUX9pODlG0oKE/9MbiuKeCjTh3oYMcwupZ9rQcNrVZjtRIlaxizon/ 5Lp5h1HIJ5Ron8U6Av+YA== X-UI-Out-Filterresults: notjunk:1;V03:K0:Qpyn37DlYkk=:7mKvHz2SWowFMhZgWrWs1o wthtQf/+ql3h9F+stipNW6AXa07KjIpomD3pEu6KpPXTPacmwB6A01s+ultXDcQHoYi9YRMS4 ONzx8B5T7oeqXfsxzbIiP4S6vNCBdqm7jHsDhEaH+IVa+dbHztzl55kuVhgLn6ruO+SkrBci/ 6yVY3AqRLQYM+ovmf1+dknsmpi7N+SlAJLQo11n5uTzluSU47Wd5BC2vgubM3UWEUtUA4EtkD 9Y4xeDotYeZZBiQ/0apDHIFasio9DCoAnvWpPY5ajFYl8zzM7WhB675LCNE0IDL4gyrGkX3Fl OIIoH/0CrYN7q8Bsm4MuY5KKsJ6hDatJiw8jyq1vdR4EwdwhSw8gzGuluJ9lLfpDLpTHed1et r8rhlRWKkivEqcLfaB5J6l4dJjn4idmSbFvaDBxMOlDrsw7h3oGnLd8I2LCcUevYp/HJIunav aYV0NKFJqovnJOPWozE7/kKSJ2ag5xVkf58+0cWTaNEjKpumrE1ZdVkmeyaxaVuwYzQev8anG 9mQKRznuGeyrMYVqEqgXN4nBIhoi4IcPr3UNCgYibTGWfjPiQwOJuurclCc3jWLwlOtsfbFgD cA41xsjmms/a4QxxatQE7bFrZugYNPq+whQkPcn2Z0AmknJSvmkR4cm+nI/9NGr+uWtjqEF22 YFcEGL11Anm4pSnWCr/QfbMnJR4EOpkRt6d+yNAqvMp5r9aeA66nUdxrqS4nMeWB41LiQaH3a oD6ZUZQJe34aRjp1K8qs1OXDJq1EHGy1ZRSVODfd0JDQJvP+tDZxdBwWiOkUI1u7x9vw//Ode z/7ZyNDdnTIMBQKSYWr19zu4NJNSQ8Po/9IuRXCjK3UR52HSlRkaNAno0nEYLqoqgVrLjq0b6 xh49ugXk3Q/XGf+oIzz9Q1FKGXExXs5nOxTCQOUvuJuCRFK9vGVhMdW7COiBxlFVO2BW1NOJL K4dObjlCkt75anGzjsmb1U6RCFoc7NpU+E3v27yJKVvO4oZjp4Wn2882XKNxl/XD41C6TU+ez eilhHt4gx1Z+vQM9+sGHn5PEQg9EO0lAXrt/dyzROR0aPlFPZIefUbuWrkdhLolnQYvwDvLxw OdQZWahevg2evAoPLv5f54HeTKqm+QVdru+tIEwJDWu26xvtV4C9b6jOHe801/65i15/CBvsT qHpd/zhgOdozlKRfhbQr7ROYJq4Tz4ZLwu/1dC+vgAX+L9JMsfE5INxegQfmqHTOsGMH4d5aQ pElUn7gbBt07M+C40VhInln754bgriEfX/HksKyF8kT4wWN184pYSxNdHzOGQLEvEzFpPzcPN PYbfUE7W+O3Gdrd0LExPcv4EB5WkVGFBCGnB6mE6Ge0hKbMwSS2xOI0sZg0SW6t5uiymvEq9R 0Y1OQHCVEAOBqbW6hhpzciOTOL4NUVLVehSn/HDYNVmlxs5VwHQzdypbjb+Mm4lxjPiplPSSf J/yA1K0sbhfxsuTlxc0rVQ0y/IQ3HgXE5/N6pwgc0Nv/ftUsHC5HwvddbG6OJQXjAAlW6Gjw2 fsASkysiyLNjGV3Wl/AtlToGhY6mIhUM80FRa+I8GPSzZ Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org The unlabelled registers NPCM_I2CCTL4 to NPCM_I2CSCLHT overlap with the bank 1 registers below, and they are accessed after selecting bank 0, so they clearly belong to bank 0. Move them together with the other bank 0 registers, and move the unrelated definition of npcm_i2caddr down to keep the banked registers in one piece. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Tali Perry --- drivers/i2c/busses/i2c-npcm7xx.c | 31 +++++++++++++++---------------- 1 file changed, 15 insertions(+), 16 deletions(-) -- 2.35.1 diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c index 0c365b57d9572..9a7a2d0bf5765 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -106,7 +106,7 @@ enum i2c_addr { #define NPCM_I2CCST3 0x19 #define I2C_VER 0x1F -/*BANK0 regs*/ +/* BANK 0 regs */ #define NPCM_I2CADDR3 0x10 #define NPCM_I2CADDR7 0x11 #define NPCM_I2CADDR4 0x12 @@ -115,6 +115,20 @@ enum i2c_addr { #define NPCM_I2CADDR9 0x15 #define NPCM_I2CADDR6 0x16 #define NPCM_I2CADDR10 0x17 +#define NPCM_I2CCTL4 0x1A +#define NPCM_I2CCTL5 0x1B +#define NPCM_I2CSCLLT 0x1C /* SCL Low Time */ +#define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */ +#define NPCM_I2CSCLHT 0x1E /* SCL High Time */ + +/* BANK 1 regs */ +#define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */ +#define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */ +#define NPCM_I2CT_OUT 0x14 /* Bus T.O. */ +#define NPCM_I2CPEC 0x16 /* PEC Data */ +#define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */ +#define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */ +#define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */ #if IS_ENABLED(CONFIG_I2C_SLAVE) /* @@ -131,21 +145,6 @@ static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { }; #endif -#define NPCM_I2CCTL4 0x1A -#define NPCM_I2CCTL5 0x1B -#define NPCM_I2CSCLLT 0x1C /* SCL Low Time */ -#define NPCM_I2CFIF_CTL 0x1D /* FIFO Control */ -#define NPCM_I2CSCLHT 0x1E /* SCL High Time */ - -/* BANK 1 regs */ -#define NPCM_I2CFIF_CTS 0x10 /* Both FIFOs Control and Status */ -#define NPCM_I2CTXF_CTL 0x12 /* Tx-FIFO Control */ -#define NPCM_I2CT_OUT 0x14 /* Bus T.O. */ -#define NPCM_I2CPEC 0x16 /* PEC Data */ -#define NPCM_I2CTXF_STS 0x1A /* Tx-FIFO Status */ -#define NPCM_I2CRXF_STS 0x1C /* Rx-FIFO Status */ -#define NPCM_I2CRXF_CTL 0x1E /* Rx-FIFO Control */ - /* NPCM_I2CST reg fields */ #define NPCM_I2CST_XMIT BIT(0) #define NPCM_I2CST_MASTER BIT(1) From patchwork Sat Oct 8 12:59:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= X-Patchwork-Id: 613674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 54DD0C433F5 for ; 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Sat, 08 Oct 2022 14:59:51 +0200 From: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= To: linux-i2c@vger.kernel.org, openbmc@lists.ozlabs.org Cc: =?utf-8?q?Jonathan_Neusch=C3=A4fer?= , Avi Fishman , Tomer Maimon , Tali Perry , Patrick Venture , Nancy Yuen , Benjamin Fair , linux-kernel@vger.kernel.org Subject: [PATCH 2/2] i2c: npcm7xx: Annotate register field definitions with longer names Date: Sat, 8 Oct 2022 14:59:24 +0200 Message-Id: <20221008125924.1220203-2-j.neuschaefer@gmx.net> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20221008125924.1220203-1-j.neuschaefer@gmx.net> References: <20221008125924.1220203-1-j.neuschaefer@gmx.net> MIME-Version: 1.0 X-Provags-ID: V03:K1:BVtpz2qNRzS11sDXJa30qP9mr0ckzThAxnYrxv7n1H2dEoJLclV BuzJm+d0AejkXL/UEHU2yt2T/1zEjWR5U8Kw+FbEtEh2fepQg+1MRKEWuqrH5wXkfH1fgmg iNHi3fSrEVnv/k/l99t/fCq4bZGLEb4trtgeulf47VlRFoEX5Rf4Sfoo4uY42nxUKxTqbkm /YFt7f2Df1o8aRD27dmBg== X-UI-Out-Filterresults: notjunk:1;V03:K0:+vQchtdoOnM=:psMX5yb5Bp6IaRHBHmENO+ 7rN82ANHYiW7VgnJPPlXey2OrHPyAiCHeIgcnxe0NEeaq7H5iYPp+5gQcWqczx/EcTvHMlQrU N246N3LdBOnu4wRa5Rs07iDskEgD8hnIvff0RVZACaFHN9MT6KVdH3ymmtI5tSAk0h7rmS9Xw LcARCVjaUpzHxwG3QkB57+LadGNx/PMonE93JTWTgp1foFwkGbz0kKkLw9qx/tzkfpxrSdnfS UDrKmmbFIGoEQ4ajLlm6uNzDbL1BHBs4mLU/RpxED31epakAC/PPQJVUksz4pbef0RYW0xgOD TM4Do+2z6mB3SseCyxg2UJDYxUiDo4K5QAaX3uIfjwnixzfxKXUrD6Tuws5f103Y50uJ1Izia Myxlz7zcd8Cg1d3s0+gJtJJZ0Qpf6MdOzKHCimwe9FzUDmelA73KaQNihbf2N3PyQtjdS7FX4 DXJ0hyT/K3H9m4qA+yoo1dwvxrvdgY4UAG6SbEoYt5ZBVXsKk383we4IJJZIwASvXlmAKC0S8 WOsuVIt05ebz8sZ9URf2vE5NSi3bwhdCN+sk9HzDfv63BtbsBEzEXeQke4SfVKSchpSewDA3V yHiVz9RfQWX2uM8bLjRutRRKUKyOdlxygryf75bJ+r/fPzuyxf73ZeqQ+8HFHix+lxxyuiVtp eUJU5p0NDHm9vqomMtn/Kw2u7a611EBnZyKr2fZTZNwjX/yFPxCJxAT6n20ViWSP76ZGzZMQC wnQhOgKjXpGGutUTGuXwPtiMmT7AxIvdHwRQMnWPQhnJoyRVZ0xdyFQEW0mmCp9ZSGP/bhkLZ E/CFoveT5TX0eGhGC6rfsV4UvXdlsjbBNCw1fmTSBDNxDptZ2QAroDBEL9iCPe6yOcpxhocKP NHhb529guCKtGb0eekh3JBGcGw4RbFfGMs0uil+lDNYJkki1BAiZJG14C8Kn7315mkAdc4qSW P4VEpeJFHaSDieP56+1Dph8b9TNWa5ncZOJF3ca6Kr6pZPBJTDInghzr+LD/RtcwKZvwufxXX +JFcOn6VPhjj/FibgmTxOlGGeLZ8tcdnXeiP9AFEBrdu7D1vmG0oiCG5mZTIAU1rX4nAD5L6b c6XWsSTovOchwdDrUDwzDn0Mr5fkv0YvLIvjotloYW20djEdMf79VGAtzt4DzIamnP8d1Q97f 8hUgjidch7lm8fiyl4eUnK+Ym2AglCScvMb+uSjzgePzs3pZKflJRqPiJQQ6i2CnbbXtub/cZ F76fs70SSCe/Y8UzZs3C1ILaellYJF8nkDQ0zqXrRJO1FsWm7a4NB2B/6cj+EDZQKIFThUrSs N7UcvCgKrynf4n5nIoWyhDoC/bkzKygWRjCc+AGiQW9F6n44nic8Us3QEWdIbFSujRK3jqvHR TASt8Lc9EaFWL1bFzekPpP2O7uBIEMXZ8AuBwpvRdwUr5W/WpnvWLhOL7wJZ63dqiJnnw/8xw L32qUyzPn+DM4Z38GPCuwrndqKBHHYMvXchgfOlDzNSQIDjesyygL9QuyPPiFennFSuekNJgC cRAWCXwLn/57RPw5gSny1gPW1m5pPxv5I/lAcc1M5rSRK Precedence: bulk List-ID: X-Mailing-List: linux-i2c@vger.kernel.org To make the code easier to understand, add longer names to the definitions of register fields. These longer names are based on source code published by DELL/AESS for WPCM450, but should apply just as well to NPCM7xx and NPCM8xx. Signed-off-by: Jonathan Neuschäfer Reviewed-by: Tali Perry --- drivers/i2c/busses/i2c-npcm7xx.c | 56 ++++++++++++++++---------------- 1 file changed, 28 insertions(+), 28 deletions(-) -- 2.35.1 diff --git a/drivers/i2c/busses/i2c-npcm7xx.c b/drivers/i2c/busses/i2c-npcm7xx.c index 9a7a2d0bf5765..bbc7359e67f74 100644 --- a/drivers/i2c/busses/i2c-npcm7xx.c +++ b/drivers/i2c/busses/i2c-npcm7xx.c @@ -146,50 +146,50 @@ static const int npcm_i2caddr[I2C_NUM_OWN_ADDR] = { #endif /* NPCM_I2CST reg fields */ -#define NPCM_I2CST_XMIT BIT(0) -#define NPCM_I2CST_MASTER BIT(1) -#define NPCM_I2CST_NMATCH BIT(2) -#define NPCM_I2CST_STASTR BIT(3) -#define NPCM_I2CST_NEGACK BIT(4) -#define NPCM_I2CST_BER BIT(5) -#define NPCM_I2CST_SDAST BIT(6) -#define NPCM_I2CST_SLVSTP BIT(7) +#define NPCM_I2CST_XMIT BIT(0) /* Transmit mode */ +#define NPCM_I2CST_MASTER BIT(1) /* Master mode */ +#define NPCM_I2CST_NMATCH BIT(2) /* New match */ +#define NPCM_I2CST_STASTR BIT(3) /* Stall after start */ +#define NPCM_I2CST_NEGACK BIT(4) /* Negative ACK */ +#define NPCM_I2CST_BER BIT(5) /* Bus error */ +#define NPCM_I2CST_SDAST BIT(6) /* SDA status */ +#define NPCM_I2CST_SLVSTP BIT(7) /* Slave stop */ /* NPCM_I2CCST reg fields */ -#define NPCM_I2CCST_BUSY BIT(0) -#define NPCM_I2CCST_BB BIT(1) -#define NPCM_I2CCST_MATCH BIT(2) -#define NPCM_I2CCST_GCMATCH BIT(3) -#define NPCM_I2CCST_TSDA BIT(4) -#define NPCM_I2CCST_TGSCL BIT(5) -#define NPCM_I2CCST_MATCHAF BIT(6) -#define NPCM_I2CCST_ARPMATCH BIT(7) +#define NPCM_I2CCST_BUSY BIT(0) /* Busy */ +#define NPCM_I2CCST_BB BIT(1) /* Bus busy */ +#define NPCM_I2CCST_MATCH BIT(2) /* Address match */ +#define NPCM_I2CCST_GCMATCH BIT(3) /* Global call match */ +#define NPCM_I2CCST_TSDA BIT(4) /* Test SDA line */ +#define NPCM_I2CCST_TGSCL BIT(5) /* Toggle SCL line */ +#define NPCM_I2CCST_MATCHAF BIT(6) /* Match address field */ +#define NPCM_I2CCST_ARPMATCH BIT(7) /* ARP address match */ /* NPCM_I2CCTL1 reg fields */ -#define NPCM_I2CCTL1_START BIT(0) -#define NPCM_I2CCTL1_STOP BIT(1) -#define NPCM_I2CCTL1_INTEN BIT(2) +#define NPCM_I2CCTL1_START BIT(0) /* Generate start condition */ +#define NPCM_I2CCTL1_STOP BIT(1) /* Generate stop condition */ +#define NPCM_I2CCTL1_INTEN BIT(2) /* Interrupt enable */ #define NPCM_I2CCTL1_EOBINTE BIT(3) #define NPCM_I2CCTL1_ACK BIT(4) -#define NPCM_I2CCTL1_GCMEN BIT(5) -#define NPCM_I2CCTL1_NMINTE BIT(6) -#define NPCM_I2CCTL1_STASTRE BIT(7) +#define NPCM_I2CCTL1_GCMEN BIT(5) /* Global call match enable */ +#define NPCM_I2CCTL1_NMINTE BIT(6) /* New match interrupt enable */ +#define NPCM_I2CCTL1_STASTRE BIT(7) /* Stall after start enable */ /* RW1S fields (inside a RW reg): */ #define NPCM_I2CCTL1_RWS \ (NPCM_I2CCTL1_START | NPCM_I2CCTL1_STOP | NPCM_I2CCTL1_ACK) /* npcm_i2caddr reg fields */ -#define NPCM_I2CADDR_A GENMASK(6, 0) -#define NPCM_I2CADDR_SAEN BIT(7) +#define NPCM_I2CADDR_A GENMASK(6, 0) /* Address */ +#define NPCM_I2CADDR_SAEN BIT(7) /* Slave address enable */ /* NPCM_I2CCTL2 reg fields */ -#define I2CCTL2_ENABLE BIT(0) -#define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) +#define I2CCTL2_ENABLE BIT(0) /* Module enable */ +#define I2CCTL2_SCLFRQ6_0 GENMASK(7, 1) /* Bits 0:6 of frequency divisor */ /* NPCM_I2CCTL3 reg fields */ -#define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) -#define I2CCTL3_ARPMEN BIT(2) +#define I2CCTL3_SCLFRQ8_7 GENMASK(1, 0) /* Bits 7:8 of frequency divisor */ +#define I2CCTL3_ARPMEN BIT(2) /* ARP match enable */ #define I2CCTL3_IDL_START BIT(3) #define I2CCTL3_400K_MODE BIT(4) #define I2CCTL3_BNK_SEL BIT(5)