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Date: Tue, 4 Oct 2022 13:18:45 +0530 Message-ID: <20221004074845.29583-1-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT101:EE_|CH2PR12MB5004:EE_ X-MS-Office365-Filtering-Correlation-Id: 2691a36a-f153-4fdd-006c-08daa5dce4c2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: k1Ber+dt5LE3x7wUZFcLBSij8JsqmCvBNk1Qev+XUf3ux7rMvKZ0UICuXI8RizsE29Z2Eza5V6F/oFHqzImLrHJY2MN/k21C6mcAPX/SaWY8Te767cbXMlpj1lLc76mMk0fD+lQ7C6huX50MmSXkSwYtoDH2VA+P4QsxIXPe+J3+fCvxScTZug5NUSq4arrcs0ZJzKCyq+J1EtSGdmQABmwKQ3z2+bpZA8136YZ5LX2GoWuiVcOuEvcdfb7KQIbJS1sv9MXa7Nyke++2ULBX3cw3m4j1w6V3yM1oCZSW3oV4nTkY9S47ZvQZTs6yvFjlQ73ul9eOhnDwsuJmCLG4a5yJ4VzW0qDIYpSL8pbds3odrNeyHh2BtqwSj3AxX/pntvKw1wfBtSZ3CvFDU4xsbTU1NPoPzLYTaadhhAEMXsxoOQAXbYIJDMbhtoAzwd8j6ZzUngZM8jPuiXlAkTJDJfATDQyRCiaOlJVyM01VNKVGKlmp9OfBFOlZCsiHvoxMqA7LB0f/IHpPpQycxPoi5JFGJVqkOfItBlrmhXhaNk8gPPUnUCuVsXM6R9FucbF4PVioyQvylel6GM6JOWo3TKAhlPG3aW4hDCrLQFF0kxptm32yCKvFlwqPE9SXo70Ph4vYlYVuhM/jD1fGAP3SY6IaQZ6MjiRkqq7REJyxcyrqKBTDQAE4ST4wloE1GdPsmJSsN/Ja8an60DvirDyHKos4qX5nmC3LG6DwEXre8UIkmF3tFypPfWEMIsjj0GxV+yXeB9uD15M/3Pnz/1lw7g== X-Forefront-Antispam-Report: CIP:216.228.118.233; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc7edge2.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(136003)(396003)(39860400002)(346002)(376002)(451199015)(36840700001)(40470700004)(46966006)(1076003)(186003)(2616005)(356005)(82310400005)(2906002)(316002)(36756003)(70206006)(107886003)(6666004)(40460700003)(70586007)(54906003)(478600001)(110136005)(41300700001)(8676002)(4326008)(336012)(7636003)(40480700001)(86362001)(7696005)(8936002)(26005)(5660300002)(426003)(47076005)(82740400003)(83380400001)(36860700001); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2022 07:48:57.3622 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 2691a36a-f153-4fdd-006c-08daa5dce4c2 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.118.233]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT101.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB5004 Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org This change checks if we have the necessary permission to access the GPIO. For devices that have support for virtualisation we need to check both the TEGRA186_GPIO_VM_REG and the TEGRA186_GPIO_SCR_REG registers. For device that do not have virtualisation support for GPIOs we only need to check the TEGRA186_GPIO_SCR_REG register. Signed-off-by: Manish Bhardwaj Signed-off-by: Prathamesh Shete Acked-by: Thierry Reding --- drivers/gpio/gpio-tegra186.c | 74 ++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) diff --git a/drivers/gpio/gpio-tegra186.c b/drivers/gpio/gpio-tegra186.c index 54d9fa7da9c1..34b6c287d608 100644 --- a/drivers/gpio/gpio-tegra186.c +++ b/drivers/gpio/gpio-tegra186.c @@ -26,6 +26,22 @@ #define TEGRA186_GPIO_INT_ROUTE_MAPPING(p, x) (0x14 + (p) * 0x20 + (x) * 4) +#define TEGRA186_GPIO_VM 0x00 +#define TEGRA186_GPIO_VM_RW_MASK 0x03 +#define TEGRA186_GPIO_SCR 0x04 +#define TEGRA186_GPIO_SCR_PIN_SIZE 0x08 +#define TEGRA186_GPIO_SCR_PORT_SIZE 0x40 +#define TEGRA186_GPIO_SCR_SEC_WEN BIT(28) +#define TEGRA186_GPIO_SCR_SEC_REN BIT(27) +#define TEGRA186_GPIO_SCR_SEC_G1W BIT(9) +#define TEGRA186_GPIO_SCR_SEC_G1R BIT(1) +#define TEGRA186_GPIO_FULL_ACCESS (TEGRA186_GPIO_SCR_SEC_WEN | \ + TEGRA186_GPIO_SCR_SEC_REN | \ + TEGRA186_GPIO_SCR_SEC_G1R | \ + TEGRA186_GPIO_SCR_SEC_G1W) +#define TEGRA186_GPIO_SCR_SEC_ENABLE (TEGRA186_GPIO_SCR_SEC_WEN | \ + TEGRA186_GPIO_SCR_SEC_REN) + /* control registers */ #define TEGRA186_GPIO_ENABLE_CONFIG 0x00 #define TEGRA186_GPIO_ENABLE_CONFIG_ENABLE BIT(0) @@ -77,6 +93,7 @@ struct tegra_gpio_soc { unsigned int num_irqs_per_bank; const struct tegra186_pin_range *pin_ranges; + bool has_vm_support; unsigned int num_pin_ranges; const char *pinmux; bool has_gte; @@ -129,6 +146,58 @@ static void __iomem *tegra186_gpio_get_base(struct tegra_gpio *gpio, return gpio->base + offset + pin * 0x20; } +static void __iomem *tegra186_gpio_get_secure_base(struct tegra_gpio *gpio, + unsigned int pin) +{ + const struct tegra_gpio_port *port; + unsigned int offset; + + port = tegra186_gpio_get_port(gpio, &pin); + if (!port) + return NULL; + + offset = port->bank * 0x1000 + port->port * TEGRA186_GPIO_SCR_PORT_SIZE; + + return gpio->secure + offset + pin * TEGRA186_GPIO_SCR_PIN_SIZE; +} + +static inline bool tegra186_gpio_is_accessible(struct tegra_gpio *gpio, u32 pin) +{ + void __iomem *secure; + u32 val; + + secure = tegra186_gpio_get_secure_base(gpio, pin); + + if (gpio->soc->has_vm_support) { + val = readl(secure + TEGRA186_GPIO_VM); + if ((val & TEGRA186_GPIO_VM_RW_MASK) != TEGRA186_GPIO_VM_RW_MASK) + return false; + } + + val = __raw_readl(secure + TEGRA186_GPIO_SCR); + + if ((val & TEGRA186_GPIO_SCR_SEC_ENABLE) == 0) + return true; + + if ((val & TEGRA186_GPIO_FULL_ACCESS) == TEGRA186_GPIO_FULL_ACCESS) + return true; + + return false; +} + +static int tegra186_init_valid_mask(struct gpio_chip *chip, + unsigned long *valid_mask, unsigned int ngpios) +{ + struct tegra_gpio *gpio = gpiochip_get_data(chip); + int j; + + for (j = 0; j < ngpios; j++) { + if (!tegra186_gpio_is_accessible(gpio, j)) + clear_bit(j, valid_mask); + } + return 0; +} + static int tegra186_gpio_get_direction(struct gpio_chip *chip, unsigned int offset) { @@ -763,6 +832,7 @@ static int tegra186_gpio_probe(struct platform_device *pdev) gpio->soc = device_get_match_data(&pdev->dev); gpio->gpio.label = gpio->soc->name; gpio->gpio.parent = &pdev->dev; + gpio->gpio.init_valid_mask = tegra186_init_valid_mask; /* count the number of banks in the controller */ for (i = 0; i < gpio->soc->num_ports; i++) @@ -1042,6 +1112,7 @@ static const struct tegra_gpio_soc tegra194_main_soc = { .num_pin_ranges = ARRAY_SIZE(tegra194_main_pin_ranges), .pin_ranges = tegra194_main_pin_ranges, .pinmux = "nvidia,tegra194-pinmux", + .has_vm_support = true, }; #define TEGRA194_AON_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -1067,6 +1138,7 @@ static const struct tegra_gpio_soc tegra194_aon_soc = { .instance = 1, .num_irqs_per_bank = 8, .has_gte = true, + .has_vm_support = false, }; #define TEGRA234_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -1111,6 +1183,7 @@ static const struct tegra_gpio_soc tegra234_main_soc = { .name = "tegra234-gpio", .instance = 0, .num_irqs_per_bank = 8, + .has_vm_support = true, }; #define TEGRA234_AON_GPIO_PORT(_name, _bank, _port, _pins) \ @@ -1136,6 +1209,7 @@ static const struct tegra_gpio_soc tegra234_aon_soc = { .name = "tegra234-gpio-aon", .instance = 1, .num_irqs_per_bank = 8, + .has_vm_support = false, }; #define TEGRA241_MAIN_GPIO_PORT(_name, _bank, _port, _pins) \