From patchwork Sat Feb 23 13:06:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159111 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33084jad; Sat, 23 Feb 2019 05:07:58 -0800 (PST) X-Google-Smtp-Source: AHgI3IbvJTqKznbKuvFQL4h0xt5xhiVobq/Aoo/innOjxvUlrRRANmTRprRhfD7z0oP/CL3RwPNj X-Received: by 2002:a17:902:207:: with SMTP id 7mr9211537plc.142.1550927278360; Sat, 23 Feb 2019 05:07:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927278; cv=none; d=google.com; s=arc-20160816; b=VhX//R2ifx0IJvNg+fwj+JAd9F1z67avGOU+cqA+VL/c+A7ZX/HBwzDbGREnQJEcFr 11DBcoeNYgGrlFNJ4QOennnd21RBLVHPLuQ60LBw4Z7QC9RI3mSs0WAmDTTR4RwPZIyM YPNhvUk1pHAHWgdmzQA2SaPhHD5whQV5Z0bVhmy6xZoE7LaTtE/tGSCLxTQARMbKG4lG 0jyG4vs1YAwoQvYSZKIaT9gmBv8D+ju+5kTBLLcQbH61Qj/QqRupaXfAJdSD3uqmUdcR ucbxfJSGYUDT9HSwVwCVFFN2nWnw193WMAiBbgWYiFvLILB/2gf8UAJXjHhrQt3BxFjp ZHjA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=AKSyCQMNYBv5nWh/KBmSW8hTM6N2dO+8FV84ST3V3Mk=; b=whuUvNjsHsdQXDoDXpXM/EcApjC2Ogbs8+9xtlcWlnx7vWQriKZ5OBq3pC4iDWaN4R vvk/OW2ZKB1GrXxs5d+7zpBFi8uESn03OZkEp2cBmDhvOcwbqiNS2XKp+dP9pmGNh3y3 sJVmsvav+5RX6mbGHYOzs+vGwkvxQCB+H8QjcV0mTEvt5IfgR1iykGhFS+7xbmmX7n/G nqYlswy+yQV3OdJY9KstiQw/55RdDJJp40rXuNoMetmGhvdmjvUrJ1fs7w4ZhqhrX7Pg h8TXZHdIX2pRBx5ycr4WDb56nK2zxrLZVCqH+Gc8QkatMkDJpFju8tpubZSBVioKdGF8 q2+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FweXRpwO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.07.52 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:07:52 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Chen-Yu Tsai , Maxime Ripard , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Allwinner sunXi SoC support) Subject: [PATCH 01/18] clocksource/drivers/sun5i: Fail gracefully when clock rate is unavailable Date: Sat, 23 Feb 2019 14:06:49 +0100 Message-Id: <20190223130707.16704-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Chen-Yu Tsai If the clock tree is not fully populated when the timer-sun5i init code is called, attempts to get the clock rate for the timer would fail and return 0. Make the init code for both clock events and clocksource check the returned clock rate and fail gracefully if the result is 0, instead of causing a divide by 0 exception later on. Fixes: 4a59058f0b09 ("clocksource/drivers/sun5i: Refactor the current code") Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-sun5i.c | 10 ++++++++++ 1 file changed, 10 insertions(+) -- 2.17.1 diff --git a/drivers/clocksource/timer-sun5i.c b/drivers/clocksource/timer-sun5i.c index 3b56ea3f52af..552c5254390c 100644 --- a/drivers/clocksource/timer-sun5i.c +++ b/drivers/clocksource/timer-sun5i.c @@ -202,6 +202,11 @@ static int __init sun5i_setup_clocksource(struct device_node *node, } rate = clk_get_rate(clk); + if (!rate) { + pr_err("Couldn't get parent clock rate\n"); + ret = -EINVAL; + goto err_disable_clk; + } cs->timer.base = base; cs->timer.clk = clk; @@ -275,6 +280,11 @@ static int __init sun5i_setup_clockevent(struct device_node *node, void __iomem } rate = clk_get_rate(clk); + if (!rate) { + pr_err("Couldn't get parent clock rate\n"); + ret = -EINVAL; + goto err_disable_clk; + } ce->timer.base = base; ce->timer.ticks_per_jiffy = DIV_ROUND_UP(rate, HZ); From patchwork Sat Feb 23 13:06:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159112 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33138jad; Sat, 23 Feb 2019 05:08:02 -0800 (PST) X-Google-Smtp-Source: AHgI3IZYYioHpFEpubXUQgAzGsuk75o8yCRWj3WoQZX3/OyEFJNJYD54sZ6yockmpp9TpNDil965 X-Received: by 2002:a17:902:e01:: with SMTP id 1mr9138977plw.251.1550927282339; Sat, 23 Feb 2019 05:08:02 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927282; cv=none; d=google.com; s=arc-20160816; b=f194TB5waEKGB2MkNANz2D487t4qdTYea/KyrpgJaiweVbo4DvoyJz0GmAIvxHLX4Y mLyMnSwEiSxpKXjjhZ/XmyFsFOY4qNiYvHlJ5gtr/Zqy88WiL83kZewhYjaqr8IJplV0 4MjoSLYkGtRXbV1NoX5jnPiOVOYC2ISFB69fc2I6ECjmldCfg1s4fsL4ErmmR5VOAJ2P eCQlnkyQ5TxyDXFKlLs26M1xonqbBc5sl9tNnoIdOls5Ru4WWmG8cW9ffzvO6PZuFoJx 9DIQ5uaBF/KBrE68ud2EIhAj5dVu5oVBu2RGMUD8NltDO8JDn3kJ7xzyFAjQRYVz0sDL 192g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=TCClcj1oSiSPcPMDubqhYNK1kcD8iCYJHgBypgIkPDM=; b=qYUqozbI5t2uoFDut9ekJffKsQcqRam0uW6GtQcBavkAI7UbIMIgm2epi1jESCQsEK H82EEjik5S5b8rLX9HU5StRSKl9vmOsGducZJxhVmbV8S7jEuYEdmX6qLbbNo0F5JuAb UYkLFOA7X3mT3rXLZLU3dVYJ7EuVORBgX6XL4XqBltyKGTRNZxUCIV9dk9BZvSYa6V8M YFAfsaHCpeivAXRk9+Rpr5pTZr/7HR+ha633sxaKLnbM/fjuJTO5tJETMLq6lmM4p3/u /SFtYky9zKaPNe/7GfDXWZFdN1nM3l+G9VseG0dLuhp4UW3JRxEmlAa/YHtfsp3mKgvi 9aMw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o4YHW4xg; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.07.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:07:55 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Samuel Holland , stable@vger.kernel.org, Maxime Ripard , Andre Przywara , Catalin Marinas , Will Deacon , Jonathan Corbet , Mark Rutland , Marc Zyngier , linux-arm-kernel@lists.infradead.org (moderated list:ARM64 PORT (AARCH64 ARCHITECTURE)), linux-doc@vger.kernel.org (open list:DOCUMENTATION) Subject: [PATCH 02/18] clocksource/drivers/arch_timer: Workaround for Allwinner A64 timer instability Date: Sat, 23 Feb 2019 14:06:50 +0100 Message-Id: <20190223130707.16704-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> MIME-Version: 1.0 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Samuel Holland The Allwinner A64 SoC is known[1] to have an unstable architectural timer, which manifests itself most obviously in the time jumping forward a multiple of 95 years[2][3]. This coincides with 2^56 cycles at a timer frequency of 24 MHz, implying that the time went slightly backward (and this was interpreted by the kernel as it jumping forward and wrapping around past the epoch). Investigation revealed instability in the low bits of CNTVCT at the point a high bit rolls over. This leads to power-of-two cycle forward and backward jumps. (Testing shows that forward jumps are about twice as likely as backward jumps.) Since the counter value returns to normal after an indeterminate read, each "jump" really consists of both a forward and backward jump from the software perspective. Unless the kernel is trapping CNTVCT reads, a userspace program is able to read the register in a loop faster than it changes. A test program running on all 4 CPU cores that reported jumps larger than 100 ms was run for 13.6 hours and reported the following: Count | Event -------+--------------------------- 9940 | jumped backward 699ms 268 | jumped backward 1398ms 1 | jumped backward 2097ms 16020 | jumped forward 175ms 6443 | jumped forward 699ms 2976 | jumped forward 1398ms 9 | jumped forward 356516ms 9 | jumped forward 357215ms 4 | jumped forward 714430ms 1 | jumped forward 3578440ms This works out to a jump larger than 100 ms about every 5.5 seconds on each CPU core. The largest jump (almost an hour!) was the following sequence of reads: 0x0000007fffffffff → 0x00000093feffffff → 0x0000008000000000 Note that the middle bits don't necessarily all read as all zeroes or all ones during the anomalous behavior; however the low 10 bits checked by the function in this patch have never been observed with any other value. Also note that smaller jumps are much more common, with backward jumps of 2048 (2^11) cycles observed over 400 times per second on each core. (Of course, this is partially explained by lower bits rolling over more frequently.) Any one of these could have caused the 95 year time skip. Similar anomalies were observed while reading CNTPCT (after patching the kernel to allow reads from userspace). However, the CNTPCT jumps are much less frequent, and only small jumps were observed. The same program as before (except now reading CNTPCT) observed after 72 hours: Count | Event -------+--------------------------- 17 | jumped backward 699ms 52 | jumped forward 175ms 2831 | jumped forward 699ms 5 | jumped forward 1398ms Further investigation showed that the instability in CNTPCT/CNTVCT also affected the respective timer's TVAL register. The following values were observed immediately after writing CNVT_TVAL to 0x10000000: CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error --------------------+------------+--------------------+----------------- 0x000000d4a2d8bfff | 0x10003fff | 0x000000d4b2d8bfff | +0x00004000 0x000000d4a2d94000 | 0x0fffffff | 0x000000d4b2d97fff | -0x00004000 0x000000d4a2d97fff | 0x10003fff | 0x000000d4b2d97fff | +0x00004000 0x000000d4a2d9c000 | 0x0fffffff | 0x000000d4b2d9ffff | -0x00004000 The pattern of errors in CNTV_TVAL seemed to depend on exactly which value was written to it. For example, after writing 0x10101010: CNTVCT | CNTV_TVAL | CNTV_CVAL | CNTV_TVAL Error --------------------+------------+--------------------+----------------- 0x000001ac3effffff | 0x1110100f | 0x000001ac4f10100f | +0x1000000 0x000001ac40000000 | 0x1010100f | 0x000001ac5110100f | -0x1000000 0x000001ac58ffffff | 0x1110100f | 0x000001ac6910100f | +0x1000000 0x000001ac66000000 | 0x1010100f | 0x000001ac7710100f | -0x1000000 0x000001ac6affffff | 0x1110100f | 0x000001ac7b10100f | +0x1000000 0x000001ac6e000000 | 0x1010100f | 0x000001ac7f10100f | -0x1000000 I was also twice able to reproduce the issue covered by Allwinner's workaround[4], that writing to TVAL sometimes fails, and both CVAL and TVAL are left with entirely bogus values. One was the following values: CNTVCT | CNTV_TVAL | CNTV_CVAL --------------------+------------+-------------------------------------- 0x000000d4a2d6014c | 0x8fbd5721 | 0x000000d132935fff (615s in the past) Reviewed-by: Marc Zyngier -- 2.17.1 ======================================================================== Because the CPU can read the CNTPCT/CNTVCT registers faster than they change, performing two reads of the register and comparing the high bits (like other workarounds) is not a workable solution. And because the timer can jump both forward and backward, no pair of reads can distinguish a good value from a bad one. The only way to guarantee a good value from consecutive reads would be to read _three_ times, and take the middle value only if the three values are 1) each unique and 2) increasing. This takes at minimum 3 counter cycles (125 ns), or more if an anomaly is detected. However, since there is a distinct pattern to the bad values, we can optimize the common case (1022/1024 of the time) to a single read by simply ignoring values that match the error pattern. This still takes no more than 3 cycles in the worst case, and requires much less code. As an additional safety check, we still limit the loop iteration to the number of max-frequency (1.2 GHz) CPU cycles in three 24 MHz counter periods. For the TVAL registers, the simple solution is to not use them. Instead, read or write the CVAL and calculate the TVAL value in software. Although the manufacturer is aware of at least part of the erratum[4], there is no official name for it. For now, use the kernel-internal name "UNKNOWN1". [1]: https://github.com/armbian/build/commit/a08cd6fe7ae9 [2]: https://forum.armbian.com/topic/3458-a64-datetime-clock-issue/ [3]: https://irclog.whitequark.org/linux-sunxi/2018-01-26 [4]: https://github.com/Allwinner-Homlet/H6-BSP4.9-linux/blob/master/drivers/clocksource/arm_arch_timer.c#L272 Acked-by: Maxime Ripard Tested-by: Andre Przywara Signed-off-by: Samuel Holland Cc: stable@vger.kernel.org Signed-off-by: Daniel Lezcano Signed-off-by: Daniel Lezcano --- Documentation/arm64/silicon-errata.txt | 2 + drivers/clocksource/Kconfig | 10 +++++ drivers/clocksource/arm_arch_timer.c | 55 ++++++++++++++++++++++++++ 3 files changed, 67 insertions(+) diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt index 1f09d043d086..ddb8ce5333ba 100644 --- a/Documentation/arm64/silicon-errata.txt +++ b/Documentation/arm64/silicon-errata.txt @@ -44,6 +44,8 @@ stable kernels. | Implementor | Component | Erratum ID | Kconfig | +----------------+-----------------+-----------------+-----------------------------+ +| Allwinner | A64/R18 | UNKNOWN1 | SUN50I_ERRATUM_UNKNOWN1 | +| | | | | | ARM | Cortex-A53 | #826319 | ARM64_ERRATUM_826319 | | ARM | Cortex-A53 | #827319 | ARM64_ERRATUM_827319 | | ARM | Cortex-A53 | #824069 | ARM64_ERRATUM_824069 | diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index a9e26f6a81a1..8dfd3bc448d0 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -360,6 +360,16 @@ config ARM64_ERRATUM_858921 The workaround will be dynamically enabled when an affected core is detected. +config SUN50I_ERRATUM_UNKNOWN1 + bool "Workaround for Allwinner A64 erratum UNKNOWN1" + default y + depends on ARM_ARCH_TIMER && ARM64 && ARCH_SUNXI + select ARM_ARCH_TIMER_OOL_WORKAROUND + help + This option enables a workaround for instability in the timer on + the Allwinner A64 SoC. The workaround will only be active if the + allwinner,erratum-unknown1 property is found in the timer node. + config ARM_GLOBAL_TIMER bool "Support for the ARM global timer" if COMPILE_TEST select TIMER_OF if OF diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 9a7d4dc00b6e..a8b20b65bd4b 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -326,6 +326,48 @@ static u64 notrace arm64_1188873_read_cntvct_el0(void) } #endif +#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1 +/* + * The low bits of the counter registers are indeterminate while bit 10 or + * greater is rolling over. Since the counter value can jump both backward + * (7ff -> 000 -> 800) and forward (7ff -> fff -> 800), ignore register values + * with all ones or all zeros in the low bits. Bound the loop by the maximum + * number of CPU cycles in 3 consecutive 24 MHz counter periods. + */ +#define __sun50i_a64_read_reg(reg) ({ \ + u64 _val; \ + int _retries = 150; \ + \ + do { \ + _val = read_sysreg(reg); \ + _retries--; \ + } while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \ + \ + WARN_ON_ONCE(!_retries); \ + _val; \ +}) + +static u64 notrace sun50i_a64_read_cntpct_el0(void) +{ + return __sun50i_a64_read_reg(cntpct_el0); +} + +static u64 notrace sun50i_a64_read_cntvct_el0(void) +{ + return __sun50i_a64_read_reg(cntvct_el0); +} + +static u32 notrace sun50i_a64_read_cntp_tval_el0(void) +{ + return read_sysreg(cntp_cval_el0) - sun50i_a64_read_cntpct_el0(); +} + +static u32 notrace sun50i_a64_read_cntv_tval_el0(void) +{ + return read_sysreg(cntv_cval_el0) - sun50i_a64_read_cntvct_el0(); +} +#endif + #ifdef CONFIG_ARM_ARCH_TIMER_OOL_WORKAROUND DEFINE_PER_CPU(const struct arch_timer_erratum_workaround *, timer_unstable_counter_workaround); EXPORT_SYMBOL_GPL(timer_unstable_counter_workaround); @@ -423,6 +465,19 @@ static const struct arch_timer_erratum_workaround ool_workarounds[] = { .read_cntvct_el0 = arm64_1188873_read_cntvct_el0, }, #endif +#ifdef CONFIG_SUN50I_ERRATUM_UNKNOWN1 + { + .match_type = ate_match_dt, + .id = "allwinner,erratum-unknown1", + .desc = "Allwinner erratum UNKNOWN1", + .read_cntp_tval_el0 = sun50i_a64_read_cntp_tval_el0, + .read_cntv_tval_el0 = sun50i_a64_read_cntv_tval_el0, + .read_cntpct_el0 = sun50i_a64_read_cntpct_el0, + .read_cntvct_el0 = sun50i_a64_read_cntvct_el0, + .set_next_event_phys = erratum_set_next_event_tval_phys, + .set_next_event_virt = erratum_set_next_event_tval_virt, + }, +#endif }; typedef bool (*ate_match_fn_t)(const struct arch_timer_erratum_workaround *, From patchwork Sat Feb 23 13:06:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159113 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33180jad; Sat, 23 Feb 2019 05:08:05 -0800 (PST) X-Google-Smtp-Source: AHgI3IYi+nDDeaEpyInJrx5UGwRqYc67vDXbHhQ/w3kxJEl9JIzVpyJZAhgcf1OqTS1+RJmUArS2 X-Received: by 2002:a63:c04b:: with SMTP id z11mr8645632pgi.135.1550927285308; Sat, 23 Feb 2019 05:08:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927285; cv=none; d=google.com; s=arc-20160816; b=AEmvrEPpOYCeOpTXBEA//brKHWyWVer45asfGYRWnlOtLZEgSpdUbssnWdMAaIPlh8 t+tY0ubCyn/Ps2bpFWpBlnkKYDXNXHoDd791HrCr1hJ8+toTMqeCVEXWQRiHe7q8bbQg hlQxQEMVFySVl4tidZjllI3srqkv4BXYNNUekG8cMzYTSK0k76cqnUziIDkjXteR+9EY /XZNwFENFGLg08XR4rkWVWcgpc5+itQ1oNyM/wigcpYKtMQNmZC8fTCnLzuwydOpPqha 0tv5nFehff1imXrW9zLCIHrLS6ApSb15l5fxxGV6o1QOsZqxjDfzfkRqpkuf2F9O299O EnmA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=1aU82OCB8EaU5gSyx1GLNfzRZ/n+CtM0wF3xQO3ltdE=; b=O3ari3bg3H9l8bUmu34zyBFc3wkTlZtlSy8I5+ZDCnF7rtRlmYWrdmo7uF9oJEIMcF YdBg5JM7T0t4gMRrYl+KDdXLwwfZYOVF9ePtnXLxKRkRm/nNS6PJLpeASt/77TSezfVu 3+a/Iaj+wynck2iUpgwDxcKAgIRVBwajskbz/TXmFyYdfPNzHXhWYywy88bYqA9cNsHe 1q9QtGw4CovCG65yBsJ6xEJxmFWQ5Tci3BS6Ogdh9NoMDHQ6vEN71lYFarZAdp8Y5/2q U4JfcDvL5rlnH8tWAW3uaMUYPsM/yPCZ/OEnzHHZL07dw35A9uG9WNCwZu9jRSB+dpou HDyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="qSVc/DD1"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.07.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:07:59 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Stuart Menefy , stable@vger.kernel.org, Marek Szyprowski , Kukjin Kim , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES) Subject: [PATCH 04/18] clocksource/drivers/exynos_mct: Clear timer interrupt when shutdown Date: Sat, 23 Feb 2019 14:06:52 +0100 Message-Id: <20190223130707.16704-4-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Stuart Menefy When shutting down the timer, ensure that after we have stopped the timer any pending interrupts are cleared. This fixes a problem when suspending, as interrupts are disabled before the timer is stopped, so the timer interrupt may still be asserted, preventing the system entering a low power state when the wfi is executed. Signed-off-by: Stuart Menefy Reviewed-by: Krzysztof Kozlowski Tested-by: Marek Szyprowski Cc: # v4.3+ Signed-off-by: Daniel Lezcano --- drivers/clocksource/exynos_mct.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 1e325f89d408..d55c30f6981d 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -411,6 +411,7 @@ static int set_state_shutdown(struct clock_event_device *evt) mevt = container_of(evt, struct mct_clock_event_device, evt); exynos4_mct_tick_stop(mevt); + exynos4_mct_tick_clear(mevt); return 0; } From patchwork Sat Feb 23 13:06:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159126 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp34317jad; Sat, 23 Feb 2019 05:09:12 -0800 (PST) X-Google-Smtp-Source: AHgI3IYxNPqWFEUsSjAZK4UsKRWm+38fIRbN3zCMeq9g8wa9I6B1YVS6GpkMWD/TIgBviYGA5AQM X-Received: by 2002:a63:2682:: with SMTP id m124mr8597258pgm.35.1550927352196; Sat, 23 Feb 2019 05:09:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927352; cv=none; d=google.com; s=arc-20160816; b=fwefpoYhQivvdjAEccYbHn4ZIvDRftMVyZWGmbHuyEq43tJoiG9T9eZUbKDiGf3QJI hkxODsvkTckaDpivBeCgGrn+RpSa0h8V3Z0XvxzorDRd/sX01snqMaR/TtlVO77Sr2jf e7XlBtKQgiZs+x8E2U65/W0eO9Tep9HVLXHSJzScNmc9kwlRdkYrVM2t81T1P0EgG8/Y 9h8oHPuzShawJZXDu89CZIgrRBeRL0rN0qv4KnOdzdT0DuTKEp7ht4hKkYSfSKZB+d2c yNILeVE5j68s85jyxeoip2wHcEPRpvVLh7EAE8720U+OMyphrq9LvDPVmKTYX9bDvliu ZC3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=4hvqmBcDEXpGFW/EoS27NZ2ZFW8t9Sep0ptzXoc9+DY=; b=GLvP9S6Dxi2xjVN5wOg69qm5YNsWN5udpTRtHzuWqor4Z2enwiyedruSS2YLil4pm2 bIZzsBNNfoxYItdb523wv1UMggzTMQdeoSU+BHuQVKlqWmBdFLkq6K8tLAYCMHgTDp+A Q+xisD+EAwlCsFS90Y8nou1tjQTYBp6sJGkyHZ3p9a/+/wX0of3IqmrpwusUFywf8m4C FgV1QNF+0t4NulxlV38+EOubosEGfawpHrS/B3/wHhBuyYTPYUtCCeC/UOMJqrrzQofc ZmWOvt006gDCkzuzM2CUembDmyNaH7mkkLutZWztDz0wapESG4/hh0oxUYLa7tt14ODi Q6Hw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=F8YZWafT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.00 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:00 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Biju Das , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 05/18] dt-bindings: timer: renesas, cmt: Document r8a774c0 CMT support Date: Sat, 23 Feb 2019 14:06:53 +0100 Message-Id: <20190223130707.16704-5-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Biju Das Document SoC specific bindings for RZ/G2E (r8a774c0) SoC. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,cmt.txt | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/renesas,cmt.txt b/Documentation/devicetree/bindings/timer/renesas,cmt.txt index 862a80f0380a..c0594450e9ef 100644 --- a/Documentation/devicetree/bindings/timer/renesas,cmt.txt +++ b/Documentation/devicetree/bindings/timer/renesas,cmt.txt @@ -32,6 +32,8 @@ Required Properties: - "renesas,r8a77470-cmt1" for the 48-bit CMT1 device included in r8a77470. - "renesas,r8a774a1-cmt0" for the 32-bit CMT0 device included in r8a774a1. - "renesas,r8a774a1-cmt1" for the 48-bit CMT1 device included in r8a774a1. + - "renesas,r8a774c0-cmt0" for the 32-bit CMT0 device included in r8a774c0. + - "renesas,r8a774c0-cmt1" for the 48-bit CMT1 device included in r8a774c0. - "renesas,r8a7790-cmt0" for the 32-bit CMT0 device included in r8a7790. - "renesas,r8a7790-cmt1" for the 48-bit CMT1 device included in r8a7790. - "renesas,r8a7791-cmt0" for the 32-bit CMT0 device included in r8a7791. From patchwork Sat Feb 23 13:06:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159114 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33284jad; Sat, 23 Feb 2019 05:08:10 -0800 (PST) X-Google-Smtp-Source: AHgI3IYX9XeYt+7yNbB4uO8BLNCXx302tshoopIno8pujEreEpwJmcP7sj61KZLL//PFKtOpzVP1 X-Received: by 2002:a62:b511:: with SMTP id y17mr9389605pfe.199.1550927290815; Sat, 23 Feb 2019 05:08:10 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927290; cv=none; d=google.com; s=arc-20160816; b=wHBPgb3gHPHcj285ZmibpvhAubkPh/hqR6yqY1GqImacbj32/af07cC2Xw8pxrSje6 1EMjezrTFjKy/JGhVv4lgS/1aM76o1xSUEQ8kk7HXK/b/WI9pgfUCDxkNzA6d9n1bkg3 3nkJYzYzM3dQK0cRf+8Si4KGn5gguLVSxhEpbovOu63LiGP5oxYC5/oYaEFAK36ziCUU HULlAO9TIoSSRIGEw/qnXVs3skRQmVBAocWvOaSgniGd9/X015iWsnGj92ho8mUYju3N A0QEst1coeU0wCdqm73gYQF0FcV8wDiQIx2r3/8TFDkmPRRgxM616BY73Srgw/DYmEOr bizA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=UlLUZKsUBvvlpp0PaigJ6mdmQK3TFOW7gecu0d4T2EM=; b=j1r+W1O2BwKav6dXqzV4mtF/mC37ZfmRTSWYUgKwUAO0l5KnWfwO4J9N5YuHeqOBKa ZY5+bEUvJuBa6e8AfnzMCP9DNVDo7qWZoEBxmUWtjmFdRaKKUPnAWsMsz4pAyQiknnxd VC/EKOm1byX7scNw3Ib3s0P8GwgYZ9Oq0kSrF242A3oIea2Xwj2N8Wl+LBjbxuIcG2Py UX0jm+Toki1B1BKmBW/QAtDvvb/faUUw59OXLsmgMH5kAZYxyfeWmiXN3wueB4xYSK78 3ahu8TdUoH1031miTLex8gclX7hFvhnb7CTVQvx+aJKIfxOdSkItb0SrXwOdei+QEUc0 cN0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rpLLugPK; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:02 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Biju Das , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 06/18] dt-bindings: timer: renesas: tmu: Document r8a774c0 bindings Date: Sat, 23 Feb 2019 14:06:54 +0100 Message-Id: <20190223130707.16704-6-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Biju Das Document RZ/G2E (R8A774C0) SoC in the Renesas TMU bindings. Signed-off-by: Biju Das Reviewed-by: Geert Uytterhoeven Reviewed-by: Simon Horman Signed-off-by: Daniel Lezcano --- Documentation/devicetree/bindings/timer/renesas,tmu.txt | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/renesas,tmu.txt b/Documentation/devicetree/bindings/timer/renesas,tmu.txt index 4ddff85837da..13ad07416bdd 100644 --- a/Documentation/devicetree/bindings/timer/renesas,tmu.txt +++ b/Documentation/devicetree/bindings/timer/renesas,tmu.txt @@ -10,6 +10,7 @@ Required Properties: - compatible: must contain one or more of the following: - "renesas,tmu-r8a7740" for the r8a7740 TMU + - "renesas,tmu-r8a774c0" for the r8a774C0 TMU - "renesas,tmu-r8a7778" for the r8a7778 TMU - "renesas,tmu-r8a7779" for the r8a7779 TMU - "renesas,tmu-r8a77970" for the r8a77970 TMU From patchwork Sat Feb 23 13:06:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159127 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp34389jad; Sat, 23 Feb 2019 05:09:16 -0800 (PST) X-Google-Smtp-Source: AHgI3IbXSUgcoKOMuVTF8uzNV/vOJLPG1KSxt+YX51NThwxADTjvQui8bGFCzGbq4xzUdwSgzwps X-Received: by 2002:a62:ea10:: with SMTP id t16mr3135727pfh.3.1550927356585; Sat, 23 Feb 2019 05:09:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927356; cv=none; d=google.com; s=arc-20160816; b=BYd3rwTWcyldHivKw2yt8mcbSqUtQ6W5hHxfFkJk6zCUPRZ0wVkbN7wdGC5Sb0pge5 zsCC2KxqXNg3oCGESzpz8oQ0EPHfA3ICJzc6K+loS37yUcut8laLiLlXFH5ADSbXQwRF OlmDPUKFSfaihRO8kOi3JPjlxAfBsHbP1aaIwjRJcdefyrqVDnLM1qS890iJm+4j4Qzj ufMtDd9DdWToke+Y+164xWpgC62R5wcIgdiNuhIj2aR4tQYjtIuNSBsFqazFhEdSgZMu yFnguiyEDUnouzfsDqtxFY8f3GacCTBtb1CotLFyPetZyI/7Yz7v416VtdX2FVKj1/Rs 292g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=FvWbQwT7yD0J6wXiJv9iSEtwBLiuq9ZwuzA1XeKrA9g=; b=Cg6InZM9jPPLcxBAi2M48GD9IfZVy34z23nxEY1BM5mXu6bLKYSP39STj9Ym1XF/KT Lw91fZQGdcXTB/46he5O9Wf1EQ/OouaInj6gw+L5k/9cILwCeuDm8ai2a1XQnMXOCFNs sidQFMFUC2VAlUNTttqdfayKBX1SU1yEXi+72/bxF/Q1yaq3BiB1oT7XYBg0IxI53GDf p/pBrhTVe//LecmrNtzlO1nzcIZ/0N9PyBwbhJPO3gMjl5ziSROdEbC4Gm0brfaMNlMG vJ6/gQKKDXmvHnF1UPEPn42PCZzsQnfopJnCJHOKqZjvxudz8K4dID60D2YL8oqDfOvq lf1w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IwFsOfX9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:04 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Atish Patra , Palmer Dabbelt , Albert Ou , Paul Walmsley , linux-riscv@lists.infradead.org (open list:RISC-V ARCHITECTURE) Subject: [PATCH 07/18] clocksource/drivers/riscv: Add required checks during clock source init Date: Sat, 23 Feb 2019 14:06:55 +0100 Message-Id: <20190223130707.16704-7-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Atish Patra Currently, clocksource registration happens for an invalid cpu for non-smp kernels. This lead to kernel panic as cpu hotplug registration will fail for those cpus. Moreover, riscv_hartid_to_cpuid can return errors now. Do not proceed if hartid or cpuid is invalid. Take this opportunity to print appropriate error strings for different failure cases. Signed-off-by: Atish Patra Reviewed-by: Anup Patel Reviewed-by: Palmer Dabbelt Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-riscv.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 431892200a08..e8163693e936 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -95,13 +95,30 @@ static int __init riscv_timer_init_dt(struct device_node *n) struct clocksource *cs; hartid = riscv_of_processor_hartid(n); + if (hartid < 0) { + pr_warn("Not valid hartid for node [%pOF] error = [%d]\n", + n, hartid); + return hartid; + } + cpuid = riscv_hartid_to_cpuid(hartid); + if (cpuid < 0) { + pr_warn("Invalid cpuid for hartid [%d]\n", hartid); + return cpuid; + } if (cpuid != smp_processor_id()) return 0; + pr_info("%s: Registering clocksource cpuid [%d] hartid [%d]\n", + __func__, cpuid, hartid); cs = per_cpu_ptr(&riscv_clocksource, cpuid); - clocksource_register_hz(cs, riscv_timebase); + error = clocksource_register_hz(cs, riscv_timebase); + if (error) { + pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", + error, cpuid); + return error; + } sched_clock_register(riscv_sched_clock, BITS_PER_LONG, riscv_timebase); @@ -110,8 +127,8 @@ static int __init riscv_timer_init_dt(struct device_node *n) "clockevents/riscv/timer:starting", riscv_timer_starting_cpu, riscv_timer_dying_cpu); if (error) - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", - error, cpuid); + pr_err("cpu hp setup state failed for RISCV timer [%d]\n", + error); return error; } From patchwork Sat Feb 23 13:06:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159115 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33340jad; Sat, 23 Feb 2019 05:08:14 -0800 (PST) X-Google-Smtp-Source: AHgI3Ib3HFWCHSimLf1S3J5V2EvsXPTnWQcQ3qSH2HnY/mB/adlMbDfwhmrIQXAm/LkBjmWft5ik X-Received: by 2002:a62:1c45:: with SMTP id c66mr9448944pfc.90.1550927294032; Sat, 23 Feb 2019 05:08:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927294; cv=none; d=google.com; s=arc-20160816; b=Plg5Xh+GXWae+oABtruE77BNiZghBY8PHfH+PEoznCPzQqctuCrB1JKvTLX15VGMmw L/F16muA8jVJtCFsWqTBy6QQ5D7wu3NqX57NJaSi0JCOMoEj1Fvyu39+TZS2eZSczOqg GFC9+j9lYXBwJuICjk+DnqmFjXURYXJagRhSpoA06grsjG5etPOih7sIpkznZ4DTBGnD zyws7n9cNePdhWD57omQE71K/ZRqBKkXDYrfA4Y+4UsAivImWj9sa7GosEJabykFVjp+ 6FKhtIXpXMYGpVa3DjOEclSr97fYSsOoqrtTyePBv+6foAraz7/80NAYuw8jry4+ex8z 2Jcw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=X/dC9KlJ2HFYdYmnw3hP+wmPZpOjWjCgiVR8KWlL9Mw=; b=VilgzQT/G7G6XhgC0ft7xBJMs9ewknrrLmFOLsmFjE7ZqlyqNoE6Pi5trwZ+EmokvX PteQWMWSNmtNqoILz49Kh3rumWpN4m/yLY5Q8FGzfJcWK3VuLCP9E7WsI4srCA9gwfVP fe/qjtdkmQOww5cYAP612jzYpX0QFvy3U3Ej/rZNwCQ2izjF/BHZA24bCJhexhlv8xnp gbGfF2V+mIiDEhgp8UPnheO2BGtDWD7KQMBgumNQw9OH581BnRK/Xvg8H90qLMk1IP1c NtFZz0+iPGH79ExmONE6xhPCzI7NPjERDX4F1URtElluoo1PTRAiYDfFv1Cw7OzpFGs5 T1EA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mn8OH9P9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:05 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marek Szyprowski , Kukjin Kim , Krzysztof Kozlowski , linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES) Subject: [PATCH 08/18] clocksource/drivers/exynos_mct: Remove dead code Date: Sat, 23 Feb 2019 14:06:56 +0100 Message-Id: <20190223130707.16704-8-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marek Szyprowski Exynos Multi-Core Timer driver is used only on device-tree based systems, so remove non-dt related code. In case of !CONFIG_OF the code is anyway equal because of_irq_count() has a stub returning 0. Device node pointer is always provided when driver has been probed from device tree. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi Signed-off-by: Daniel Lezcano --- drivers/clocksource/exynos_mct.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index d55c30f6981d..647ea9fc752f 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -508,13 +508,12 @@ static int __init exynos4_timer_resources(struct device_node *np, void __iomem * int err, cpu; struct clk *mct_clk, *tick_clk; - tick_clk = np ? of_clk_get_by_name(np, "fin_pll") : - clk_get(NULL, "fin_pll"); + tick_clk = of_clk_get_by_name(np, "fin_pll"); if (IS_ERR(tick_clk)) panic("%s: unable to determine tick clock rate\n", __func__); clk_rate = clk_get_rate(tick_clk); - mct_clk = np ? of_clk_get_by_name(np, "mct") : clk_get(NULL, "mct"); + mct_clk = of_clk_get_by_name(np, "mct"); if (IS_ERR(mct_clk)) panic("%s: unable to retrieve mct clock instance\n", __func__); clk_prepare_enable(mct_clk); @@ -582,11 +581,7 @@ static int __init mct_init_dt(struct device_node *np, unsigned int int_type) * timer irqs are specified after the four global timer * irqs are specified. */ -#ifdef CONFIG_OF nr_irqs = of_irq_count(np); -#else - nr_irqs = 0; -#endif for (i = MCT_L0_IRQ; i < nr_irqs; i++) mct_irqs[i] = irq_of_parse_and_map(np, i); From patchwork Sat Feb 23 13:06:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159116 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33397jad; Sat, 23 Feb 2019 05:08:16 -0800 (PST) X-Google-Smtp-Source: AHgI3IYXAB0W0BsVphLxJQvlU2WjmLqUpaGSXQTPdOPD46ipAhLF3w3ASEnluFMi1lFlGyZRZNt+ X-Received: by 2002:a17:902:9b90:: with SMTP id y16mr9507761plp.0.1550927296802; Sat, 23 Feb 2019 05:08:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927296; cv=none; d=google.com; s=arc-20160816; b=g/ivGvLcf97sAM/uVXnUcuelgQAqIGfTCsLEF41Bz++lFjihDoq/hpvG/9JvZhqG5k nhxcWpQ7/j9oVreyQ09UTP33BUR2moKCZVdLBuVVayhBdAnrwrOmuG686ogZqQgDKDss BNdSDp/Ey+NTF5GJOPZ5jPIPed2uNfFxhe2CsT/Lg9GkJ1W0xZuB5fhYJ9Ump95BQCNw RrLdFamyMCmxnJkzs7KZOFEOBluT8xg6lkrwtI/rnnUesNvkP7mY+CTt5YxvDmAd3EcZ sSgXRSS1pr+AsfSKN3iJvfBt3yzQFLF9D+HZZCeW5PmgTfOlTaG9+EkMZW/YqFpeN/gv CEZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=HqlZ9y60+g61RglAPoiE/a+Pic8KuxjtCcTeAXdOW8w=; b=w2vZfbC47hfhspBB8OhmyH7OESH/TDegrWscERabRSvHUs5iCNpli0MGQ+0gA8UdFd jLMgbha6UP6pHZD6zHCOiWFPiBgebRRasezXcROAAIX4zB7FOr4InFVpr9QCgkRrTji6 yl7JifWHgroziNZ7RGHKb6SxkEomr/TRjOVB89MVoCkvH+ofcR7EDawluOJUBGFHNqc+ IOv1L1fAHD7JmKfswzUyPvsNAhyxovo3QPyQ7A4/C7QcktxYK5DM52zbehuJSYQBFn9m tKsMOo8DFSY9aBlepBh+clfYl4YsUTD5XG493bfSW6jS8oayFOscTlzVirZn2bEG5TOy EW2A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UDySiRAE; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:07 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marek Szyprowski , Krzysztof Kozlowski , Kukjin Kim , linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES) Subject: [PATCH 09/18] clocksource/drivers/exynos_mct: Fix error path in timer resources initialization Date: Sat, 23 Feb 2019 14:06:57 +0100 Message-Id: <20190223130707.16704-9-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marek Szyprowski While freeing interrupt handlers in error path, don't assume that all requested interrupts are per-processor interrupts and properly release standard interrupts too. Reported-by: Krzysztof Kozlowski Fixes: 56a94f13919c ("clocksource: exynos_mct: Avoid blocking calls in the cpu hotplug notifier") Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi Signed-off-by: Daniel Lezcano --- drivers/clocksource/exynos_mct.c | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 647ea9fc752f..33e90c080877 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -562,7 +562,19 @@ static int __init exynos4_timer_resources(struct device_node *np, void __iomem * return 0; out_irq: - free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); + if (mct_int_type == MCT_INT_PPI) { + free_percpu_irq(mct_irqs[MCT_L0_IRQ], &percpu_mct_tick); + } else { + for_each_possible_cpu(cpu) { + struct mct_clock_event_device *pcpu_mevt = + per_cpu_ptr(&percpu_mct_tick, cpu); + + if (pcpu_mevt->evt.irq != -1) { + free_irq(pcpu_mevt->evt.irq, pcpu_mevt); + pcpu_mevt->evt.irq = -1; + } + } + } return err; } From patchwork Sat Feb 23 13:06:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159117 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33425jad; Sat, 23 Feb 2019 05:08:18 -0800 (PST) X-Google-Smtp-Source: AHgI3IYAgYWJmfNfoo5dyMXCB9S1/dHj+mcC6T7JaVvDCrgMfmd4rmHHiy7iZqLVnPWrSTIUiijY X-Received: by 2002:a63:f30d:: with SMTP id l13mr8798923pgh.399.1550927298384; Sat, 23 Feb 2019 05:08:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927298; cv=none; d=google.com; s=arc-20160816; b=YFp4Uqj/Ct/oDjfXB5wJ6Yc2PRBrl6ymdrD94y2XunHSBWKnZBfFk4B9tkX1h9fB7A belJgKV0KpH0UoWEHFcTOM9kZRiIvJQHZOyvcmapOQibJuBr1KzdHyG8lTuAWbbF0n6y p8CASe2gHDBavrEhAK5GohLn5pxksz3bqBu5G8YaYGvTU3NpnZFAwhFII3E6oLavHzU3 O/dImC6y6Yw/i4qv7fo4wTnhESXDgzI0kgAruuTusccLE2IS9KAOeHLfm6mxsz2oyiWc HlJ2lzCxFp0mpS+BTA8tawANdtX3m+C7zjd/F94eMh7NCNT1Rh9CMaeJJfuZES1OUeX3 vsGA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=aFmdTDn+1DhlKxKeSwBRQMFH12sZspvNOM68gN8DFWg=; b=NQYyZXj1/vE9JzCdBdj9+mh61JiBNvsc2YIRs+Wwyun0J/Dyv7HS84PhlkGJzGn4PY cG8m05jxGqpyO+DGZOUdyVnqmBM7ZBXGjua6SoVCQhuO4ooDxME8L5nqhjjxksW5w1Vv iV9VbG+mlRQO91PkxoT4mSrrf5yXSv163sePc7BLSvVG0f8KkIN+EUxQrx27A8QbnZqS NQc9z8594DB6cTYVcmT4GpFWj908kz+klZ2nZfq8l1z/gnvmNmH2FoqOIXB+T04bQy2Z WRJ8Abm//nvAVs4ZewTbXx9dV1ESX0OhdVF53c3ExSGBiGu4GerYIT8Xyw7hHU4qrufk l2Yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=G2vB15Nm; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.08 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:10 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Ryder Lee , Rob Herring , Mark Rutland , Matthias Brugger , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/Mediatek SoC support), linux-mediatek@lists.infradead.org (moderated list:ARM/Mediatek SoC support) Subject: [PATCH 10/18] dt-bindings: timer: mediatek: update bindings for MT7629 SoC Date: Sat, 23 Feb 2019 14:06:58 +0100 Message-Id: <20190223130707.16704-10-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Ryder Lee Update the binding for MT7629 SoC, which uses fallback compatible to MT6765 SYST, so add more descriptions to distinguish it from the other SoCs that use GPT. Signed-off-by: Ryder Lee Cc: Daniel Lezcano Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/mediatek,mtk-timer.txt | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt index 18d4d0166c76..ff7c567a7972 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt +++ b/Documentation/devicetree/bindings/timer/mediatek,mtk-timer.txt @@ -1,7 +1,7 @@ -Mediatek Timers +MediaTek Timers --------------- -Mediatek SoCs have two different timers on different platforms, +MediaTek SoCs have two different timers on different platforms, - GPT (General Purpose Timer) - SYST (System Timer) @@ -9,6 +9,7 @@ The proper timer will be selected automatically by driver. Required properties: - compatible should contain: + For those SoCs that use GPT * "mediatek,mt2701-timer" for MT2701 compatible timers (GPT) * "mediatek,mt6580-timer" for MT6580 compatible timers (GPT) * "mediatek,mt6589-timer" for MT6589 compatible timers (GPT) @@ -17,7 +18,11 @@ Required properties: * "mediatek,mt8135-timer" for MT8135 compatible timers (GPT) * "mediatek,mt8173-timer" for MT8173 compatible timers (GPT) * "mediatek,mt6577-timer" for MT6577 and all above compatible timers (GPT) - * "mediatek,mt6765-timer" for MT6765 compatible timers (SYST) + + For those SoCs that use SYST + * "mediatek,mt7629-timer" for MT7629 compatible timers (SYST) + * "mediatek,mt6765-timer" for MT6765 and all above compatible timers (SYST) + - reg: Should contain location and length for timer register. - clocks: Should contain system clock. From patchwork Sat Feb 23 13:06:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159118 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33458jad; Sat, 23 Feb 2019 05:08:20 -0800 (PST) X-Google-Smtp-Source: AHgI3IZgm+LXjNwn/fgqP9/sdqN1QRYQponcGtN4lBDsSED8g8XOToomHqFtbos99a5JFRz4km0f X-Received: by 2002:a63:6841:: with SMTP id d62mr8817272pgc.133.1550927300045; Sat, 23 Feb 2019 05:08:20 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927300; cv=none; d=google.com; s=arc-20160816; b=NlG5U7Q2dI0bZ3DoYrYauN/CXcaBXHahNQNtwqy/Om+pAe2P4NQ49DiSdJG/a1as04 30i0GzMus7yKJXcZmvO60kLZE1NrUEKgPAPoNXk8aERgDO5IHE8kVUSc3QScP1uSA3tt bXhiNdtux/7xZV5rYDCUzoXvhgMH+YTruSTNbHQcmSkfA0eJQWgO8cv20qmcr6TbOau1 b6cdRk1rPYmKrXiksF3bz25dNiL5kXql/yMrh5aOASKGdwjSnH94dU045lgOCDsvg/W3 SGGM1AuenaQb7Z4HeUF8junRkfDGUqMghMr8/d2ZNa6rKmBKhrYbnpeOKs4vCWOvM2cP lw8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=GtXFZaf3Lxm4MFz8aDdKlTiKXkM/CBAgN7ASkzCfdj4=; b=Ityrs0Tbr6tWWdenZUREivb1nI1RZUubmRZ1yRlZ/mnFRhE9S/cagnj65Uk+tXrnbZ AcegEAhbDbuwxT1ececvp/RT48P5K+S2j3B2lyqZCMdXapJbrdd8uTmQS5pCk7k2a/u/ CSuqrrlt6FXjTcMgUiMUz/9ealvakWZY8PABz5gZWToBHaXHCeIwYDb1by0wHGVNt/ur ozmO9upqzhJig2LdpQEmKR57u7VQRl5xrqjgg4YhlLHflS5s5pcQgG+ug2612bvf4zsx C2ldUZ0Wl5b72f7ycNosZ4JDtyXwxIDmULH6OTZ8lDy2D32JK+kgYVJFbWuRYqDYJvsZ 6Rpg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=HZg4KyRa; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:13 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Kukjin Kim , linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES) Subject: [PATCH 11/18] clocksource/drivers/exynos_mct: Remove unused header includes Date: Sat, 23 Feb 2019 14:06:59 +0100 Message-Id: <20190223130707.16704-11-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Krzysztof Kozlowski The driver does not use sched.h and platform_device.h. Signed-off-by: Krzysztof Kozlowski Signed-off-by: Daniel Lezcano --- drivers/clocksource/exynos_mct.c | 2 -- 1 file changed, 2 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 33e90c080877..34bd250d46c6 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -10,14 +10,12 @@ * published by the Free Software Foundation. */ -#include #include #include #include #include #include #include -#include #include #include #include From patchwork Sat Feb 23 13:07:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159119 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33495jad; Sat, 23 Feb 2019 05:08:22 -0800 (PST) X-Google-Smtp-Source: AHgI3IbB137PeT84Sdn4HnLQZvUI7qDRH0ZWScWWKpM8Th3ReOMbukA5hopE3DdcGQkEW42rbfvb X-Received: by 2002:a17:902:e60e:: with SMTP id cm14mr9358092plb.192.1550927302193; Sat, 23 Feb 2019 05:08:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927302; cv=none; d=google.com; s=arc-20160816; b=QEnvQWCZCg9AgiM0hF8eWFxjcU+5E6g7ZyvBMDppncgxK1dPBl0HmNpT0FHdoq1bdK tTj5cVjsnZv5vz4b0xQIjrShKoza5XYfe1lK6QWbBLWkJrIwruKXfxmS7me1frZI317I HTFdkRgXLWbDCdFztmBdJ0JT54HWdjdD9QUIybbaGFmMRrScA33h2CGyQZSBfCYwvo2B 3SI1L/aO88fyBRhtzyx2vFgn54h06nSzG1XozMSgoplxYf/a/31NlPEGTLg6w7uctWoT bzuB9G8ljB6iOyrDxDcf4PAAfHp8VE6fvJhvlM7D1ZRBkZ96oAGwZew5yyDE23s4G/y1 4hnA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=XjmpIkemHWcDi0hPr+0l9SdJ/Rn9t0FUVqCSEcUng6w=; b=O4V41lRg1lVKO/q/Lpya2R1+iSf+d9M2F4dwfsVibPKhzh3JineARgbeWaYPwNfEii Ct4ZwbcCYFnqiiG6nYOpyoqqtYgvBX7jgMlZLUXOCqApmvl/o22r0u7CDA5kGxDBIToh VZC2WyeKyBhS2iHf9XHQ0gg/dMHv8mcD07kGPSzgw+5QOakLFg1STVc09X+I2RrKVc2A KOmCQguo3qTkVyrIta0HItSIZLMnny29cqZAOWEGXQgwqMbPCbNHcMEWaUHR+93faaOY E0xDftfAv3PhBP8YiYvt5t1PFxDsyNm5GKGoXbW6eJ1SYoSnjqOk0kcE6RGlgO4Nw6G0 EXGA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uYBY1+0V; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:15 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Anson Huang , Anson Huang , Rob Herring , Mark Rutland , devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS) Subject: [PATCH 12/18] dt-bindings: timer: gpt: update binding doc Date: Sat, 23 Feb 2019 14:07:00 +0100 Message-Id: <20190223130707.16704-12-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Anson Huang The i.MX GPT timer driver binding doc is out of date, update it according to current GPT timer driver. Signed-off-by: Anson Huang Reviewed-by: Rob Herring Signed-off-by: Daniel Lezcano --- .../devicetree/bindings/timer/fsl,imxgpt.txt | 39 ++++++++++++++++--- 1 file changed, 33 insertions(+), 6 deletions(-) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt index 9809b11f7180..5d8fd5b52598 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt @@ -2,17 +2,44 @@ Freescale i.MX General Purpose Timer (GPT) Required properties: -- compatible : should be "fsl,-gpt" -- reg : Specifies base physical address and size of the registers. -- interrupts : A list of 4 interrupts; one per timer channel. -- clocks : The clocks provided by the SoC to drive the timer. +- compatible : should be one of following: + for i.MX1: + - "fsl,imx1-gpt"; + for i.MX21: + - "fsl,imx21-gpt"; + for i.MX27: + - "fsl,imx27-gpt", "fsl,imx21-gpt"; + for i.MX31: + - "fsl,imx31-gpt"; + for i.MX25: + - "fsl,imx25-gpt", "fsl,imx31-gpt"; + for i.MX50: + - "fsl,imx50-gpt", "fsl,imx31-gpt"; + for i.MX51: + - "fsl,imx51-gpt", "fsl,imx31-gpt"; + for i.MX53: + - "fsl,imx53-gpt", "fsl,imx31-gpt"; + for i.MX6Q: + - "fsl,imx6q-gpt", "fsl,imx31-gpt"; + for i.MX6DL: + - "fsl,imx6dl-gpt"; + for i.MX6SL: + - "fsl,imx6sl-gpt", "fsl,imx6dl-gpt"; + for i.MX6SX: + - "fsl,imx6sx-gpt", "fsl,imx6dl-gpt"; +- reg : specifies base physical address and size of the registers. +- interrupts : should be the gpt interrupt. +- clocks : the clocks provided by the SoC to drive the timer, must contain + an entry for each entry in clock-names. +- clock-names : must include "ipg" entry first, then "per" entry. Example: gpt1: timer@10003000 { - compatible = "fsl,imx27-gpt", "fsl,imx1-gpt"; + compatible = "fsl,imx27-gpt", "fsl,imx21-gpt"; reg = <0x10003000 0x1000>; interrupts = <26>; - clocks = <&clks 46>, <&clks 61>; + clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>, + <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; From patchwork Sat Feb 23 13:07:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159120 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33615jad; Sat, 23 Feb 2019 05:08:29 -0800 (PST) X-Google-Smtp-Source: AHgI3IYq4+xeTklmCtnbjas5/ZT5ouhNhoGPlri4iSbBxPfX0qqKyA8k+9JBSkTJ+miC1Y6pMEjD X-Received: by 2002:a63:d49:: with SMTP id 9mr8761229pgn.27.1550927309659; Sat, 23 Feb 2019 05:08:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927309; cv=none; d=google.com; s=arc-20160816; b=UTCQf5y6vVafSt3mhROsGjePcfay0yWCa3zWl2L4GqZp6NLFQhzECh+YS3hRFytbdt YFKDl5wQN2P2+OaYG15czin9sSNFR/OrFOIFxf4EmzpCsmxD6aG9L8SZhWYE423sQacm pPSHwDzEqf8WI5lwfjHrnlv8bcyt1kmqIq/DTsobmrwrvwJ7A/PpxOkPtlwRtTl3Ac4Z Va+fKObjLvW/KqU6TWXOuH8/kM4hDc2MR+/HjhpXtRrWYiyGBp7J2n1Nep8SoV+RmIqU NAl6NEwSio/y/byj/aT/0zVP+YwzMjKtg4AEr4qNUai/LGhrfP5uwYLVxXIO5StosMsv TU1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=zFlPFLyFgw01uA6gH5DBSfpAPaQdL6b18fd1L1abNfo=; b=KKSwST7041tDho2rqqtsVzIr1VceOtxPz2uOxD9xSAij9Lkyo5rMxpLgkrQtcFVrSo RcMIO4hnjI9UBKPXSLospKITgbJUwZusMGioJpzZ4rM1nj9nAw1CbPKCs/8zv6J3/ZQI fshXknAVUdbjB1xD+ihYIqk6SIW6kyuZZKpvdaB4xpFwVioJkQU8XcwGfOB350Sove0E 1QAzwxO+I7ZzJ8M7czFQ8CLt4wmVFUIku20ulp7dagGMbE+bawyuH3QcXQilrLDw8b52 X8vuQVv39jb6KyfbCqeIdYRnLvQKnYaz7L8OQOHMblBpSTqc7lxVsleb8aGd9OX8kyia F5yg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=qCTVRhxS; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:17 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org Subject: [PATCH 13/18] clocksource/drivers/tango-xtal: Rename the file for consistency Date: Sat, 23 Feb 2019 14:07:01 +0100 Message-Id: <20190223130707.16704-13-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For the sake of consistency, let's rename the file to a name similar to other file names in this directory. Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{tango_xtal.c => timer-tango-xtal.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{tango_xtal.c => timer-tango-xtal.c} (100%) -- 2.17.1 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index cdd210ff89ea..47052ea15f20 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -69,7 +69,7 @@ obj-$(CONFIG_KEYSTONE_TIMER) += timer-keystone.o obj-$(CONFIG_INTEGRATOR_AP_TIMER) += timer-integrator-ap.o obj-$(CONFIG_CLKSRC_VERSATILE) += timer-versatile.o obj-$(CONFIG_CLKSRC_MIPS_GIC) += mips-gic-timer.o -obj-$(CONFIG_CLKSRC_TANGO_XTAL) += tango_xtal.o +obj-$(CONFIG_CLKSRC_TANGO_XTAL) += timer-tango-xtal.o obj-$(CONFIG_CLKSRC_IMX_GPT) += timer-imx-gpt.o obj-$(CONFIG_CLKSRC_IMX_TPM) += timer-imx-tpm.o obj-$(CONFIG_ASM9260_TIMER) += asm9260_timer.o diff --git a/drivers/clocksource/tango_xtal.c b/drivers/clocksource/timer-tango-xtal.c similarity index 100% rename from drivers/clocksource/tango_xtal.c rename to drivers/clocksource/timer-tango-xtal.c From patchwork Sat Feb 23 13:07:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159125 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33992jad; Sat, 23 Feb 2019 05:08:52 -0800 (PST) X-Google-Smtp-Source: AHgI3IbcjBEBfWTXhXeBUuSQi1xtnCQlhLAWxUAmEOYpq0/BAbssl2u3tA4wcqQo/nWJeEAjGDAf X-Received: by 2002:a63:6cc8:: with SMTP id h191mr8486757pgc.366.1550927332574; Sat, 23 Feb 2019 05:08:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927332; cv=none; d=google.com; s=arc-20160816; b=CZhaaeRaeIi/PpWBgQy+78QIz+nLdC6auvLxozNc8o6+t+EL3VDh8fcsYPDBlCrk91 4p6bPs0pN10FywpJvmvhWTsOdTfFF+A9NjCPWLuCo8e2fA5UD4dxOlLWZCRaQrhye86W QtyVBwh4UgrIdGdUhMB7SI0OG1S6WyuwJ9uJBCLzRdoN/2WxKkEQzjz2HI150xl3EYk9 g9bfcnQjveuFBTCwxpGMT6sW5Amf0AyTc3Aw9b74zQT+v9fkd94BCoim9PBL8npObDyD RdmsOMza9vGO9vrM5c0pHcvfdXcMEI89rXp1fxj3kCbKxtLMSR9Mn0YiiBocUeCpbIoP 7nQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=BwQfWziq3qwqhPCKOxGuiZqx00tpUJAjOFtgPROv/OM=; b=R/1BP0fG6QiFu57NRpMwpB6ltmPCakTezBXV7WPa2quQ7IQO2LzNg9vQuvdL7IgVr2 +OAQFKvbyMctnB8IWTY31oRUgshAgdgS/4ZEFZC5/em7pU6aOvGw4Owr8uvgtPw3OfUr rQ3dFcZwqFfZnsMwNFxfJvKBbAwTqRk1k9wMfQXhAfhr3q6YmHgNU6bAJqN8ay4YpiVb kR5uAycUWhy1qkQpci/Pwfob0KUT/7lbKnlarTrF/NcoBTPIoUpJF6I2IuefHEK+bZtf sNim04NY3Q7Fnl9qgDN0KqRkMfusDquv5SWoREKkZXGtgtobAJ8ybjnPthsZHR1jVM1C KiRA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MHIE2KNh; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:18 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org Subject: [PATCH 14/18] clocksource/drivers/timer-pxa: Rename the file for consistency Date: Sat, 23 Feb 2019 14:07:02 +0100 Message-Id: <20190223130707.16704-14-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For the sake of consistency, let's rename the file to a name similar to other file names in this directory. Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{pxa_timer.c => timer-pxa.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{pxa_timer.c => timer-pxa.c} (100%) -- 2.17.1 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 47052ea15f20..a9e7c642ecce 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -29,7 +29,7 @@ obj-$(CONFIG_BCM2835_TIMER) += bcm2835_timer.o obj-$(CONFIG_CLPS711X_TIMER) += clps711x-timer.o obj-$(CONFIG_ATLAS7_TIMER) += timer-atlas7.o obj-$(CONFIG_MXS_TIMER) += mxs_timer.o -obj-$(CONFIG_CLKSRC_PXA) += pxa_timer.o +obj-$(CONFIG_CLKSRC_PXA) += timer-pxa.o obj-$(CONFIG_PRIMA2_TIMER) += timer-prima2.o obj-$(CONFIG_U300_TIMER) += timer-u300.o obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o diff --git a/drivers/clocksource/pxa_timer.c b/drivers/clocksource/timer-pxa.c similarity index 100% rename from drivers/clocksource/pxa_timer.c rename to drivers/clocksource/timer-pxa.c From patchwork Sat Feb 23 13:07:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159124 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33893jad; Sat, 23 Feb 2019 05:08:47 -0800 (PST) X-Google-Smtp-Source: AHgI3IaFjr5Y2ealN7RrIidOCxim+q/4rIPxlsWHEHksYXyEFv+BudaypmT2n5a+iQW5vgyfWoGw X-Received: by 2002:a17:902:be15:: with SMTP id r21mr9132188pls.143.1550927327484; Sat, 23 Feb 2019 05:08:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927327; cv=none; d=google.com; s=arc-20160816; b=u11DPyTnZNF+qd1u1lbr2cnrCSkEerNCY+K8VslhV8vRNES3MmHdGNY1yYEuHRcxYY H5Nm2TrAY8HZHQ7mDXDR2KrzvDY+yO1aOR2F9hjVHfWPmwrhLUv9reKrmUWEb/LxD8Xc TFpC54EPeH3QwFPg4fZ0RcaoT0b+Z4jv6afqLKrcGJTCsK+M4vtrd2MQwcknmOlgQXND vhKhwWdyOBj76L7Hv5ibEvtjQOlitwvDoh9M2uzkOTmvFPDr4PcsSUW/bMjWr8+7jjWW /QlHvFUmum70mQ4v6OTeJv/bbzIiWJjwvcEurqfDElR4whkCMc3OGtZzZE574TxOfkNw ALNQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=vUftDpL4i18Pw6X49JOGif3RmHhi91QSNFqo0duvcr4=; b=0W8xz5v5ZRDEaH4AFRSzZI51zD7j8Fzfu5Rsb/UupW6L6IsXa5qTKHGzxtIMPkoiA/ wjEbrW3Zt/uGz//6BPSbgEEmuGNA5FOnN0pVOJw66YVV2nB5vbS3HxKXLsiCPirZqXEK UYgEv8Sf9VuvcUp6IHjsNr3Syws8bQWpfHPSV13wzquinDoKY8+HNlor2TtI9EJwdpZi yH+4GGq4nasKuPlOqi6PDrVCJpHSvmt4F1nfFbShqGhA/nw5zRervzcppGbJJyM6EUPl LGQ1imeGrxzfQnLKcRvlReK6tsvrayQUBj4RCJuedwSbWIuyo4Wp+AJOkj7LMndQwwFN JF8Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="OKS/iPp4"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.19 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:20 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org Subject: [PATCH 15/18] clocksource/drivers/timer-cs5535: Rename the file for consistency Date: Sat, 23 Feb 2019 14:07:03 +0100 Message-Id: <20190223130707.16704-15-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For the sake of consistency, let's rename the file to a name similar to other file names in this directory. Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{cs5535-clockevt.c => timer-cs5535.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{cs5535-clockevt.c => timer-cs5535.c} (100%) -- 2.17.1 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index a9e7c642ecce..c4a8e9ef932a 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -6,7 +6,7 @@ obj-$(CONFIG_ATMEL_ST) += timer-atmel-st.o obj-$(CONFIG_ATMEL_TCB_CLKSRC) += tcb_clksrc.o obj-$(CONFIG_X86_PM_TIMER) += acpi_pm.o obj-$(CONFIG_SCx200HR_TIMER) += scx200_hrt.o -obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += cs5535-clockevt.o +obj-$(CONFIG_CS5535_CLOCK_EVENT_SRC) += timer-cs5535.o obj-$(CONFIG_CLKSRC_JCORE_PIT) += jcore-pit.o obj-$(CONFIG_SH_TIMER_CMT) += sh_cmt.o obj-$(CONFIG_SH_TIMER_MTU2) += sh_mtu2.o diff --git a/drivers/clocksource/cs5535-clockevt.c b/drivers/clocksource/timer-cs5535.c similarity index 100% rename from drivers/clocksource/cs5535-clockevt.c rename to drivers/clocksource/timer-cs5535.c From patchwork Sat Feb 23 13:07:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159122 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33754jad; Sat, 23 Feb 2019 05:08:37 -0800 (PST) X-Google-Smtp-Source: AHgI3IZIjFPOUFooOncAv0msS+cYAvXAs1WOzjVkFl0vc/SKHXcRdHgFpCgLEr8b73VzYPYrGeS0 X-Received: by 2002:a63:8042:: with SMTP id j63mr8494970pgd.36.1550927317543; Sat, 23 Feb 2019 05:08:37 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550927317; cv=none; d=google.com; s=arc-20160816; b=zgTtPAQr2i993OHhBaLuD1sYOI986MkkiVSIJCM1nTtaUblfZtDZ8P1zWTQYqhOj+h sO9chJ/bDxS+xx0MUfPec2vnQOzHUy3BRa/1XqE8OH3cqF+GouBOprOjtOqxDtoM/mPn TUsADrna8oArwwlr1DAm8LIp98WOKB5T3r0IoAS4vSQ1nR0mmDPr9U1zlKPkJO9J8Ji8 1/21dI9GvslGWNz+eGD7sO8fr6Ht+4AoBix+6U9f2xldR2kbXAeTI9MtV3mK0tZnb2vh tD7Zbqda9iqz0+TIeagFLGH1kIFZpjjx3EZ0sl52hHWlxJHoFhDO3L9SZ8zKBm0fWqUT lqng== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=tZP0UsIfUr5CMc4uOaLIcITOIHDvPRz2+Lu8XUazvZE=; b=k7XOAU5WVn+ozUDqX6poLXD/TLgTnpltl0D0bI7QThrwHQAFWv/YxJTPkHFqFgczOe OXi0eIwciDLSExyTE4r1InByiwuhdwqYuOofQ18QPHYNrnKtd0s+yBsSzwLZWPlk4vuv gMSMedAOFK3GpQLnZzUFdqzyWJKeCbMCVPBWo6coA5yrNoKySaWb4ST1f1PwAoA9bxuj /g7Jl7VJH16NuMcPeXF20x4RpFIvX3L9ENln4rYsOCAJ4/fsNzTkJfdWe2LV5nGr+zf7 uW/2Om25fETxGW7d74Blvzoz0z371qrIyDlVjyBnMDWwIB3G80JX2lzbuHti5/iectvO 5QNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=B6ukx1OC; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.30 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:31 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Joseph Lo , Thierry Reding , Jon Hunter , Thierry Reding , Palmer Dabbelt , Peter Zijlstra , Will Deacon , James Hogan , Lucas Stach , Guo Ren , Hoan Tran , Arnd Bergmann , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 17/18] clocksource/drivers/tegra: Add Tegra210 timer support Date: Sat, 23 Feb 2019 14:07:05 +0100 Message-Id: <20190223130707.16704-17-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joseph Lo Add support for the Tegra210 timer that runs at oscillator clock (TMR10-TMR13). We need these timers to work as clock event device and to replace the ARMv8 architected timer due to it can't survive across the power cycle of the CPU core or CPUPORESET signal. So it can't be a wake-up source when CPU suspends in power down state. Also convert the original driver to use timer-of API. Cc: Daniel Lezcano Cc: Thomas Gleixner Cc: linux-kernel@vger.kernel.org Signed-off-by: Joseph Lo Acked-by: Thierry Reding Acked-by: Jon Hunter Acked-by: Daniel Lezcano Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 3 +- drivers/clocksource/timer-tegra20.c | 370 +++++++++++++++++++--------- include/linux/cpuhotplug.h | 1 + 3 files changed, 262 insertions(+), 112 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 8dfd3bc448d0..5d93e580e5dc 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -131,7 +131,8 @@ config SUN5I_HSTIMER config TEGRA_TIMER bool "Tegra timer driver" if COMPILE_TEST select CLKSRC_MMIO - depends on ARM + select TIMER_OF + depends on ARM || ARM64 help Enables support for the Tegra driver. diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 4293943f4e2b..fdb3d795a409 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -15,21 +15,24 @@ * */ -#include +#include +#include +#include +#include +#include #include -#include #include -#include -#include -#include -#include -#include #include #include +#include #include -#include +#include + +#include "timer-of.h" +#ifdef CONFIG_ARM #include +#endif #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c @@ -39,74 +42,161 @@ #define TIMERUS_USEC_CFG 0x14 #define TIMERUS_CNTR_FREEZE 0x4c -#define TIMER1_BASE 0x0 -#define TIMER2_BASE 0x8 -#define TIMER3_BASE 0x50 -#define TIMER4_BASE 0x58 - -#define TIMER_PTV 0x0 -#define TIMER_PCR 0x4 - +#define TIMER_PTV 0x0 +#define TIMER_PTV_EN BIT(31) +#define TIMER_PTV_PER BIT(30) +#define TIMER_PCR 0x4 +#define TIMER_PCR_INTR_CLR BIT(30) + +#ifdef CONFIG_ARM +#define TIMER_CPU0 0x50 /* TIMER3 */ +#else +#define TIMER_CPU0 0x90 /* TIMER10 */ +#define TIMER10_IRQ_IDX 10 +#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) +#endif +#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) + +static u32 usec_config; static void __iomem *timer_reg_base; +#ifdef CONFIG_ARM static void __iomem *rtc_base; - static struct timespec64 persistent_ts; static u64 persistent_ms, last_persistent_ms; - static struct delay_timer tegra_delay_timer; - -#define timer_writel(value, reg) \ - writel_relaxed(value, timer_reg_base + (reg)) -#define timer_readl(reg) \ - readl_relaxed(timer_reg_base + (reg)) +#endif static int tegra_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) { - u32 reg; + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); + writel(TIMER_PTV_EN | + ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ + reg_base + TIMER_PTV); return 0; } -static inline void timer_shutdown(struct clock_event_device *evt) +static int tegra_timer_shutdown(struct clock_event_device *evt) { - timer_writel(0, TIMER3_BASE + TIMER_PTV); + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(0, reg_base + TIMER_PTV); + + return 0; } -static int tegra_timer_shutdown(struct clock_event_device *evt) +static int tegra_timer_set_periodic(struct clock_event_device *evt) { - timer_shutdown(evt); + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(TIMER_PTV_EN | TIMER_PTV_PER | + ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), + reg_base + TIMER_PTV); + return 0; } -static int tegra_timer_set_periodic(struct clock_event_device *evt) +static irqreturn_t tegra_timer_isr(int irq, void *dev_id) +{ + struct clock_event_device *evt = (struct clock_event_device *)dev_id; + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + evt->event_handler(evt); + + return IRQ_HANDLED; +} + +static void tegra_timer_suspend(struct clock_event_device *evt) +{ + void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + + writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); +} + +static void tegra_timer_resume(struct clock_event_device *evt) +{ + writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); +} + +#ifdef CONFIG_ARM64 +static DEFINE_PER_CPU(struct timer_of, tegra_to) = { + .flags = TIMER_OF_CLOCK | TIMER_OF_BASE, + + .clkevt = { + .name = "tegra_timer", + .rating = 460, + .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, + .set_next_event = tegra_timer_set_next_event, + .set_state_shutdown = tegra_timer_shutdown, + .set_state_periodic = tegra_timer_set_periodic, + .set_state_oneshot = tegra_timer_shutdown, + .tick_resume = tegra_timer_shutdown, + .suspend = tegra_timer_suspend, + .resume = tegra_timer_resume, + }, +}; + +static int tegra_timer_setup(unsigned int cpu) { - u32 reg = 0xC0000000 | ((1000000 / HZ) - 1); + struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + + irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); + enable_irq(to->clkevt.irq); + + clockevents_config_and_register(&to->clkevt, timer_of_rate(to), + 1, /* min */ + 0x1fffffff); /* 29 bits */ - timer_shutdown(evt); - timer_writel(reg, TIMER3_BASE + TIMER_PTV); return 0; } -static struct clock_event_device tegra_clockevent = { - .name = "timer0", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_DYNIRQ, - .set_next_event = tegra_timer_set_next_event, - .set_state_shutdown = tegra_timer_shutdown, - .set_state_periodic = tegra_timer_set_periodic, - .set_state_oneshot = tegra_timer_shutdown, - .tick_resume = tegra_timer_shutdown, +static int tegra_timer_stop(unsigned int cpu) +{ + struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + + to->clkevt.set_state_shutdown(&to->clkevt); + disable_irq_nosync(to->clkevt.irq); + + return 0; +} +#else /* CONFIG_ARM */ +static struct timer_of tegra_to = { + .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ, + + .clkevt = { + .name = "tegra_timer", + .rating = 300, + .features = CLOCK_EVT_FEAT_ONESHOT | + CLOCK_EVT_FEAT_PERIODIC | + CLOCK_EVT_FEAT_DYNIRQ, + .set_next_event = tegra_timer_set_next_event, + .set_state_shutdown = tegra_timer_shutdown, + .set_state_periodic = tegra_timer_set_periodic, + .set_state_oneshot = tegra_timer_shutdown, + .tick_resume = tegra_timer_shutdown, + .suspend = tegra_timer_suspend, + .resume = tegra_timer_resume, + .cpumask = cpu_possible_mask, + }, + + .of_irq = { + .index = 2, + .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, + .handler = tegra_timer_isr, + }, }; static u64 notrace tegra_read_sched_clock(void) { - return timer_readl(TIMERUS_CNTR_1US); + return readl(timer_reg_base + TIMERUS_CNTR_1US); +} + +static unsigned long tegra_delay_timer_read_counter_long(void) +{ + return readl(timer_reg_base + TIMERUS_CNTR_1US); } /* @@ -143,100 +233,155 @@ static void tegra_read_persistent_clock64(struct timespec64 *ts) timespec64_add_ns(&persistent_ts, delta * NSEC_PER_MSEC); *ts = persistent_ts; } +#endif -static unsigned long tegra_delay_timer_read_counter_long(void) -{ - return readl(timer_reg_base + TIMERUS_CNTR_1US); -} - -static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) -{ - struct clock_event_device *evt = (struct clock_event_device *)dev_id; - timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); - evt->event_handler(evt); - return IRQ_HANDLED; -} - -static struct irqaction tegra_timer_irq = { - .name = "timer0", - .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, - .handler = tegra_timer_interrupt, - .dev_id = &tegra_clockevent, -}; - -static int __init tegra20_init_timer(struct device_node *np) +static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) { - struct clk *clk; - unsigned long rate; - int ret; - - timer_reg_base = of_iomap(np, 0); - if (!timer_reg_base) { - pr_err("Can't map timer registers\n"); - return -ENXIO; - } + int ret = 0; - tegra_timer_irq.irq = irq_of_parse_and_map(np, 2); - if (tegra_timer_irq.irq <= 0) { - pr_err("Failed to map timer IRQ\n"); - return -EINVAL; - } + ret = timer_of_init(np, to); + if (ret < 0) + goto out; - clk = of_clk_get(np, 0); - if (IS_ERR(clk)) { - pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n"); - rate = 12000000; - } else { - clk_prepare_enable(clk); - rate = clk_get_rate(clk); - } + timer_reg_base = timer_of_base(to); - switch (rate) { + /* + * Configure microsecond timers to have 1MHz clock + * Config register is 0xqqww, where qq is "dividend", ww is "divisor" + * Uses n+1 scheme + */ + switch (timer_of_rate(to)) { case 12000000: - timer_writel(0x000b, TIMERUS_USEC_CFG); + usec_config = 0x000b; /* (11+1)/(0+1) */ + break; + case 12800000: + usec_config = 0x043f; /* (63+1)/(4+1) */ break; case 13000000: - timer_writel(0x000c, TIMERUS_USEC_CFG); + usec_config = 0x000c; /* (12+1)/(0+1) */ + break; + case 16800000: + usec_config = 0x0453; /* (83+1)/(4+1) */ break; case 19200000: - timer_writel(0x045f, TIMERUS_USEC_CFG); + usec_config = 0x045f; /* (95+1)/(4+1) */ break; case 26000000: - timer_writel(0x0019, TIMERUS_USEC_CFG); + usec_config = 0x0019; /* (25+1)/(0+1) */ + break; + case 38400000: + usec_config = 0x04bf; /* (191+1)/(4+1) */ + break; + case 48000000: + usec_config = 0x002f; /* (47+1)/(0+1) */ break; default: - WARN(1, "Unknown clock rate"); + ret = -EINVAL; + goto out; + } + + writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG); + +out: + return ret; +} + +#ifdef CONFIG_ARM64 +static int __init tegra_init_timer(struct device_node *np) +{ + int cpu, ret = 0; + struct timer_of *to; + + to = this_cpu_ptr(&tegra_to); + ret = tegra_timer_common_init(np, to); + if (ret < 0) + goto out; + + for_each_possible_cpu(cpu) { + struct timer_of *cpu_to; + + cpu_to = per_cpu_ptr(&tegra_to, cpu); + cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu); + cpu_to->of_clk.rate = timer_of_rate(to); + cpu_to->clkevt.cpumask = cpumask_of(cpu); + cpu_to->clkevt.irq = + irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); + if (!cpu_to->clkevt.irq) { + pr_err("%s: can't map IRQ for CPU%d\n", + __func__, cpu); + ret = -EINVAL; + goto out; + } + + irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); + ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, + IRQF_TIMER | IRQF_NOBALANCING, + cpu_to->clkevt.name, &cpu_to->clkevt); + if (ret) { + pr_err("%s: cannot setup irq %d for CPU%d\n", + __func__, cpu_to->clkevt.irq, cpu); + ret = -EINVAL; + goto out_irq; + } + } + + cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, + "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, + tegra_timer_stop); + + return ret; +out_irq: + for_each_possible_cpu(cpu) { + struct timer_of *cpu_to; + + cpu_to = per_cpu_ptr(&tegra_to, cpu); + if (cpu_to->clkevt.irq) { + free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt); + irq_dispose_mapping(cpu_to->clkevt.irq); + } } +out: + timer_of_cleanup(to); + return ret; +} +#else /* CONFIG_ARM */ +static int __init tegra_init_timer(struct device_node *np) +{ + int ret = 0; + + ret = tegra_timer_common_init(np, &tegra_to); + if (ret < 0) + goto out; - sched_clock_register(tegra_read_sched_clock, 32, 1000000); + tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0); + tegra_to.of_clk.rate = 1000000; /* microsecond timer */ + sched_clock_register(tegra_read_sched_clock, 32, + timer_of_rate(&tegra_to)); ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", 1000000, 300, 32, - clocksource_mmio_readl_up); + "timer_us", timer_of_rate(&tegra_to), + 300, 32, clocksource_mmio_readl_up); if (ret) { pr_err("Failed to register clocksource\n"); - return ret; + goto out; } tegra_delay_timer.read_current_timer = tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = 1000000; + tegra_delay_timer.freq = timer_of_rate(&tegra_to); register_current_timer_delay(&tegra_delay_timer); - ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); - if (ret) { - pr_err("Failed to register timer IRQ: %d\n", ret); - return ret; - } + clockevents_config_and_register(&tegra_to.clkevt, + timer_of_rate(&tegra_to), + 0x1, + 0x1fffffff); - tegra_clockevent.cpumask = cpu_possible_mask; - tegra_clockevent.irq = tegra_timer_irq.irq; - clockevents_config_and_register(&tegra_clockevent, 1000000, - 0x1, 0x1fffffff); + return ret; +out: + timer_of_cleanup(&tegra_to); - return 0; + return ret; } -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); static int __init tegra20_init_rtc(struct device_node *np) { @@ -261,3 +406,6 @@ static int __init tegra20_init_rtc(struct device_node *np) return register_persistent_clock(tegra_read_persistent_clock64); } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); +#endif +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer); +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index fd586d0301e7..e78281d07b70 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -121,6 +121,7 @@ enum cpuhp_state { CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, CPUHP_AP_ARM_TWD_STARTING, CPUHP_AP_QCOM_TIMER_STARTING, + CPUHP_AP_TEGRA_TIMER_STARTING, CPUHP_AP_ARMADA_TIMER_STARTING, CPUHP_AP_MARCO_TIMER_STARTING, CPUHP_AP_MIPS_GIC_TIMER_STARTING, From patchwork Sat Feb 23 13:07:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 159123 Delivered-To: patch@linaro.org Received: by 2002:a02:5cc1:0:0:0:0:0 with SMTP id w62csp33846jad; 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[77.130.126.189]) by smtp.gmail.com with ESMTPSA id i12sm7830746wrq.21.2019.02.23.05.08.36 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 23 Feb 2019 05:08:37 -0800 (PST) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Joseph Lo , Thierry Reding , Jon Hunter , Thierry Reding , Mikko Perttunen , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 18/18] soc/tegra: default select TEGRA_TIMER for Tegra210 Date: Sat, 23 Feb 2019 14:07:06 +0100 Message-Id: <20190223130707.16704-18-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190223130707.16704-1-daniel.lezcano@linaro.org> References: <20190223130707.16704-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Joseph Lo The tegra timer is necessary for Tegra210 to support CPU idle power-down state. So select it by default. Signed-off-by: Joseph Lo Acked-by: Thierry Reding Acked-by: Jon Hunter Signed-off-by: Daniel Lezcano --- drivers/soc/tegra/Kconfig | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/soc/tegra/Kconfig b/drivers/soc/tegra/Kconfig index fe4481676da6..a0b03443d8c1 100644 --- a/drivers/soc/tegra/Kconfig +++ b/drivers/soc/tegra/Kconfig @@ -76,6 +76,7 @@ config ARCH_TEGRA_210_SOC select PINCTRL_TEGRA210 select SOC_TEGRA_FLOWCTRL select SOC_TEGRA_PMC + select TEGRA_TIMER help Enable support for the NVIDIA Tegra210 SoC. Also known as Tegra X1, the Tegra210 has four Cortex-A57 cores paired with four Cortex-A53