From patchwork Sat Oct 1 03:03:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 611459 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5841C433F5 for ; Sat, 1 Oct 2022 03:05:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232358AbiJADFY (ORCPT ); Fri, 30 Sep 2022 23:05:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44932 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231805AbiJADFO (ORCPT ); Fri, 30 Sep 2022 23:05:14 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DED3422C3; Fri, 30 Sep 2022 20:04:54 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 291307wE016494; Sat, 1 Oct 2022 03:04:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=nK+w0u1qJP8hgBCJjYl2ABaMvW8XisKwAxeSR/2K+x8=; b=IvRnHzXeYEZpVjL+pnG1Fao+3DbtgEHZiMXMwSm1zsOgX/k1065XSj5gXkHdrkUPjPLR QA5YYumyQ8M/VnQldk6pd3paExErPtL8l1rTAX8iKxvRcBurMc7hTzwNnU44Teq2nH5G nk2M2KyP7NizlAoW9a8IwAXOo1T0T0opvetqMQp7JeJZ41j8vVgKwhvLytnuBQ618uUl z+ASWrj2MkxTT542lxb9GOwRhf5aWaMPozIndKn+Pm2FC3MEIr58/3iyAr16zQS1V7cU Mjdwi6/sV1EhAtl0Ri+80lfscFtym66v/1F2ASr+lhJm7eCVy2zDeFEann0Bvo2ZRCdg og== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jxcjf81ce-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 01 Oct 2022 03:04:34 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29134X9A003163 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 1 Oct 2022 03:04:33 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:04:32 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , "Krzysztof Kozlowski" , Thomas Gleixner , Marc Zyngier CC: , , , , Melody Olvera Subject: [PATCH 1/5] dt-bindings: clock: Add QDU1000 and QRU1000 GCC clock bindings Date: Fri, 30 Sep 2022 20:03:59 -0700 Message-ID: <20221001030403.27659-2-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030403.27659-1-quic_molvera@quicinc.com> References: <20221001030403.27659-1-quic_molvera@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: JkMm9wQxyf_ilca24QhCU0MtBwQY33-t X-Proofpoint-ORIG-GUID: JkMm9wQxyf_ilca24QhCU0MtBwQY33-t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-01_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 mlxscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 impostorscore=0 spamscore=0 phishscore=0 malwarescore=0 clxscore=1015 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210010015 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device tree bindings for global clock controller on QDU1000 and QRU1000 SoCs. Signed-off-by: Melody Olvera --- .../bindings/clock/qcom,gcc-qdru1000.yaml | 74 ++++++++ include/dt-bindings/clock/qcom,gcc-qdru1000.h | 170 ++++++++++++++++++ 2 files changed, 244 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-qdru1000.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-qdru1000.h diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-qdru1000.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-qdru1000.yaml new file mode 100644 index 000000000000..d92f558d547c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-qdru1000.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-qdru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding for QDU1000 and QRU1000 + +maintainers: + - Melody Olvera + +description: | + Qualcomm global clock control module which supports the clocks, resets and + power domains on QDU1000 and QRU1000 + + See also: + - dt-bindings/clock/qcom,gcc-qdru1000.h + +properties: + compatible: + enum: + - qcom,gcc-qdu1000 + - qcom,gcc-qru1000 + + clocks: + items: + - description: Board XO source + - description: Sleep clock source + - description: PCIE 0 Pipe clock source (Optional clock) + - description: PCIE 0 Phy Auxiliary clock source (Optional clock) + - description: USB3 Phy wrapper pipe clock source (Optional clock) + minItems: 2 + + clock-names: + items: + - const: bi_tcxo + - const: sleep_clk + - const: pcie_0_pipe_clk # Optional clock + - const: pcie_0_phy_aux_clk # Optional clock + - const: usb3_phy_wrapper_gcc_usb30_pipe_clk # Optional clock + minItems: 2 + + '#clock-cells': + const: 1 + + '#reset-cells': + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + clock-controller@100000 { + compatible = "qcom,gcc-qdu1000"; + reg = <0x00100000 0x001f4200>; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; + clock-names = "bi_tcxo", "sleep_clk"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + +... diff --git a/include/dt-bindings/clock/qcom,gcc-qdru1000.h b/include/dt-bindings/clock/qcom,gcc-qdru1000.h new file mode 100644 index 000000000000..cdc5d1a6a007 --- /dev/null +++ b/include/dt-bindings/clock/qcom,gcc-qdru1000.h @@ -0,0 +1,170 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2021-2022, Qualcomm Innovation Center, Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QDRU1000_H +#define _DT_BINDINGS_CLK_QCOM_GCC_QDRU1000_H + +/* GCC clocks */ +#define GCC_GPLL0 0 +#define GCC_GPLL0_OUT_EVEN 1 +#define GCC_GPLL1 2 +#define GCC_GPLL2 3 +#define GCC_GPLL2_OUT_EVEN 4 +#define GCC_GPLL3 5 +#define GCC_GPLL4 6 +#define GCC_GPLL5 7 +#define GCC_GPLL5_OUT_EVEN 8 +#define GCC_GPLL6 9 +#define GCC_GPLL7 10 +#define GCC_GPLL8 11 +#define GCC_AGGRE_NOC_ECPRI_DMA_CLK 12 +#define GCC_AGGRE_NOC_ECPRI_DMA_CLK_SRC 13 +#define GCC_AGGRE_NOC_ECPRI_GSI_CLK_SRC 14 +#define GCC_BOOT_ROM_AHB_CLK 15 +#define GCC_CFG_NOC_ECPRI_CC_AHB_CLK 16 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 +#define GCC_DDRSS_ECPRI_DMA_CLK 18 +#define GCC_ECPRI_AHB_CLK 19 +#define GCC_ECPRI_CC_GPLL0_CLK_SRC 20 +#define GCC_ECPRI_CC_GPLL1_EVEN_CLK_SRC 21 +#define GCC_ECPRI_CC_GPLL2_EVEN_CLK_SRC 22 +#define GCC_ECPRI_CC_GPLL3_CLK_SRC 23 +#define GCC_ECPRI_CC_GPLL4_CLK_SRC 24 +#define GCC_ECPRI_CC_GPLL5_EVEN_CLK_SRC 25 +#define GCC_ECPRI_XO_CLK 26 +#define GCC_ETH_DBG_SNOC_AXI_CLK 27 +#define GCC_GEMNOC_PCIE_QX_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP1_CLK_SRC 30 +#define GCC_GP2_CLK 31 +#define GCC_GP2_CLK_SRC 32 +#define GCC_GP3_CLK 33 +#define GCC_GP3_CLK_SRC 34 +#define GCC_PCIE_0_AUX_CLK 35 +#define GCC_PCIE_0_AUX_CLK_SRC 36 +#define GCC_PCIE_0_CFG_AHB_CLK 37 +#define GCC_PCIE_0_CLKREF_EN 38 +#define GCC_PCIE_0_MSTR_AXI_CLK 39 +#define GCC_PCIE_0_PHY_AUX_CLK 40 +#define GCC_PCIE_0_PHY_RCHNG_CLK 41 +#define GCC_PCIE_0_PHY_RCHNG_CLK_SRC 42 +#define GCC_PCIE_0_PIPE_CLK 43 +#define GCC_PCIE_0_SLV_AXI_CLK 44 +#define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 +#define GCC_PDM2_CLK 46 +#define GCC_PDM2_CLK_SRC 47 +#define GCC_PDM_AHB_CLK 48 +#define GCC_PDM_XO4_CLK 49 +#define GCC_QMIP_ANOC_PCIE_CLK 50 +#define GCC_QMIP_ECPRI_DMA0_CLK 51 +#define GCC_QMIP_ECPRI_DMA1_CLK 52 +#define GCC_QMIP_ECPRI_GSI_CLK 53 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 54 +#define GCC_QUPV3_WRAP0_CORE_CLK 55 +#define GCC_QUPV3_WRAP0_S0_CLK 56 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 57 +#define GCC_QUPV3_WRAP0_S1_CLK 58 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 59 +#define GCC_QUPV3_WRAP0_S2_CLK 60 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 61 +#define GCC_QUPV3_WRAP0_S3_CLK 62 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 63 +#define GCC_QUPV3_WRAP0_S4_CLK 64 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 65 +#define GCC_QUPV3_WRAP0_S5_CLK 66 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 67 +#define GCC_QUPV3_WRAP0_S6_CLK 68 +#define GCC_QUPV3_WRAP0_S6_CLK_SRC 69 +#define GCC_QUPV3_WRAP0_S7_CLK 70 +#define GCC_QUPV3_WRAP0_S7_CLK_SRC 71 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 72 +#define GCC_QUPV3_WRAP1_CORE_CLK 73 +#define GCC_QUPV3_WRAP1_S0_CLK 74 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 75 +#define GCC_QUPV3_WRAP1_S1_CLK 76 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 77 +#define GCC_QUPV3_WRAP1_S2_CLK 78 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 79 +#define GCC_QUPV3_WRAP1_S3_CLK 80 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 81 +#define GCC_QUPV3_WRAP1_S4_CLK 82 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 83 +#define GCC_QUPV3_WRAP1_S5_CLK 84 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 85 +#define GCC_QUPV3_WRAP1_S6_CLK 86 +#define GCC_QUPV3_WRAP1_S6_CLK_SRC 87 +#define GCC_QUPV3_WRAP1_S7_CLK 88 +#define GCC_QUPV3_WRAP1_S7_CLK_SRC 89 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 90 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 91 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 92 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 93 +#define GCC_SDCC5_AHB_CLK 94 +#define GCC_SDCC5_APPS_CLK 95 +#define GCC_SDCC5_APPS_CLK_SRC 96 +#define GCC_SDCC5_ICE_CORE_CLK 97 +#define GCC_SDCC5_ICE_CORE_CLK_SRC 98 +#define GCC_SNOC_CNOC_GEMNOC_PCIE_QX_CLK 99 +#define GCC_SNOC_CNOC_GEMNOC_PCIE_SOUTH_QX_CLK 100 +#define GCC_SNOC_CNOC_PCIE_QX_CLK 101 +#define GCC_SNOC_PCIE_SF_CENTER_QX_CLK 102 +#define GCC_SNOC_PCIE_SF_SOUTH_QX_CLK 103 +#define GCC_TSC_CFG_AHB_CLK 104 +#define GCC_TSC_CLK_SRC 105 +#define GCC_TSC_CNTR_CLK 106 +#define GCC_TSC_ETU_CLK 107 +#define GCC_USB2_CLKREF_EN 108 +#define GCC_USB30_PRIM_MASTER_CLK 109 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 +#define GCC_USB30_PRIM_MOCK_UTMI_POSTDIV_CLK_SRC 113 +#define GCC_USB30_PRIM_SLEEP_CLK 114 +#define GCC_USB3_PRIM_PHY_AUX_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 +#define GCC_SM_BUS_AHB_CLK 119 +#define GCC_SM_BUS_XO_CLK 120 +#define GCC_SM_BUS_XO_CLK_SRC 121 +#define GCC_USB3_PRIM_PHY_PIPE_CLK_SRC 122 +#define GCC_ETH_100G_C2C_HM_APB_CLK 123 +#define GCC_ETH_100G_FH_HM_APB_0_CLK 124 +#define GCC_ETH_100G_FH_HM_APB_1_CLK 125 +#define GCC_ETH_100G_FH_HM_APB_2_CLK 126 +#define GCC_ETH_DBG_C2C_HM_APB_CLK 127 +#define GCC_AGGRE_NOC_ECPRI_GSI_CLK 128 +#define GCC_PCIE_0_PIPE_CLK_SRC 129 +#define GCC_PCIE_0_PHY_AUX_CLK_SRC 130 + +/* GCC resets */ +#define GCC_ECPRI_CC_BCR 0 +#define GCC_ECPRI_SS_BCR 1 +#define GCC_ETH_WRAPPER_BCR 2 +#define GCC_PCIE_0_BCR 3 +#define GCC_PCIE_0_LINK_DOWN_BCR 4 +#define GCC_PCIE_0_NOCSR_COM_PHY_BCR 5 +#define GCC_PCIE_0_PHY_BCR 6 +#define GCC_PCIE_0_PHY_NOCSR_COM_PHY_BCR 7 +#define GCC_PCIE_PHY_CFG_AHB_BCR 8 +#define GCC_PCIE_PHY_COM_BCR 9 +#define GCC_PDM_BCR 10 +#define GCC_QUPV3_WRAPPER_0_BCR 11 +#define GCC_QUPV3_WRAPPER_1_BCR 12 +#define GCC_QUSB2PHY_PRIM_BCR 13 +#define GCC_QUSB2PHY_SEC_BCR 14 +#define GCC_SDCC5_BCR 15 +#define GCC_TCSR_PCIE_BCR 16 +#define GCC_TSC_BCR 17 +#define GCC_USB30_PRIM_BCR 18 +#define GCC_USB3_DP_PHY_PRIM_BCR 19 +#define GCC_USB3_DP_PHY_SEC_BCR 20 +#define GCC_USB3_PHY_PRIM_BCR 21 +#define GCC_USB3_PHY_SEC_BCR 22 +#define GCC_USB3PHY_PHY_PRIM_BCR 23 +#define GCC_USB3PHY_PHY_SEC_BCR 24 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 25 + +#endif From patchwork Sat Oct 1 03:06:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 611815 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 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Signed-off-by: Melody Olvera --- Documentation/devicetree/bindings/arm/qcom.yaml | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index fb1d00bcc847..1cfd92f4ab5d 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -61,6 +61,8 @@ description: | sm8250 sm8350 sm8450 + qdu1000 + qru1000 The 'board' element must be one of the following strings: @@ -76,6 +78,7 @@ description: | mtp qrd sbc + x100 The 'soc_version' and 'board_version' elements take the form of v. where the minor number may be omitted when it's zero, i.e. v1.0 is the same @@ -718,6 +721,19 @@ properties: - qcom,sm8450-qrd - const: qcom,sm8450 + - description: Qualcomm Technologies, Inc. Distributed Unit 1000 platform + - items: + - enum: + - qcom,qdu1000-idp + - qcom,qdu1000-x100 + - const: qcom,qdu1000 + + - description: Qualcomm Technologies, Inc. Radio Unit 1000 platform + - items: + - enum: + -qcom,qru1000-idp + - const: qcom,qru1000 + additionalProperties: true ... From patchwork Sat Oct 1 03:06:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 611452 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29BDDC4321E for ; Sat, 1 Oct 2022 03:09:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232888AbiJADI7 (ORCPT ); Fri, 30 Sep 2022 23:08:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232362AbiJADHn (ORCPT ); Fri, 30 Sep 2022 23:07:43 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9EAD6DD34C; Fri, 30 Sep 2022 20:06:59 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2912veZ7027910; Sat, 1 Oct 2022 03:06:56 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=3LDcN/d6wB3yOfoHmvrdmHWUtojlpULg+lZOZ/55Pzs=; b=k8NctpzhO/pSusNrm3dfesZ/I9SH+fUsTeZJNnPc00ZEpkHN6sMTsaTOzWuaaKzd/TAT XAJWjq+LeGbQhoIgjxa4/kJ6ffWsiCNhbnHbSLf++L2S3eGB73YLhX8lmRkC3D5wiRnR 2wg2UiWx/qkPL6kNqjjexazHBd/MAQx8ayaQwyCTzOOFAwTdBNnX7r7OwfhstcwJbvQ+ NC1UVyrVdXJJk0TW+J9Murd49NGDpanmGNJYhyACt1cWST4N1PqV5O5/pmny3yjWDcV9 PXoHbG9ENZt/RJloi6oZBpMK45ijhbmCko2wIDQUgfj5c13SlF8oBx/KI7jNG0D2LPHD vg== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jxd58g0de-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 01 Oct 2022 03:06:56 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29136tms004981 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 1 Oct 2022 03:06:55 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:06:54 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Ulf Hansson CC: Bhupesh Sharma , , , , , Melody Olvera Subject: [PATCH 3/5] dt-bindings: power: rpmpd: Add QDU1000/QRU1000 to rpmpd binding Date: Fri, 30 Sep 2022 20:06:39 -0700 Message-ID: <20221001030641.29354-4-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030641.29354-1-quic_molvera@quicinc.com> References: <20221001030641.29354-1-quic_molvera@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: T_dGoI5_yUgsYzn1MyAiNlk8mD3O5Ibb X-Proofpoint-ORIG-GUID: T_dGoI5_yUgsYzn1MyAiNlk8mD3O5Ibb X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-01_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxscore=0 bulkscore=0 suspectscore=0 malwarescore=0 mlxlogscore=805 priorityscore=1501 clxscore=1015 spamscore=0 adultscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210010016 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add compatible and constants for the power domains exposed by the RPMH in the Qualcomm QDU1000 and QRU1000 platforms. Signed-off-by: Melody Olvera --- Documentation/devicetree/bindings/power/qcom,rpmpd.yaml | 2 ++ include/dt-bindings/power/qcom-rpmpd.h | 6 ++++++ 2 files changed, 8 insertions(+) diff --git a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml index 3934a2b44894..7343cfc91262 100644 --- a/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml +++ b/Documentation/devicetree/bindings/power/qcom,rpmpd.yaml @@ -44,6 +44,8 @@ properties: - qcom,sm8250-rpmhpd - qcom,sm8350-rpmhpd - qcom,sm8450-rpmhpd + - qcom,qdu1000-rpmhpd + - qcom,qru1000-rpmhpd '#power-domain-cells': const: 1 diff --git a/include/dt-bindings/power/qcom-rpmpd.h b/include/dt-bindings/power/qcom-rpmpd.h index d81de63ae31c..e0d9e5b48a4d 100644 --- a/include/dt-bindings/power/qcom-rpmpd.h +++ b/include/dt-bindings/power/qcom-rpmpd.h @@ -91,6 +91,12 @@ #define SM8450_MXC_AO 11 #define SM8450_MSS 12 +/* QDU1000/QRU1000 Power Domain Indexes */ +#define QDRU1000_EBI 0 +#define QDRU1000_MSS 1 +#define QDRU1000_CX 2 +#define QDRU1000_MX 3 + /* SC7180 Power Domain Indexes */ #define SC7180_CX 0 #define SC7180_CX_AO 1 From patchwork Sat Oct 1 03:06:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 611453 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5E49C433F5 for ; Sat, 1 Oct 2022 03:08:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232853AbiJADIx (ORCPT ); Fri, 30 Sep 2022 23:08:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46918 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232255AbiJADHg (ORCPT ); Fri, 30 Sep 2022 23:07:36 -0400 Received: from alexa-out-sd-01.qualcomm.com (alexa-out-sd-01.qualcomm.com [199.106.114.38]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E1B995FE1; Fri, 30 Sep 2022 20:06:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1664593615; x=1696129615; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=nJ5xQYKUQaO0xTDVuI0a+cGf8oFR+0COgrbcWmyWzhk=; b=SbqYbYmZ2KaBajtzmbogAbpn3T/5NUVfRH+2z8WaxBjwy9377eX+Wy1U 721KfHGmhMwmS+6ALCJDqgiizkLyoZx+RZRyk75J8cvcLkLCdXAShtmLE d6EuJIqfmKIFnOafw7FaW/0wqgdMRV5D7flw8+kzy8Nc9rIzYwiISmB5t E=; Received: from unknown (HELO ironmsg-SD-alpha.qualcomm.com) ([10.53.140.30]) by alexa-out-sd-01.qualcomm.com with ESMTP; 30 Sep 2022 20:06:55 -0700 X-QCInternal: smtphost Received: from nasanex01b.na.qualcomm.com ([10.46.141.250]) by ironmsg-SD-alpha.qualcomm.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 30 Sep 2022 20:06:55 -0700 Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:06:55 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Ulf Hansson CC: Bhupesh Sharma , , , , , Melody Olvera Subject: [PATCH 4/5] soc: qcom: rpmhpd: Add QDU1000/QRU1000 power domains Date: Fri, 30 Sep 2022 20:06:40 -0700 Message-ID: <20221001030641.29354-5-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030641.29354-1-quic_molvera@quicinc.com> References: <20221001030641.29354-1-quic_molvera@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the power domains exposed by RPMH in the Qualcomm QDU1000 and QRU1000 platforms. Signed-off-by: Melody Olvera Reviewed-by: Dmitry Baryshkov --- drivers/soc/qcom/rpmhpd.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/soc/qcom/rpmhpd.c b/drivers/soc/qcom/rpmhpd.c index 092f6ab09acf..f70573cbc636 100644 --- a/drivers/soc/qcom/rpmhpd.c +++ b/drivers/soc/qcom/rpmhpd.c @@ -353,6 +353,19 @@ static const struct rpmhpd_desc sm8450_desc = { .num_pds = ARRAY_SIZE(sm8450_rpmhpds), }; +/* QDU1000/QRU1000 RPMH powerdomains */ +static struct rpmhpd *qdru1000_rpmhpds[] = { + [QDRU1000_CX] = &cx, + [QDRU1000_EBI] = &ebi, + [QDRU1000_MSS] = &mss, + [QDRU1000_MX] = &mx, +}; + +static const struct rpmhpd_desc qdru1000_desc = { + .rpmhpds = qdru1000_rpmhpds, + .num_pds = ARRAY_SIZE(qdru1000_rpmhpds), +}; + /* SC7180 RPMH powerdomains */ static struct rpmhpd *sc7180_rpmhpds[] = { [SC7180_CX] = &cx_w_mx_parent, From patchwork Sat Oct 1 03:06:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Melody Olvera X-Patchwork-Id: 611451 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5BB53C4332F for ; Sat, 1 Oct 2022 03:09:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232908AbiJADJD (ORCPT ); Fri, 30 Sep 2022 23:09:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44876 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232371AbiJADHo (ORCPT ); Fri, 30 Sep 2022 23:07:44 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 50822E318C; Fri, 30 Sep 2022 20:07:00 -0700 (PDT) Received: from pps.filterd (m0279872.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 2912puFL012021; Sat, 1 Oct 2022 03:06:57 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=IjK9zVJOXKYgoA3dvxjM9g3vnQSeUVYSH6OEJu8iyz0=; b=MILBwbajVmUSTqxZinz3/BNELiqw4gPHEfUb0LwmiazAtKA7fRMS9sCdLLiYtqEBjp2+ ZA6SjZCvQ+UG6MrpZR4kf86QblOTpz72CBaH0GvnL8yDNKd/GUc19skch8k9L3ZNINq4 BG4LxNJgsO7ZcqO58GNk9Vz9cJj5D3Gp8uJIsZdb7hJ7cIFpJ3C9FAJFqKosN2mGVIWa jYQljorEEBTXgzNB9U6iRuQx76bEGZ56UBv3FWNgMEXSxDU8PXvBigBuF9JPS98z5jNT nI31euigKndFEbipCCYANZHuuJCxnSxSuonpAynZhrIrIi9RJ2WPVRTDileC6nGXv5CC WQ== Received: from nasanppmta03.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3jwkee47qx-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 01 Oct 2022 03:06:57 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 29136uiH004990 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Sat, 1 Oct 2022 03:06:56 GMT Received: from hu-molvera-sd.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Fri, 30 Sep 2022 20:06:55 -0700 From: Melody Olvera To: Andy Gross , Bjorn Andersson , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Ulf Hansson CC: Bhupesh Sharma , , , , , Melody Olvera Subject: [PATCH 5/5] soc: qcom: socinfo: Add QDU1000/QRU1000 and variant IDs Date: Fri, 30 Sep 2022 20:06:41 -0700 Message-ID: <20221001030641.29354-6-quic_molvera@quicinc.com> X-Mailer: git-send-email 2.37.3 In-Reply-To: <20221001030641.29354-1-quic_molvera@quicinc.com> References: <20221001030641.29354-1-quic_molvera@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 1LpebKUp_PBJd4M8bemCWfsgUCaIP8OP X-Proofpoint-ORIG-GUID: 1LpebKUp_PBJd4M8bemCWfsgUCaIP8OP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.528,FMLib:17.11.122.1 definitions=2022-10-01_02,2022-09-29_03,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 adultscore=0 bulkscore=0 phishscore=0 mlxlogscore=979 spamscore=0 suspectscore=0 impostorscore=0 lowpriorityscore=0 malwarescore=0 priorityscore=1501 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2209130000 definitions=main-2210010016 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add soc IDs for QDU1000 and QRU1000 and their variants. Signed-off-by: Melody Olvera --- drivers/soc/qcom/socinfo.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/soc/qcom/socinfo.c b/drivers/soc/qcom/socinfo.c index 4554fb8655d3..d10942b1b9a7 100644 --- a/drivers/soc/qcom/socinfo.c +++ b/drivers/soc/qcom/socinfo.c @@ -334,6 +334,12 @@ static const struct soc_id soc_id[] = { { 482, "SM8450" }, { 487, "SC7280" }, { 495, "SC7180P" }, + { 539, "QRU1000" }, + { 545, "QDU1000" }, + { 587, "QDU1010" }, + { 588, "QRU1032" }, + { 589, "QRU1052" }, + { 590, "QRU1062" }, }; static const char *socinfo_machine(struct device *dev, unsigned int id)