From patchwork Fri Feb 22 18:04:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 159045 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2024366jaa; Fri, 22 Feb 2019 10:05:04 -0800 (PST) X-Google-Smtp-Source: AHgI3IZOy9G9262M6+vxsec8Q40BcZozqgkzqAmlg0qbdV6/aL3TV8qJmlcbDspA+954Kx1PAYmZ X-Received: by 2002:a62:5385:: with SMTP id h127mr5391816pfb.10.1550858704694; Fri, 22 Feb 2019 10:05:04 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550858704; cv=none; d=google.com; s=arc-20160816; b=I55H8QbX2sR5swwo7eM3MVjZsYucGP/8ecLd8q3NMdEPreTrSGjlqdW8hQNAdq6w6A TQVYiWZnXl11p0vMPTibBOzdG2i+WZHl477mk1QSeMWpds581hbbPLYfg6M+/4kTS0vl TIwMETf+KMoumkFWYGMvULd6lunDxclS1uN6Wgc92zt1ZA14LE9ximvqYqePX9woYfBC 3iE5zw6XiRylyUJr/00WOFCdMNszjyczIHWlmyfYH4MhKP+hfl/ky9MMyHVd4nF3CpQ9 d4E9JFLXySj4mQX7liv5ytE/O2qWMQBBLpWxtpIm3vY4qBMSUI+9C3tNtcNfYK9yspaZ XK3w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=QMKz3vuIBIM6AojhnAMV6y5LVpSvQpMGCecyRKnRWws=; b=GGB7oKPNugJHhE7Dx7FYDSHy/XjjbIEMWv2Al64jkh6hCPOpZTiosuTZti89z/O6N4 Pm2VVLTWY3mVaXI+eQvZ6Zxzg8gjqY45AG7RTGE7a3LnoZ0huOdXEVqu1Rv36umRGH8G w2sKfKo+oOtfPX+k89+EHR5cnYTXmOffQZhKOS0rxBjaraZpflpXfabG9ISvrXrRp+ND ij5P0Z7mjci5342dhZromi/HVmLDcKtY8pmJjyY8QS6nWpy6Hv83uw36fRTPNuS0GiWv ozM5s9xn0dbcvtUJapRg3EWjmG6a/QpOgJJP7tWCX/Caov++b0RHXkQkkUzEZwKtiicA wAHg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v23si1894517pgn.542.2019.02.22.10.05.04; Fri, 22 Feb 2019 10:05:04 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727652AbfBVSFD (ORCPT + 32 others); Fri, 22 Feb 2019 13:05:03 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:38156 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727628AbfBVSFC (ORCPT ); Fri, 22 Feb 2019 13:05:02 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7B479165C; Fri, 22 Feb 2019 10:05:01 -0800 (PST) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 008523F5C1; Fri, 22 Feb 2019 10:04:59 -0800 (PST) From: Will Deacon To: linux-arch@vger.kernel.org Cc: linux-kernel@vger.kernel.org, andrew.murray@arm.com, arnd@arndb.de, catalin.marinas@arm.com, geert@linux-m68k.org, palmer@sifive.com, Will Deacon Subject: [PATCH v2 1/3] asm-generic/io: Pass result of I/O accessor to __io_[p]ar() Date: Fri, 22 Feb 2019 18:04:52 +0000 Message-Id: <20190222180454.5992-2-will.deacon@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190222180454.5992-1-will.deacon@arm.com> References: <20190222180454.5992-1-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The inX() and readX() I/O accessors must enforce ordering against subsequent calls to the delay() routines, so that a read-back from a device can be used to postpone a subsequent write to the same device. On some architectures, including arm64, this ordering can only be achieved by creating a dependency on the value returned by the I/O accessor operation, so we need to pass the value we read to the __io_par() and __io_ar() macros in these cases. Acked-by: Arnd Bergmann Reported-by: Andrew Murray Signed-off-by: Will Deacon --- include/asm-generic/io.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) -- 2.11.0 diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index d356f802945a..303871651f8a 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -32,9 +32,9 @@ /* prevent prefetching of coherent DMA data ahead of a dma-complete */ #ifndef __io_ar #ifdef rmb -#define __io_ar() rmb() +#define __io_ar(v) rmb() #else -#define __io_ar() barrier() +#define __io_ar(v) barrier() #endif #endif @@ -65,7 +65,7 @@ #endif #ifndef __io_par -#define __io_par() __io_ar() +#define __io_par(v) __io_ar(v) #endif @@ -158,7 +158,7 @@ static inline u8 readb(const volatile void __iomem *addr) __io_br(); val = __raw_readb(addr); - __io_ar(); + __io_ar(val); return val; } #endif @@ -171,7 +171,7 @@ static inline u16 readw(const volatile void __iomem *addr) __io_br(); val = __le16_to_cpu(__raw_readw(addr)); - __io_ar(); + __io_ar(val); return val; } #endif @@ -184,7 +184,7 @@ static inline u32 readl(const volatile void __iomem *addr) __io_br(); val = __le32_to_cpu(__raw_readl(addr)); - __io_ar(); + __io_ar(val); return val; } #endif @@ -198,7 +198,7 @@ static inline u64 readq(const volatile void __iomem *addr) __io_br(); val = __le64_to_cpu(__raw_readq(addr)); - __io_ar(); + __io_ar(val); return val; } #endif @@ -471,7 +471,7 @@ static inline u8 inb(unsigned long addr) __io_pbr(); val = __raw_readb(PCI_IOBASE + addr); - __io_par(); + __io_par(val); return val; } #endif @@ -484,7 +484,7 @@ static inline u16 inw(unsigned long addr) __io_pbr(); val = __le16_to_cpu(__raw_readw(PCI_IOBASE + addr)); - __io_par(); + __io_par(val); return val; } #endif @@ -497,7 +497,7 @@ static inline u32 inl(unsigned long addr) __io_pbr(); val = __le32_to_cpu(__raw_readl(PCI_IOBASE + addr)); - __io_par(); + __io_par(val); return val; } #endif From patchwork Fri Feb 22 18:04:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 159047 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2024513jaa; Fri, 22 Feb 2019 10:05:12 -0800 (PST) X-Google-Smtp-Source: AHgI3IYi3p83tPJ6ExYzbDbq2lR0wvrgHwTMEKPFzlVaVa7pkaOFVGhpd5dYuLfyq2chO4kVosM3 X-Received: by 2002:a17:902:fa2:: with SMTP id 31mr5429941plz.75.1550858712891; Fri, 22 Feb 2019 10:05:12 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550858712; cv=none; d=google.com; s=arc-20160816; b=Jv4+aO294njAd1USWco1F3n0t7XF92WU6xM6zBHrJ7yJpPXTEUP+laeIDjvaegFeMs ldgCfvoqmTdQX+dbcGecTRM+MT6kJMR7Mj/+bJbHy4NFz4NaxxxaxVsPNVQU1EcxmqP8 OWepyIVIesUDMXnj2WJqPjfc9RGq5xgQbSdPSeVFQMyF/v+3XZDoZk9B6DrI47VhFKa/ qy4Tb2MqgJYf/PpybaL3N5wjlCAkQb+N8qW8orD6JTkawsb5BLkMMISpfhbUE9gsSnn7 DFObmuED5CmUq2WjQxB81ieLVHcgMGk2y5vc+fSjCKTwGfz4TuKGNqBgKxGR2B5uwMwI ni+g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from; bh=y7ptIV6pfK/ZiHYmVwjNkF4QygCuS13BED1xBjhiu6E=; b=u0zI7Jl64aVgoSygKKRXIgloJ4Xl4al/2qjUCWtGhL29J5wpP5dhLDhVO96zVtvm99 jff2CM+T1Vq5T2E3X7N9vUlNsq4pTcuvINhGO4qTl93FP+M7lepcit5lwF72QnYp5/OC Cp0CYITQi0L94dFCW/9O7Qsx5C8vrwokdLG3dxykzzorxAUvnQYS18gdvESxrhMG9SzE AEaUBqJHRkkWETKP1fNgkH4OWNs4ewFTksNaNfH4rgussvUVlrVhB9ORTDM94HNfNI40 Tpl+HNAbD81cyTVHThepnKGhtGPBAGIrsiRsKIWkNq4jqj+d/raIpbpSGIc2HSsnmLq4 W7dA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id v23si1894517pgn.542.2019.02.22.10.05.12; Fri, 22 Feb 2019 10:05:12 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727667AbfBVSFF (ORCPT + 32 others); Fri, 22 Feb 2019 13:05:05 -0500 Received: from foss.arm.com ([217.140.101.70]:38168 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727655AbfBVSFD (ORCPT ); Fri, 22 Feb 2019 13:05:03 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3F49015AB; Fri, 22 Feb 2019 10:05:03 -0800 (PST) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id B96FA3F5C1; Fri, 22 Feb 2019 10:05:01 -0800 (PST) From: Will Deacon To: linux-arch@vger.kernel.org Cc: linux-kernel@vger.kernel.org, andrew.murray@arm.com, arnd@arndb.de, catalin.marinas@arm.com, geert@linux-m68k.org, palmer@sifive.com, Will Deacon Subject: [PATCH v2 2/3] riscv: io: Update __io_[p]ar() macros to take an argument Date: Fri, 22 Feb 2019 18:04:53 +0000 Message-Id: <20190222180454.5992-3-will.deacon@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190222180454.5992-1-will.deacon@arm.com> References: <20190222180454.5992-1-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The definitions of the __io_[p]ar() macros in asm-generic/io.h take the value returned by the preceding I/O read as an argument so that architectures can use this to create order with a subsequent delayX() routine using a dependency. Update the riscv barrier definitions to match, although the argument is currently unused. Suggested-by: Arnd Bergmann Reviewed-by: Palmer Dabbelt Signed-off-by: Will Deacon --- arch/riscv/include/asm/io.h | 36 ++++++++++++++++++------------------ 1 file changed, 18 insertions(+), 18 deletions(-) -- 2.11.0 diff --git a/arch/riscv/include/asm/io.h b/arch/riscv/include/asm/io.h index b269451e7e85..1d9c1376dc64 100644 --- a/arch/riscv/include/asm/io.h +++ b/arch/riscv/include/asm/io.h @@ -163,20 +163,20 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * doesn't define any ordering between the memory space and the I/O space. */ #define __io_br() do {} while (0) -#define __io_ar() __asm__ __volatile__ ("fence i,r" : : : "memory"); +#define __io_ar(v) __asm__ __volatile__ ("fence i,r" : : : "memory"); #define __io_bw() __asm__ __volatile__ ("fence w,o" : : : "memory"); #define __io_aw() do {} while (0) -#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(); __v; }) -#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(); __v; }) -#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(); __v; }) +#define readb(c) ({ u8 __v; __io_br(); __v = readb_cpu(c); __io_ar(__v); __v; }) +#define readw(c) ({ u16 __v; __io_br(); __v = readw_cpu(c); __io_ar(__v); __v; }) +#define readl(c) ({ u32 __v; __io_br(); __v = readl_cpu(c); __io_ar(__v); __v; }) #define writeb(v,c) ({ __io_bw(); writeb_cpu((v),(c)); __io_aw(); }) #define writew(v,c) ({ __io_bw(); writew_cpu((v),(c)); __io_aw(); }) #define writel(v,c) ({ __io_bw(); writel_cpu((v),(c)); __io_aw(); }) #ifdef CONFIG_64BIT -#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(); __v; }) +#define readq(c) ({ u64 __v; __io_br(); __v = readq_cpu(c); __io_ar(__v); __v; }) #define writeq(v,c) ({ __io_bw(); writeq_cpu((v),(c)); __io_aw(); }) #endif @@ -198,20 +198,20 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) * writes. */ #define __io_pbr() __asm__ __volatile__ ("fence io,i" : : : "memory"); -#define __io_par() __asm__ __volatile__ ("fence i,ior" : : : "memory"); +#define __io_par(v) __asm__ __volatile__ ("fence i,ior" : : : "memory"); #define __io_pbw() __asm__ __volatile__ ("fence iow,o" : : : "memory"); #define __io_paw() __asm__ __volatile__ ("fence o,io" : : : "memory"); -#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) -#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) -#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(); __v; }) +#define inb(c) ({ u8 __v; __io_pbr(); __v = readb_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) +#define inw(c) ({ u16 __v; __io_pbr(); __v = readw_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) +#define inl(c) ({ u32 __v; __io_pbr(); __v = readl_cpu((void*)(PCI_IOBASE + (c))); __io_par(__v); __v; }) #define outb(v,c) ({ __io_pbw(); writeb_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) #define outw(v,c) ({ __io_pbw(); writew_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) #define outl(v,c) ({ __io_pbw(); writel_cpu((v),(void*)(PCI_IOBASE + (c))); __io_paw(); }) #ifdef CONFIG_64BIT -#define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(); __v; }) +#define inq(c) ({ u64 __v; __io_pbr(); __v = readq_cpu((void*)(c)); __io_par(__v); __v; }) #define outq(v,c) ({ __io_pbw(); writeq_cpu((v),(void*)(c)); __io_paw(); }) #endif @@ -254,16 +254,16 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) afence; \ } -__io_reads_ins(reads, u8, b, __io_br(), __io_ar()) -__io_reads_ins(reads, u16, w, __io_br(), __io_ar()) -__io_reads_ins(reads, u32, l, __io_br(), __io_ar()) +__io_reads_ins(reads, u8, b, __io_br(), __io_ar(addr)) +__io_reads_ins(reads, u16, w, __io_br(), __io_ar(addr)) +__io_reads_ins(reads, u32, l, __io_br(), __io_ar(addr)) #define readsb(addr, buffer, count) __readsb(addr, buffer, count) #define readsw(addr, buffer, count) __readsw(addr, buffer, count) #define readsl(addr, buffer, count) __readsl(addr, buffer, count) -__io_reads_ins(ins, u8, b, __io_pbr(), __io_par()) -__io_reads_ins(ins, u16, w, __io_pbr(), __io_par()) -__io_reads_ins(ins, u32, l, __io_pbr(), __io_par()) +__io_reads_ins(ins, u8, b, __io_pbr(), __io_par(addr)) +__io_reads_ins(ins, u16, w, __io_pbr(), __io_par(addr)) +__io_reads_ins(ins, u32, l, __io_pbr(), __io_par(addr)) #define insb(addr, buffer, count) __insb((void __iomem *)(long)addr, buffer, count) #define insw(addr, buffer, count) __insw((void __iomem *)(long)addr, buffer, count) #define insl(addr, buffer, count) __insl((void __iomem *)(long)addr, buffer, count) @@ -283,10 +283,10 @@ __io_writes_outs(outs, u32, l, __io_pbw(), __io_paw()) #define outsl(addr, buffer, count) __outsl((void __iomem *)(long)addr, buffer, count) #ifdef CONFIG_64BIT -__io_reads_ins(reads, u64, q, __io_br(), __io_ar()) +__io_reads_ins(reads, u64, q, __io_br(), __io_ar(addr)) #define readsq(addr, buffer, count) __readsq(addr, buffer, count) -__io_reads_ins(ins, u64, q, __io_pbr(), __io_par()) +__io_reads_ins(ins, u64, q, __io_pbr(), __io_par(addr)) #define insq(addr, buffer, count) __insq((void __iomem *)addr, buffer, count) __io_writes_outs(writes, u64, q, __io_bw(), __io_aw()) From patchwork Fri Feb 22 18:04:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Will Deacon X-Patchwork-Id: 159046 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp2024436jaa; Fri, 22 Feb 2019 10:05:08 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia99Ktp3cL5lZmdcu4Sb5tnyP7zd/QAza3ZI0VhuV3CMNed7kW8gnx1yP1F6KQcqXR1QYzl X-Received: by 2002:a62:788a:: with SMTP id t132mr5482658pfc.101.1550858708664; Fri, 22 Feb 2019 10:05:08 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550858708; cv=none; d=google.com; s=arc-20160816; b=z1lpJqjXJJnyFBp3xumhNj18lk2UNR0MdtUblFuAcvHwAHaO9t3fidaaOTnAxShuXc VslSsTzMcuh/k6YTGGIZv5ehD7fouW3VXo9PzRWc5TqjnIdMsEMabzwO4vhotvdBLtam mo8ohVQHscgGbIXe/I+numpMLTDhyKX98blNK/FaxBi/1rsDK+0f7tBIXa3BM4paELY6 ScJeYtUqAlR7HfGdfj0M05VOUH0nqN368ntwbEyPg98juAoaK1/HkLP93alblDBYvAv5 1d2B/62bnjNc51VadjgbdCBZRIIfWMpb/zlkSnAEzlrC0qo4i54Y6Y53+LtKUHA76axq ml0g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; 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[209.132.180.67]) by mx.google.com with ESMTP id v23si1894517pgn.542.2019.02.22.10.05.08; Fri, 22 Feb 2019 10:05:08 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727681AbfBVSFH (ORCPT + 32 others); Fri, 22 Feb 2019 13:05:07 -0500 Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:38178 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727656AbfBVSFF (ORCPT ); Fri, 22 Feb 2019 13:05:05 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0E010165C; Fri, 22 Feb 2019 10:05:05 -0800 (PST) Received: from fuggles.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7D9A23F5C1; Fri, 22 Feb 2019 10:05:03 -0800 (PST) From: Will Deacon To: linux-arch@vger.kernel.org Cc: linux-kernel@vger.kernel.org, andrew.murray@arm.com, arnd@arndb.de, catalin.marinas@arm.com, geert@linux-m68k.org, palmer@sifive.com, Will Deacon Subject: [PATCH v2 3/3] arm64: io: Hook up __io_par() for inX() ordering Date: Fri, 22 Feb 2019 18:04:54 +0000 Message-Id: <20190222180454.5992-4-will.deacon@arm.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20190222180454.5992-1-will.deacon@arm.com> References: <20190222180454.5992-1-will.deacon@arm.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Ensure that inX() provides the same ordering guarantees as readX() by hooking up __io_par() so that it maps directly to __iormb(). Reported-by: Andrew Murray Signed-off-by: Will Deacon --- arch/arm64/include/asm/io.h | 1 + 1 file changed, 1 insertion(+) -- 2.11.0 diff --git a/arch/arm64/include/asm/io.h b/arch/arm64/include/asm/io.h index ee723835c1f4..8bb7210ac286 100644 --- a/arch/arm64/include/asm/io.h +++ b/arch/arm64/include/asm/io.h @@ -121,6 +121,7 @@ static inline u64 __raw_readq(const volatile void __iomem *addr) : "memory"); \ }) +#define __io_par(v) __iormb(v) #define __iowmb() wmb() #define mmiowb() do { } while (0)