From patchwork Tue Sep 27 02:55:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 611283 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CBE6C6FA93 for ; Tue, 27 Sep 2022 02:59:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231280AbiI0C7l (ORCPT ); Mon, 26 Sep 2022 22:59:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50586 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230385AbiI0C7F (ORCPT ); Mon, 26 Sep 2022 22:59:05 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5FD3A6C13; Mon, 26 Sep 2022 19:56:36 -0700 (PDT) X-UUID: 8a229ba795224c1c85734df520089a45-20220927 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=EnCltdT6Z6EH/J8fbqpmMgDX4Y07nMwnORWprAExDOA=; b=Rhnrz91+BeB+Ryi2/BhFcSSzivY+PT0t6PwKGYL3CjA0YSJH58K1A4XZbFvqHwdLddq0OJEWquXIxuOkhdezmVRDRDp3HverVEPa178lZtQuJroZm0CrVtR1hObe3/jnsQffjjGcS1lEnXntpyqs0D8UEZp/+Rhu1hq2Ke5LMuc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:17eaf7a3-543d-4ef1-8073-4e35672d9c5b, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1, CLOUDID:0c612aa3-dc04-435c-b19b-71e131a5fc35, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 8a229ba795224c1c85734df520089a45-20220927 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1343028205; Tue, 27 Sep 2022 10:56:26 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n2.mediatek.inc (172.21.101.187) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 27 Sep 2022 10:56:25 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 27 Sep 2022 10:56:25 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Tinghan Shen CC: , , , , , Subject: [PATCH v3 02/11] dt-bindings: remoteproc: mediatek: Support MT8195 dual-core SCP Date: Tue, 27 Sep 2022 10:55:57 +0800 Message-ID: <20220927025606.26673-3-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220927025606.26673-1-tinghan.shen@mediatek.com> References: <20220927025606.26673-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The MT8195 SCP is a dual-core RISC-V MCU. Extend the yaml file to describe the 2nd core as a subnode of the boot core. The configuration register is shared by MT8195 SCP core 0 and core 1. The core 1 can retrieve the information of configuration registers from parent node. Signed-off-by: Tinghan Shen --- .../bindings/remoteproc/mtk,scp.yaml | 97 ++++++++++++++++++- 1 file changed, 92 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml index 786bed897916..c012265be4eb 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -75,6 +75,83 @@ properties: required: - mediatek,rpmsg-name + '#address-cells': + const: 1 + + '#size-cells': + const: 1 + + ranges: true + +patternProperties: + "^scp-c[0-9]+@[a-f0-9]+$": + type: object + description: + The MediaTek SCP integrated to SoC might be a multi-core version. + The other cores are represented as child nodes of the boot core. + There are some integration differences for the IP like the usage of + address translator for translating SoC bus addresses into address space + for the processor. + + Each SCP core has own cache memory. The SRAM and L1TCM are shared by + cores. The power of cache, SRAM and L1TCM power should be enabled + before booting SCP cores. The size of cache, SRAM, and L1TCM are varied + on differnt SoCs. + + The SCP cores do not use an MMU, but has a set of registers to + control the translations between 32-bit CPU addresses into system bus + addresses. Cache and memory access settings are provided through a + Memory Protection Unit (MPU), programmable only from the SCP. + + properties: + compatible: + enum: + - mediatek,mt8195-scp-core + + reg: + description: The base address and size of SRAM. + maxItems: 1 + + reg-names: + const: sram + + interrupts: + maxItems: 1 + + firmware-name: + $ref: /schemas/types.yaml#/definitions/string + description: + If present, name (or relative path) of the file within the + firmware search path containing the firmware image used when + initializing sub cores of multi-core SCP. + + memory-region: + maxItems: 1 + + cros-ec-rpmsg: + type: object + description: + This subnode represents the rpmsg device. The namesof the devices + are not important. The properties of this node are defined by the + individual bindings for the rpmsg devices. + + properties: + mediatek,rpmsg-name: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Contains the name for the rpmsg device. Used to match + the subnode to rpmsg device announced by SCP. + + required: + - mediatek,rpmsg-name + + required: + - compatible + - reg + - reg-names + + additionalProperties: false + required: - compatible - reg @@ -110,16 +187,26 @@ additionalProperties: false examples: - | - #include - scp@10500000 { - compatible = "mediatek,mt8192-scp"; + compatible = "mediatek,mt8195-scp"; reg = <0x10500000 0x80000>, <0x10700000 0x8000>, <0x10720000 0xe0000>; reg-names = "sram", "cfg", "l1tcm"; - clocks = <&infracfg CLK_INFRA_SCPSYS>; - clock-names = "main"; + + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x105a0000 0x105a0000 0x20000>; + + scp-c1@105a0000 { + compatible = "mediatek,mt8195-scp-core"; + reg = <0x105a0000 0x20000>; + reg-names = "sram"; + + cros-ec-rpmsg { + mediatek,rpmsg-name = "cros-ec-rpmsg"; + }; + }; cros-ec-rpmsg { mediatek,rpmsg-name = "cros-ec-rpmsg"; From patchwork Tue Sep 27 02:55:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 611284 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C3351C07E9D for ; Tue, 27 Sep 2022 02:59:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231134AbiI0C7g (ORCPT ); Mon, 26 Sep 2022 22:59:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44806 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230388AbiI0C7D (ORCPT ); Mon, 26 Sep 2022 22:59:03 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E8C11A6AF2; Mon, 26 Sep 2022 19:56:35 -0700 (PDT) X-UUID: f5614a9d1a2f476caedacbfdd7b2ca91-20220927 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=MGo95QrOIOS0N5UamZ0ehMKwsLyrHKoHLoOELavqTTw=; b=TbY4t/xabIzBMj4XH3Gvx8rtusD+6LosPrIDpfbVTF31A2FmqHLvTDsGjjnYlNwqfnL5uSxGSw7K/07TCmU3pzJ9JYYVmMVRQASKwkz/w0BOAy/xAUNH/o+Htj/pAJarc0BJimpRKr0ZxEhnHqL09i2snyFqEJpULVokn3UxFOg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:1efa0a24-8173-4787-bc3e-da7ae5768999, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.11, REQID:1efa0a24-8173-4787-bc3e-da7ae5768999, IP:0, URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:39a5ff1, CLOUDID:bcbe1c07-1cee-4c38-b21b-a45f9682fdc0, B ulkID:220927105630K59ZMH15,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil, COL:0 X-UUID: f5614a9d1a2f476caedacbfdd7b2ca91-20220927 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 17438933; Tue, 27 Sep 2022 10:56:27 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 27 Sep 2022 10:56:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 27 Sep 2022 10:56:26 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Tiffany Lin , "Andrew-CT Chen" , Yunfei Dong , Mauro Carvalho Chehab , Tinghan Shen CC: , , , , , Subject: [PATCH v3 04/11] remoteproc: mediatek: Remove redundant rproc_boot Date: Tue, 27 Sep 2022 10:55:59 +0800 Message-ID: <20220927025606.26673-5-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220927025606.26673-1-tinghan.shen@mediatek.com> References: <20220927025606.26673-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The video codec doesn't need to explicitly boot SCP in its flow because the SCP remote processor enables auto boot. The redundant usage of rproc_boot increases the number of rproc.power over 1 and prevents successfully shutting down SCP by rproc_shutdown. Signed-off-by: Tinghan Shen --- .../mediatek/vcodec/mtk_vcodec_fw_scp.c | 2 +- drivers/remoteproc/mtk_scp.c | 17 +++++++++++++++++ include/linux/remoteproc/mtk_scp.h | 1 + 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw_scp.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw_scp.c index d8e66b645bd8..c3194f88ff31 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw_scp.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_fw_scp.c @@ -6,7 +6,7 @@ static int mtk_vcodec_scp_load_firmware(struct mtk_vcodec_fw *fw) { - return rproc_boot(scp_get_rproc(fw->scp)); + return scp_boot(fw->scp); } static unsigned int mtk_vcodec_scp_get_vdec_capa(struct mtk_vcodec_fw *fw) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index d421a2ccaa1e..bf68bccab78b 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -673,6 +673,23 @@ struct rproc *scp_get_rproc(struct mtk_scp *scp) } EXPORT_SYMBOL_GPL(scp_get_rproc); +/** + * scp_boot() - Boot SCP + * + * @scp: mtk_scp structure + **/ +int scp_boot(struct mtk_scp *scp) +{ + struct rproc *rproc = scp->rproc; + + /* scp already booted when power > 0 */ + if (atomic_read(&rproc->power) > 0) + return 0; + else + return rproc_boot(scp->rproc); +} +EXPORT_SYMBOL_GPL(scp_boot); + /** * scp_get_vdec_hw_capa() - get video decoder hardware capability * diff --git a/include/linux/remoteproc/mtk_scp.h b/include/linux/remoteproc/mtk_scp.h index 7c2b7cc9fe6c..e463105b351c 100644 --- a/include/linux/remoteproc/mtk_scp.h +++ b/include/linux/remoteproc/mtk_scp.h @@ -52,6 +52,7 @@ void scp_put(struct mtk_scp *scp); struct device *scp_get_device(struct mtk_scp *scp); struct rproc *scp_get_rproc(struct mtk_scp *scp); +int scp_boot(struct mtk_scp *scp); int scp_ipi_register(struct mtk_scp *scp, u32 id, scp_ipi_handler_t handler, void *priv); From patchwork Tue Sep 27 02:56:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 611280 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A32EAC6FA82 for ; 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Tue, 27 Sep 2022 10:56:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 27 Sep 2022 10:56:26 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Tiffany Lin , "Andrew-CT Chen" , Yunfei Dong , Mauro Carvalho Chehab , Tinghan Shen CC: , , , , , Subject: [PATCH v3 05/11] remoteproc: mediatek: Add SCP core 1 register definitions Date: Tue, 27 Sep 2022 10:56:00 +0800 Message-ID: <20220927025606.26673-6-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220927025606.26673-1-tinghan.shen@mediatek.com> References: <20220927025606.26673-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add MT8195 SCP core 1 related register definitions. Signed-off-by: Tinghan Shen Reviewed-by: Mathieu Poirier --- drivers/remoteproc/mtk_common.h | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index ea6fa1100a00..3778894c96f3 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -47,6 +47,7 @@ #define MT8192_SCP2SPM_IPC_CLR 0x4094 #define MT8192_GIPC_IN_SET 0x4098 #define MT8192_HOST_IPC_INT_BIT BIT(0) +#define MT8195_CORE1_HOST_IPC_INT_BIT BIT(4) #define MT8192_CORE0_SW_RSTN_CLR 0x10000 #define MT8192_CORE0_SW_RSTN_SET 0x10004 @@ -56,6 +57,26 @@ #define MT8195_L1TCM_SRAM_PDN_RESERVED_RSI_BITS GENMASK(7, 4) +#define MT8195_CPU1_SRAM_PD 0x1084 +#define MT8195_SSHUB2APMCU_IPC_SET 0x4088 +#define MT8195_SSHUB2APMCU_IPC_CLR 0x408C +#define MT8195_CORE1_SW_RSTN_CLR 0x20000 +#define MT8195_CORE1_SW_RSTN_SET 0x20004 +#define MT8195_CORE1_MEM_ATT_PREDEF 0x20008 +#define MT8195_CORE1_WDT_IRQ 0x20030 +#define MT8195_CORE1_WDT_CFG 0x20034 + +#define MT8195_SEC_CTRL 0x85000 +#define MT8195_CORE_OFFSET_ENABLE_D BIT(13) +#define MT8195_CORE_OFFSET_ENABLE_I BIT(12) +#define MT8195_L2TCM_OFFSET_RANGE_0_LOW 0x850b0 +#define MT8195_L2TCM_OFFSET_RANGE_0_HIGH 0x850b4 +#define MT8195_L2TCM_OFFSET 0x850d0 +#define SCP_SRAM_REMAP_LOW 0 +#define SCP_SRAM_REMAP_HIGH 1 +#define SCP_SRAM_REMAP_OFFSET 2 +#define SCP_SRAM_REMAP_SIZE 3 + #define SCP_FW_VER_LEN 32 #define SCP_SHARE_BUFFER_SIZE 288 From patchwork Tue Sep 27 02:56:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 611282 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0A50C6FA82 for ; Tue, 27 Sep 2022 02:59:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230383AbiI0C7p (ORCPT ); Mon, 26 Sep 2022 22:59:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230413AbiI0C7F (ORCPT ); Mon, 26 Sep 2022 22:59:05 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21E4AA6C15; Mon, 26 Sep 2022 19:56:36 -0700 (PDT) X-UUID: 29d83e59ea664283a347971b169064d9-20220927 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=GIDRoFehAj0CvgGt9nUIzx7Elay9M3yCmpkbTwT5lhM=; b=cQtnBb0pU9pLmmyFZ+wP0SFgX3v/6z26RLDKR5EvcUBHr9B2CRlCNhOrEvHWjxD4h41FA7sZGMX0mo82/iZy6kXXG/IjSMX84Xk04r7gjAjpKyzzYU4vM84YbmSR/JEjRxua0lwowGwTwMGyFnEI12joDo1nFozxAGIUeBxF7ZU=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:e9906db0-4c71-49f7-88dc-8c8d6134a0e0, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:95 X-CID-INFO: VERSION:1.1.11, REQID:e9906db0-4c71-49f7-88dc-8c8d6134a0e0, IP:0, URL :0,TC:0,Content:0,EDM:0,RT:0,SF:95,FILE:0,BULK:0,RULE:Spam_GS981B3D,ACTION :quarantine,TS:95 X-CID-META: VersionHash:39a5ff1, CLOUDID:c22b51e4-87f9-4bb0-97b6-34957dc0fbbe, B ulkID:220927105630AZZ5CK2K,BulkQuantity:0,Recheck:0,SF:38|28|17|19|48|823| 824,TC:nil,Content:0,EDM:-3,IP:nil,URL:0,File:nil,Bulk:nil,QS:nil,BEC:nil, COL:0 X-UUID: 29d83e59ea664283a347971b169064d9-20220927 Received: from mtkcas11.mediatek.inc [(172.21.101.40)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 598700382; Tue, 27 Sep 2022 10:56:27 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Tue, 27 Sep 2022 10:56:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 27 Sep 2022 10:56:26 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Tiffany Lin , "Andrew-CT Chen" , Yunfei Dong , Mauro Carvalho Chehab , Tinghan Shen CC: , , , , , Subject: [PATCH v3 06/11] remoteproc: mediatek: Add MT8195 SCP core 1 operations Date: Tue, 27 Sep 2022 10:56:01 +0800 Message-ID: <20220927025606.26673-7-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220927025606.26673-1-tinghan.shen@mediatek.com> References: <20220927025606.26673-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The SCP rproc driver has a set of chip dependent callbacks for boot sequence and IRQ handling. Implement these callbacks for MT8195 SCP core 1. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_scp.c | 57 ++++++++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index bf68bccab78b..1d17d77b8a14 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -176,6 +176,16 @@ static void mt8192_scp_reset_deassert(struct mtk_scp *scp) writel(1, scp->reg_base + MT8192_CORE0_SW_RSTN_CLR); } +static void mt8195_scp_c1_reset_assert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_SET); +} + +static void mt8195_scp_c1_reset_deassert(struct mtk_scp *scp) +{ + writel(1, scp->reg_base + MT8195_CORE1_SW_RSTN_CLR); +} + static void mt8183_scp_irq_handler(struct mtk_scp *scp) { u32 scp_to_host; @@ -212,6 +222,18 @@ static void mt8192_scp_irq_handler(struct mtk_scp *scp) } } +static void mt8195_scp_c1_irq_handler(struct mtk_scp *scp) +{ + u32 scp_to_host; + + scp_to_host = readl(scp->reg_base + MT8195_SSHUB2APMCU_IPC_SET); + + if (scp_to_host & MT8192_SCP_IPC_INT_BIT) + scp_ipi_handler(scp); + + writel(scp_to_host, scp->reg_base + MT8195_SSHUB2APMCU_IPC_CLR); +} + static irqreturn_t scp_irq_handler(int irq, void *priv) { struct mtk_scp *scp = priv; @@ -453,6 +475,19 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) return 0; } +static int mt8195_scp_c1_before_load(struct mtk_scp *scp) +{ + scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* hold SCP in reset while loading FW. */ + scp->data->scp_reset_assert(scp); + + /* enable MPU for all memory regions */ + writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + + return 0; +} + static int scp_load(struct rproc *rproc, const struct firmware *fw) { struct mtk_scp *scp = rproc->priv; @@ -625,6 +660,15 @@ static void mt8195_scp_stop(struct mtk_scp *scp) writel(0, scp->reg_base + MT8192_CORE0_WDT_CFG); } +static void mt8195_scp_c1_stop(struct mtk_scp *scp) +{ + /* Power off CPU SRAM */ + scp_sram_power_off(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); + + /* Disable SCP watchdog */ + writel(0, scp->reg_base + MT8195_CORE1_WDT_CFG); +} + static int scp_stop(struct rproc *rproc) { struct mtk_scp *scp = (struct mtk_scp *)rproc->priv; @@ -1007,12 +1051,25 @@ static const struct mtk_scp_of_data mt8195_of_data = { .host_to_scp_int_bit = MT8192_HOST_IPC_INT_BIT, }; +static const struct mtk_scp_of_data mt8195_core_of_data = { + .scp_clk_get = mt8195_scp_clk_get, + .scp_before_load = mt8195_scp_c1_before_load, + .scp_irq_handler = mt8195_scp_c1_irq_handler, + .scp_reset_assert = mt8195_scp_c1_reset_assert, + .scp_reset_deassert = mt8195_scp_c1_reset_deassert, + .scp_stop = mt8195_scp_c1_stop, + .scp_da_to_va = mt8192_scp_da_to_va, + .host_to_scp_reg = MT8192_GIPC_IN_SET, + .host_to_scp_int_bit = MT8195_CORE1_HOST_IPC_INT_BIT, +}; + static const struct of_device_id mtk_scp_of_match[] = { { .compatible = "mediatek,mt8183-scp", .data = &mt8183_of_data }, { .compatible = "mediatek,mt8186-scp", .data = &mt8186_of_data }, { .compatible = "mediatek,mt8188-scp", .data = &mt8188_of_data }, { .compatible = "mediatek,mt8192-scp", .data = &mt8192_of_data }, { .compatible = "mediatek,mt8195-scp", .data = &mt8195_of_data }, + { .compatible = "mediatek,mt8195-scp-core", .data = &mt8195_core_of_data }, {}, }; MODULE_DEVICE_TABLE(of, mtk_scp_of_match); From patchwork Tue Sep 27 02:56:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 611281 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 450B5C6FA90 for ; Tue, 27 Sep 2022 02:59:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230493AbiI0C7t (ORCPT ); Mon, 26 Sep 2022 22:59:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44944 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230454AbiI0C7F (ORCPT ); Mon, 26 Sep 2022 22:59:05 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABE95A6C31; Mon, 26 Sep 2022 19:56:38 -0700 (PDT) X-UUID: 7beb1adeac91421b9d5875bd5dce1d9c-20220927 DKIM-Signature: v=1; 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Tue, 27 Sep 2022 10:56:27 +0800 Received: from mtkmbs11n2.mediatek.inc (172.21.101.187) by mtkmbs11n1.mediatek.inc (172.21.101.185) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Tue, 27 Sep 2022 10:56:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 27 Sep 2022 10:56:26 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , Krzysztof Kozlowski , Matthias Brugger , Tiffany Lin , Andrew-CT Chen , Yunfei Dong , Mauro Carvalho Chehab , Tinghan Shen CC: , , , , , Subject: [PATCH v3 07/11] remoteproc: mediatek: Probe MT8195 SCP core 1 Date: Tue, 27 Sep 2022 10:56:02 +0800 Message-ID: <20220927025606.26673-8-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220927025606.26673-1-tinghan.shen@mediatek.com> References: <20220927025606.26673-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The MT8195 SCP configuration registers for core 0 and core 1 is the same. Let SCP core 1 to reuse the mapped address requested by SCP core 0. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_common.h | 2 ++ drivers/remoteproc/mtk_scp.c | 27 +++++++++++++++++++++++---- 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/remoteproc/mtk_common.h b/drivers/remoteproc/mtk_common.h index 3778894c96f3..54265c515315 100644 --- a/drivers/remoteproc/mtk_common.h +++ b/drivers/remoteproc/mtk_common.h @@ -140,6 +140,8 @@ struct mtk_scp { size_t dram_size; struct rproc_subdev *rpmsg_subdev; + + struct mtk_scp *main_scp; }; /** diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 1d17d77b8a14..f7b738743ba9 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -917,10 +917,29 @@ static int scp_probe(struct platform_device *pdev) scp->l1tcm_phys = res->start; } - scp->reg_base = devm_platform_ioremap_resource_byname(pdev, "cfg"); - if (IS_ERR(scp->reg_base)) - return dev_err_probe(dev, PTR_ERR(scp->reg_base), - "Failed to parse and map cfg memory\n"); + if (of_device_is_compatible(np, "mediatek,mt8195-scp-core")) { + struct device_node *pnp; + struct platform_device *scp_pdev; + + pnp = of_get_parent(np); + if (!pnp) + return dev_err_probe(dev, -ENODEV, "Failed to get parent core 0\n"); + + scp_pdev = of_find_device_by_node(pnp); + of_node_put(pnp); + if (!scp_pdev) + return dev_err_probe(dev, -ENODEV, "Failed to get scp core 0 pdev\n"); + + scp->main_scp = platform_get_drvdata(scp_pdev); + scp->reg_base = scp->main_scp->reg_base; + } else { + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg"); + scp->reg_base = devm_ioremap_resource(dev, res); + + if (IS_ERR(scp->reg_base)) + return dev_err_probe(dev, PTR_ERR(scp->reg_base), + "Failed to parse and map cfg memory\n"); + } ret = scp->data->scp_clk_get(scp); if (ret) From patchwork Tue Sep 27 02:56:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tinghan Shen X-Patchwork-Id: 611285 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82BD2C6FA96 for ; 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Tue, 27 Sep 2022 10:56:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n2.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Tue, 27 Sep 2022 10:56:26 +0800 From: Tinghan Shen To: Bjorn Andersson , Mathieu Poirier , Rob Herring , "Krzysztof Kozlowski" , Matthias Brugger , Tiffany Lin , "Andrew-CT Chen" , Yunfei Dong , Mauro Carvalho Chehab , Tinghan Shen CC: , , , , , Subject: [PATCH v3 09/11] remoteproc: mediatek: Setup MT8195 SCP core 1 SRAM offset Date: Tue, 27 Sep 2022 10:56:04 +0800 Message-ID: <20220927025606.26673-10-tinghan.shen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220927025606.26673-1-tinghan.shen@mediatek.com> References: <20220927025606.26673-1-tinghan.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Because MT8195 SCP core 0 and core 1 both boot from head of SRAM and have the same viewpoint of SRAM, SCP has a "Core 1 SRAM offset" to control the viewpoint of SCP core 1 to allow core 1 boot from different SRAM location. The "Core 1 SRAM offset" configuration is composed by specifying a range and an offset. When SCP core 1 accesses a SRAM address located in the configured range, SCP bus adds the configured offset to the address to shift the final physical destination on SCP SRAM. This shift is transparent to the software running on SCP core 1. Signed-off-by: Tinghan Shen --- drivers/remoteproc/mtk_scp.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/remoteproc/mtk_scp.c b/drivers/remoteproc/mtk_scp.c index 2d43338b96da..0f1b587f8502 100644 --- a/drivers/remoteproc/mtk_scp.c +++ b/drivers/remoteproc/mtk_scp.c @@ -477,6 +477,8 @@ static int mt8195_scp_before_load(struct mtk_scp *scp) static int mt8195_scp_c1_before_load(struct mtk_scp *scp) { + u32 sec_ctrl; + scp_sram_power_on(scp->reg_base + MT8195_CPU1_SRAM_PD, 0); /* hold SCP in reset while loading FW. */ @@ -485,6 +487,27 @@ static int mt8195_scp_c1_before_load(struct mtk_scp *scp) /* enable MPU for all memory regions */ writel(0xff, scp->reg_base + MT8195_CORE1_MEM_ATT_PREDEF); + /* The value of SRAM offset range is from the viewpoint of SCP core 1. + * This configuration adds an offset on SCP bus when SCP core 1 accesses SCP SRAM + * to solve the SCP core 0 and core 1 both fetch the 1st instruction from the same + * SRAM address. + * + * Because SCP core 0 and core 1 both boot from the head of sram, this must be + * configured before boot SCP core 1. + * + * Configure the range of SRAM addresses will be added offset. + */ + writel(0, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_LOW); + writel(scp->sram_size, scp->reg_base + MT8195_L2TCM_OFFSET_RANGE_0_HIGH); + + /* configure the offset value */ + writel(scp->sram_phys - scp->main_scp->sram_phys, scp->reg_base + MT8195_L2TCM_OFFSET); + + /* enable adding sram offset when fetching instruction and data */ + sec_ctrl = readl(scp->reg_base + MT8195_SEC_CTRL); + sec_ctrl |= MT8195_CORE_OFFSET_ENABLE_I | MT8195_CORE_OFFSET_ENABLE_D; + writel(sec_ctrl, scp->reg_base + MT8195_SEC_CTRL); + return 0; }