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[2001:1868:205::9]) by mx.google.com with ESMTPS id m22si16071325pfg.0.2016.08.25.08.41.07 for (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 25 Aug 2016 08:41:08 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) client-ip=2001:1868:205::9; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org designates 2001:1868:205::9 as permitted sender) smtp.mailfrom=linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.85_2 #1 (Red Hat Linux)) id 1bcwl7-0007tM-Ct; Thu, 25 Aug 2016 15:40:01 +0000 Received: from mout.kundenserver.de ([212.227.126.187]) by bombadil.infradead.org with esmtps (Exim 4.85_2 #1 (Red Hat Linux)) id 1bcwl2-0007qk-AS for linux-arm-kernel@lists.infradead.org; Thu, 25 Aug 2016 15:39:58 +0000 Received: from wuerfel.localnet ([78.42.132.4]) by mrelayeu.kundenserver.de (mreue005) with ESMTPSA (Nemesis) id 0MWOFC-1beh3C3Wji-00XaqT; Thu, 25 Aug 2016 17:39:04 +0200 From: Arnd Bergmann To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v2 1/2] smc91x: always use 8-bit access if necessary Date: Thu, 25 Aug 2016 17:39:00 +0200 Message-ID: <3107598.uul2xx8LJA@wuerfel> User-Agent: KMail/5.1.3 (Linux/4.4.0-31-generic; KDE/5.18.0; x86_64; ; ) In-Reply-To: <20160825144633.1850889-1-arnd@arndb.de> References: <20160825144633.1850889-1-arnd@arndb.de> MIME-Version: 1.0 X-Provags-ID: V03:K0:2AiXhKLRyI3jNJpVStG85giYhN6L9gVqFWsmNqxnXLMZY1Ctg9C rxz1kawm4JrpqfUBYGM3dUvD120Mnm2E3Q2w85cByIjzBTVnr2tdTH88tJ2PyUPIefNoCV4 uUG83FpCoq636oHX3Kyelyzb5ZP0fnZJrMfcBz/5r03OKaP2ceIwo2FwqruDNYC3EGq0BvL SjS9byLbbM5aCDWN3D7cw== X-UI-Out-Filterresults: notjunk:1; V01:K0:2paTBLhu8s0=:LwTKySXnw670geYf2jTg9R rRDm8SH2Ik5laAk658wH4xgeiKiypgHb2Rb7qsWWTY5/JqnL0MyY+nwMyXBzhJBWIMVrRWZTS Tm2vEjE6IItZCPwsvSy+2SyaRxuchg89Esb/68xLv99J7yNrHzMlaLd3JiLUAAZpwv1Va7Y7/ k6XAyrUJgziMMy9wsFee4fuTixatONkN7yyx7slGe1DDTYPyMyFzHmLYxbAD/VJTR/rfwcmTc zWRWqUjjC3W1NpDsd/fqgiqjVcAxZwND+r8RviOGgjqeZcmuL/tkpydec8d7sKaO7TuR8nrNL pBotR2Y1uMm0w5787RrJGo9GlsknMHkiRxqjZBZ/87eeWhNqwTUsB3FhMZLsXqukGxHNIi12O M2wAnxLjmkALkOLwae874JjUgSivxsPjpwDApeM9jMUSTcvuVnCQS4NVNOMIFknqiHM97KAFz m5ZKhTc4LtoygRWTxUVSpKXCPG+1XHbUm/hAJvzQ0BeImPBCk3vNFehWdAop81yn6Ply0QRw2 S3086BwmUzXMfHbGN6Q0bmWb+I47NjwKTklLpjEAjl17jIr8P+0mGyGwuuUFXpwbsLh0uvsE9 0JQXgx2pLCuR+xDtknNOpHArAAgOZc7pwxoCfGV+OEdhgPkIN022Z5y0mH2dt9uqjQSHtMmj7 P7ZSrOKBSAUP+f9OE/xo5HW3cnJsIcTHBd7c996tPrg5Bt9lS+Ktin9dNrEFyT+Rak13X8odU hc14OZywVyJVMmDR X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20160825_083956_883139_24EDA5E5 X-CRM114-Status: GOOD ( 18.20 ) X-Spam-Score: -1.9 (-) X-Spam-Report: SpamAssassin version 3.4.0 on bombadil.infradead.org summary: Content analysis details: (-1.9 points) pts rule name description ---- ---------------------- -------------------------------------------------- -0.0 RCVD_IN_DNSWL_NONE RBL: Sender listed at http://www.dnswl.org/, no trust [212.227.126.187 listed in list.dnswl.org] -0.0 RCVD_IN_MSPIKE_H2 RBL: Average reputation (+2) [212.227.126.187 listed in wl.mailspike.net] -1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1% [score: 0.0000] X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Nicolas Pitre , netdev@vger.kernel.org, linux-kernel@vger.kernel.org, Russell King , Robert Jarzmik , "David S. Miller" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+patch=linaro.org@lists.infradead.org As Russell King found out the hard way, a change I did to fix multiplatform builds with this driver broke the old Assabet/Neponset platform: It turns out that while the driver is runtime configurable in principle, the runtime configuration does not cover the specific case of machines that can not do any 16-bit I/O on the smc91x registers. The driver currently provides helpers to access 16-bit registers for architectures that are known at compile-time to only have 8-bit I/O, but my patch changed it to a runtime flag that never gets consulted most register accesses. This introduces new SMC_out16()/SMC_in16 helpers (if anyone can suggest a better name, I'm glad to modify this) that behaves like SMC_outw()/SMC_inw() most of the time, but uses a pair of 8-bit accesses on platforms that have no support for wider register accesses. Signed-off-by: Arnd Bergmann Reported-by: Russell King Fixes: b70661c70830d ("net: smc91x: use run-time configuration on all ARM machines") --- Having bad luck streak with this patch, the version I sent had a couple of mistakes from the last rebase before sending it out, this version should actually apply and build. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel diff --git a/drivers/net/ethernet/smsc/smc91x.h b/drivers/net/ethernet/smsc/smc91x.h index 1a55c7976df0..497411ed6de2 100644 --- a/drivers/net/ethernet/smsc/smc91x.h +++ b/drivers/net/ethernet/smsc/smc91x.h @@ -414,30 +414,32 @@ smc_pxa_dma_insw(void __iomem *ioaddr, struct smc_local *lp, int reg, int dma, #define SMC_outsl(a, r, p, l) BUG() #endif -#if ! SMC_CAN_USE_16BIT - /* - * Any 16-bit access is performed with two 8-bit accesses if the hardware - * can't do it directly. Most registers are 16-bit so those are mandatory. + * Any 16-bit register access is performed with two 8-bit accesses if the + * hardware can't do it directly. */ -#define SMC_outw(x, ioaddr, reg) \ - do { \ - unsigned int __val16 = (x); \ - SMC_outb( __val16, ioaddr, reg ); \ - SMC_outb( __val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT));\ - } while (0) -#define SMC_inw(ioaddr, reg) \ - ({ \ - unsigned int __val16; \ - __val16 = SMC_inb( ioaddr, reg ); \ +#define SMC_out16(x, ioaddr, reg) \ +do { \ + if (SMC_CAN_USE_8BIT && !SMC_16BIT(lp)) { \ + unsigned int __val16 = (x); \ + SMC_outb(__val16, ioaddr, reg ); \ + SMC_outb(__val16 >> 8, ioaddr, reg + (1 << SMC_IO_SHIFT)); \ + } else { \ + SMC_outw(x, ioaddr, reg); \ + } \ +} while (0) + +#define SMC_in16(ioaddr, reg) \ +({ \ + unsigned int __val16; \ + if (SMC_CAN_USE_8BIT && !SMC_16BIT(lp)) { \ + __val16 = SMC_inb( ioaddr, reg ); \ __val16 |= SMC_inb( ioaddr, reg + (1 << SMC_IO_SHIFT)) << 8; \ - __val16; \ - }) - -#define SMC_insw(a, r, p, l) BUG() -#define SMC_outsw(a, r, p, l) BUG() - -#endif + } else { \ + __val16 = SMC_inw(ioaddr, reg); \ + } \ + __val16; \ +}) #if !defined(SMC_insw) || !defined(SMC_outsw) #define SMC_insw(a, r, p, l) BUG() @@ -927,113 +929,113 @@ static const char * chip_ids[ 16 ] = { SMC_outw((x) << 8, ioaddr, INT_REG(lp)); \ } while (0) -#define SMC_CURRENT_BANK(lp) SMC_inw(ioaddr, BANK_SELECT) +#define SMC_CURRENT_BANK(lp) SMC_in16(ioaddr, BANK_SELECT) #define SMC_SELECT_BANK(lp, x) \ do { \ if (SMC_MUST_ALIGN_WRITE(lp)) \ SMC_outl((x)<<16, ioaddr, 12<> 8; \ - __v = SMC_inw(ioaddr, ADDR1_REG(lp)); \ + __v = SMC_in16(ioaddr, ADDR1_REG(lp)); \ addr[2] = __v; addr[3] = __v >> 8; \ - __v = SMC_inw(ioaddr, ADDR2_REG(lp)); \ + __v = SMC_in16(ioaddr, ADDR2_REG(lp)); \ addr[4] = __v; addr[5] = __v >> 8; \ } while (0) #endif #define SMC_SET_MAC_ADDR(lp, addr) \ do { \ - SMC_outw(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ - SMC_outw(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ - SMC_outw(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ + SMC_out16(addr[0]|(addr[1] << 8), ioaddr, ADDR0_REG(lp)); \ + SMC_out16(addr[2]|(addr[3] << 8), ioaddr, ADDR1_REG(lp)); \ + SMC_out16(addr[4]|(addr[5] << 8), ioaddr, ADDR2_REG(lp)); \ } while (0) #define SMC_SET_MCAST(lp, x) \ do { \ const unsigned char *mt = (x); \ - SMC_outw(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ - SMC_outw(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ - SMC_outw(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ - SMC_outw(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ + SMC_out16(mt[0] | (mt[1] << 8), ioaddr, MCAST_REG1(lp)); \ + SMC_out16(mt[2] | (mt[3] << 8), ioaddr, MCAST_REG2(lp)); \ + SMC_out16(mt[4] | (mt[5] << 8), ioaddr, MCAST_REG3(lp)); \ + SMC_out16(mt[6] | (mt[7] << 8), ioaddr, MCAST_REG4(lp)); \ } while (0) #define SMC_PUT_PKT_HDR(lp, status, length) \ @@ -1042,8 +1044,8 @@ static const char * chip_ids[ 16 ] = { SMC_outl((status) | (length)<<16, ioaddr, \ DATA_REG(lp)); \ else { \ - SMC_outw(status, ioaddr, DATA_REG(lp)); \ - SMC_outw(length, ioaddr, DATA_REG(lp)); \ + SMC_out16(status, ioaddr, DATA_REG(lp)); \ + SMC_out16(length, ioaddr, DATA_REG(lp)); \ } \ } while (0) @@ -1054,8 +1056,8 @@ static const char * chip_ids[ 16 ] = { (status) = __val & 0xffff; \ (length) = __val >> 16; \ } else { \ - (status) = SMC_inw(ioaddr, DATA_REG(lp)); \ - (length) = SMC_inw(ioaddr, DATA_REG(lp)); \ + (status) = SMC_in16(ioaddr, DATA_REG(lp)); \ + (length) = SMC_in16(ioaddr, DATA_REG(lp)); \ } \ } while (0)