From patchwork Thu Feb 21 11:42:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dave Martin X-Patchwork-Id: 158908 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp384462jaa; Thu, 21 Feb 2019 03:42:40 -0800 (PST) X-Google-Smtp-Source: AHgI3IaavoVwj2J18Ua1OUHX4CbJyqwbTwvO8Gf/9ewCQxL+9y/riFwuzJa0R6XBBYphHGOVtG8h X-Received: by 2002:a63:d70a:: with SMTP id d10mr33789633pgg.286.1550749360875; Thu, 21 Feb 2019 03:42:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550749360; cv=none; d=google.com; s=arc-20160816; b=UXtwrd+4a2djBOqIsTaO6D+Mn2ChR+0UauUBguh1FA7NAiMRTnaZ0sdtlLiS408cqK 5EuHJ5lOdm657KLfvkdzF6Ta7s1WYGyFTSJR3HfZegKgMV/6brRcGkDIaDbiq6+ZvAxx ZTak7Dd/zfebhbySnqeGa4S7/vFJlZN7A8N52a1E71MnhwY7RkB7nP7we1pubIhEjRkx ksFmcPPRW87Cnj7dkR1deCDsLik+vMfwifBSKu8ggfAHQDGyDuJkwXfv1o6jvJkrr+dH 2RRf1mnGYId5Eu7RE+2RfO+HtTYljxKslIq8CvnOAtLAZW1N4N3Nxfv0RYcbDZbOHvqE eATA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=PBHM3Msq2HeliChkMarJKNt7818NnqAiSlgDT9fEnug=; b=kYkAeXucZcRrImOfLCxHJAAT4j8PBiiWkSD9sXgcsm9Idzb/opzj6ZKSZPS92jxcz1 oSrzfX7IVPYT1rWr9M1zAje3TtJVjFVfnr4+t5Oexc6mIi6IuAuHsS+0BJoqkKJ8kFaP PTsuaR4xFNZj7MuZ9+crgT1na48GXqj1mQi9nqKHyv8u7ffOt/NVsAKcC/qN7gs9XNEn wlWmk68OQPm9WUzxgPaEgHrvlBUP8yerINNRVcGI+AVOHcegaaxICbzihNR5DIBd3hq6 16B/ojhnHlQ/pAmJRuW/Em3xI3EUf0APe8V6QQ/dk8NEXeQC6HPa0eXC5eL+2MzCXUQa ovxg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e2si20107943pgn.71.2019.02.21.03.42.40; Thu, 21 Feb 2019 03:42:40 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of stable-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=stable-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727505AbfBULmj (ORCPT + 15 others); Thu, 21 Feb 2019 06:42:39 -0500 Received: from foss.arm.com ([217.140.101.70]:42558 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726525AbfBULmi (ORCPT ); Thu, 21 Feb 2019 06:42:38 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4CCA680D; Thu, 21 Feb 2019 03:42:38 -0800 (PST) Received: from e103592.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.72.51.249]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id A5B4F3F5C1; Thu, 21 Feb 2019 03:42:36 -0800 (PST) From: Dave Martin To: kvmarm@lists.cs.columbia.edu Cc: linux-arm-kernel@lists.infradead.org, Julien Thierry , James Morse , Suzuki K Poulose , , Marc Zyngier , Christoffer Dall Subject: [PATCH] KVM: arm64: Fix architecturally invalid reset value for FPEXC32_EL2 Date: Thu, 21 Feb 2019 11:42:32 +0000 Message-Id: <1550749352-2315-1-git-send-email-Dave.Martin@arm.com> X-Mailer: git-send-email 2.1.4 Sender: stable-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: stable@vger.kernel.org Due to what looks like a typo dating back to the original addition of FPEXC32_EL2 handling, KVM currently initialises this register to an architecturally invalid value. As a result, the VECITR field (RES1) in bits [10:8] is initialised with 0, and the two reserved (RES0) bits [6:5] are initialised with 1. (In the Common VFP Subarchitecture as specified by ARMv7-A, these two bits were IMP DEF. ARMv8-A removes them.) This patch changes the reset value from 0x70 to 0x700, which reflects the architectural constraints and is presumably what was originally intended. Cc: # 4.12.x- Cc: Marc Zyngier Cc: Christoffer Dall Fixes: 62a89c44954f ("arm64: KVM: 32bit handling of coprocessor traps") Signed-off-by: Dave Martin --- For AArch32 the situation is more complicated. FPEXC[29:0] is subarchitecture-defined, so the reset value may need to be per-CPU- implementation. The machinery for this is incomplete today In fact, I haven't currently found any reset logic for the VFP registers in arch/arm/kvm. Currently I don't attempt to address this, but if anyone has ideas about the best way to address it, please shout. I'll try to figure out something in the meantime, but it's not my top priority. We have no evidence I'm aware of that this is causing problems for anybody today. --- arch/arm64/kvm/sys_regs.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.1.4 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index c936aa4..b6dac3a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1476,7 +1476,7 @@ static const struct sys_reg_desc sys_reg_descs[] = { { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 }, { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 }, - { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x70 }, + { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 }, }; static bool trap_dbgidr(struct kvm_vcpu *vcpu,