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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2022 09:49:25.6690 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5a964afb-f445-40a7-14b1-08da9fa465dc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT073.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR12MB4403 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Create new SoC data structure for Tegra234 platforms. Additional features, tap value configurations are added/ updated for Tegra234 platform hence separate Tegra194 and Tegra234 SoC data. Signed-off-by: Aniruddha Tvs Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2d2d8260c681..a6c5bbae77b4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1556,7 +1556,21 @@ static const struct sdhci_tegra_soc_data soc_data_tegra194 = { .max_tap_delay = 139, }; +static const struct sdhci_tegra_soc_data soc_data_tegra234 = { + .pdata = &sdhci_tegra186_pdata, + .dma_mask = DMA_BIT_MASK(39), + .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | + NVQUIRK_ENABLE_SDR50 | + NVQUIRK_ENABLE_SDR104 | + NVQUIRK_HAS_TMCLK, + .min_tap_delay = 95, + .max_tap_delay = 111, +}; + static const struct of_device_id sdhci_tegra_dt_match[] = { + { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 }, { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, From patchwork Mon Sep 26 09:49:04 2022 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2022 09:49:40.4717 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 514d7b8c-f899-4932-cda7-08da9fa46eae X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT101.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BY5PR12MB4100 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org SMMU clients are supposed to program stream ID from their respective address spaces instead of MC override. Define NVQUIRK_PROGRAM_STREAMID and use it to program SMMU stream ID from the SDMMC client address space. Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete --- drivers/mmc/host/sdhci-tegra.c | 35 ++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a6c5bbae77b4..4d32b5bfc424 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -25,6 +25,7 @@ #include #include #include +#ifdef CONFIG_IOMMU_API +#include +#endif #include @@ -94,6 +95,8 @@ #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) +#define SDHCI_TEGRA_CIF2AXI_CTRL_0 0x1fc + #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) @@ -121,6 +124,7 @@ #define NVQUIRK_HAS_TMCLK BIT(10) #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) +#define NVQUIRK_PROGRAM_STREAMID BIT(12) /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 @@ -128,6 +132,8 @@ #define SDHCI_TEGRA_CQE_TRNS_MODE (SDHCI_TRNS_MULTI | \ SDHCI_TRNS_BLK_CNT_EN | \ SDHCI_TRNS_DMA) +#define SDHCI_TEGRA_STREAMID_MASK 0xff +#define SDHCI_TEGRA_WRITE_STREAMID_SHIFT 0x8 struct sdhci_tegra_soc_data { const struct sdhci_pltfm_data *pdata; @@ -177,6 +183,7 @@ struct sdhci_tegra { bool enable_hwcq; unsigned long curr_clk_rate; u8 tuned_tap_delay; +#ifdef CONFIG_IOMMU_API + u32 streamid; +#endif }; static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) @@ -1564,6 +1571,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = { NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | NVQUIRK_ENABLE_SDR50 | NVQUIRK_ENABLE_SDR104 | + NVQUIRK_PROGRAM_STREAMID | NVQUIRK_HAS_TMCLK, .min_tap_delay = 95, .max_tap_delay = 111, @@ -1636,6 +1644,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev) struct sdhci_host *host; struct sdhci_pltfm_host *pltfm_host; struct sdhci_tegra *tegra_host; +#ifdef CONFIG_IOMMU_API + struct iommu_fwspec *fwspec; +#endif struct clk *clk; int rc; @@ -1775,6 +1784,23 @@ static int sdhci_tegra_probe(struct platform_device *pdev) if (rc) goto err_add_host; + /* Program MC streamID for DMA transfers */ +#ifdef CONFIG_IOMMU_API + if (soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) { + fwspec = dev_iommu_fwspec_get(&pdev->dev); + if (fwspec == NULL) { + dev_warn(mmc_dev(host->mmc), + "iommu fwspec is NULL, continue without stream ID\n"); + } else { + tegra_host->streamid = fwspec->ids[0] & 0xffff; + tegra_sdhci_writel(host, (tegra_host->streamid & + SDHCI_TEGRA_STREAMID_MASK) | + ((tegra_host->streamid << + SDHCI_TEGRA_WRITE_STREAMID_SHIFT) + & SDHCI_TEGRA_STREAMID_MASK), + SDHCI_TEGRA_CIF2AXI_CTRL_0); + } + } +#endif + return 0; err_add_host: @@ -1861,6 +1887,8 @@ static int sdhci_tegra_suspend(struct device *dev) static int sdhci_tegra_resume(struct device *dev) { struct sdhci_host *host = dev_get_drvdata(dev); +#ifdef CONFIG_IOMMU_API + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); +#endif int ret; ret = mmc_gpio_set_cd_wake(host->mmc, false); @@ -1871,6 +1899,13 @@ static int sdhci_tegra_resume(struct device *dev) if (ret) return ret; + /* Re-program MC streamID for DMA transfers */ +#ifdef CONFIG_IOMMU_API + if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_STREAMID) { + tegra_sdhci_writel(host, tegra_host->streamid | + (tegra_host->streamid << 8), + SDHCI_TEGRA_CIF2AXI_CTRL_0); + } +#endif + ret = sdhci_resume_host(host); if (ret) goto disable_clk; From patchwork Mon Sep 26 09:49:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 609531 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B58BBC6FA86 for ; Mon, 26 Sep 2022 09:49:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234005AbiIZJtx (ORCPT ); Mon, 26 Sep 2022 05:49:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60430 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233691AbiIZJtq (ORCPT ); Mon, 26 Sep 2022 05:49:46 -0400 Received: from NAM12-BN8-obe.outbound.protection.outlook.com (mail-bn8nam12on2067.outbound.protection.outlook.com [40.107.237.67]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CD7FFE093; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2022 09:49:42.8003 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 24345cda-cf8a-4762-f757-08da9fa4700a X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT052.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5316 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org In case of error condition to avoid system crash Tegra SDMMC controller requires CMD and DAT resets issued together. SDHCI controller FSM goes into bad state due to rapid SD card hot-plug event. Issuing reset on the CMD FSM before DATA FSM results in kernel panic, hence add support to issue CMD and DAT resets together. This is applicable to Tegra186 and later chips. Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete --- drivers/mmc/host/sdhci-tegra.c | 3 ++- drivers/mmc/host/sdhci.c | 20 +++++++++++++++----- drivers/mmc/host/sdhci.h | 2 ++ 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 4d32b5bfc424..58449e010a9b 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1532,7 +1532,8 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER, .ops = &tegra186_sdhci_ops, }; diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 7689ffec5ad1..2f4a0e84fee8 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3060,12 +3060,22 @@ static bool sdhci_request_done(struct sdhci_host *host) host->ops->set_clock(host, host->clock); /* - * Spec says we should do both at the same time, but Ricoh - * controllers do not like that. + * While the specification says we should do both at the + * same time, Ricoh controllers (and potentially others) do not + * like that. On the other hand, some controllers (such as those + * found on Tegra186 and later) rely on both being reset at the + * same time. Use a quirk for the latter category since most + * controllers seem to work fine with DAT and CMD getting reset + * at the same time. */ - sdhci_do_reset(host, SDHCI_RESET_CMD); - sdhci_do_reset(host, SDHCI_RESET_DATA); - + if (host->quirks2 & + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) { + sdhci_do_reset(host, SDHCI_RESET_CMD | + SDHCI_RESET_DATA); + } else { + sdhci_do_reset(host, SDHCI_RESET_CMD); + sdhci_do_reset(host, SDHCI_RESET_DATA); + } host->pending_reset = false; } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 95a08f09df30..8045308f7859 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -480,6 +480,8 @@ struct sdhci_host { * block count. */ #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) +/* Issue CMD and DATA reset together */ +#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ From patchwork Mon Sep 26 09:49:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 610455 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B2F8C32771 for ; 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Mon, 26 Sep 2022 02:49:31 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , Subject: [PATCH v3 4/4] mmc: sdhci-tegra: Use actual clock rate for SW tuning correction Date: Mon, 26 Sep 2022 15:19:06 +0530 Message-ID: <20220926094906.14537-4-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220926094906.14537-1-pshete@nvidia.com> References: <20220926094906.14537-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT074:EE_|CH0PR12MB5282:EE_ X-MS-Office365-Filtering-Correlation-Id: 18acefec-5c8e-4605-8092-08da9fa4745d X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: fNvIOhB0Ko150R7wtczjqpS+3eTvrz1zvViMlbydY0H1rRZOwgZVf8YTcIY4qdfwJGfyud2hmNtEbx7wM060buFTpXMuLCNyjG2J57ByE3zj1saSniNQM7uXz+1bGrYRbz3eQZUuRWAiIExCVNb/b8Gq7iwvPvTaTmhQUzOnX/z85RHSlJa8wbM/z6656WQTExWsm8/wENUmR/E1+bS12gxV86zkf8hIIK7qyhY6qRd6Y/BRtUfxZXEg83/vMH8IN86u5e2Ver9NFLnSs1iGpCSiUry/avr/VRZFxiqcjrzhnI0UrnSLK2y6M3MHTBr+FgxvYYOxcsYnBSfYUXvbHfq2o5mR1GtMzOPZQs80CWkR1w5rWUNEp6EUy9xGH8JloSIbCzoOkWkHL8svthatq6ZyG+CEXEldtZUSLUkQBkmn8oo+k5OM5+elhS+dki9mD5sUjz1J44Ke9xmiaPjbHaqDE2+Bkq95iSsrgWKXRTe0++bOWFQZoQ6xm4WOaWV+1dHw6+lMiBL8dYq9NEfL0mJcno1NpyVLFCkFiMMlaaJ9Lv2ZP7Zwy6maQymhFXyf9CuXhBvui3bpGthDTERC44CIyi44LkEpD+juXzf+QeyqYpF92+JT+6LHY/BTNkCg5LXq8gJJ1U4pwUUSkgsGKwwDCoqOYEw2qaTWLjEceDXWkWb/PeGwox5rrXHSOw8yfmw3MJgVJfalaWXODTkKNAncHIe2mppkqVrkEBjPy+xzJs9tP1bN3xISggkp9zAy6JxrB5dhv0wVy2oe9mnltw== X-Forefront-Antispam-Report: CIP:216.228.117.160; CTRY:US; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:mail.nvidia.com; PTR:dc6edge1.nvidia.com; CAT:NONE; SFS:(13230022)(4636009)(396003)(39860400002)(376002)(136003)(346002)(451199015)(40470700004)(46966006)(36840700001)(82740400003)(86362001)(7636003)(36756003)(356005)(36860700001)(2906002)(336012)(1076003)(186003)(2616005)(40460700003)(82310400005)(5660300002)(40480700001)(107886003)(6666004)(41300700001)(478600001)(7696005)(47076005)(26005)(426003)(83380400001)(316002)(110136005)(54906003)(8676002)(4326008)(70586007)(70206006)(8936002); DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 26 Sep 2022 09:49:50.0053 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 18acefec-5c8e-4605-8092-08da9fa4745d X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT074.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5282 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Ensure tegra_host member "curr_clk_rate" holds the actual clock rate instead of requested clock rate for proper use during tuning correction algorithm. Actual clk rate may not be the same as the requested clk frequency depending on the parent clock source set. Tuning correction algorithm depends on certain parameters which are sensitive to current clk rate. If the host clk is selected instead of the actual clock rate, tuning correction algorithm may end up applying invalid correction, which could result in errors Fixes: ea8fc5953e8b ("mmc: tegra: update hw tuning process") Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete Acked-by: Adrian Hunter --- drivers/mmc/host/sdhci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 58449e010a9b..10f6df070456 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -780,7 +780,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) dev_err(dev, "failed to set clk rate to %luHz: %d\n", host_clk, err); - tegra_host->curr_clk_rate = host_clk; + tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk); if (tegra_host->ddr_signaling) host->max_clk = host_clk; else