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[95.232.92.192]) by smtp.gmail.com with ESMTPSA id f23-20020a056402161700b0045703d699b9sm3252594edv.78.2022.09.25.10.52.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 10:52:17 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Marc Kleine-Budde , Vincent Mailhol , michael@amarulasolutions.com, Amarula patchwork , Alexandre Torgue , Dario Binacchi , Christophe Roullier , Krzysztof Kozlowski , Lee Jones , Mathieu Poirier , Maxime Coquelin , Patrice Chotard , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH v4 1/5] dt-bindings: arm: stm32: add compatible for syscon gcan node Date: Sun, 25 Sep 2022 19:52:05 +0200 Message-Id: <20220925175209.1528960-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220925175209.1528960-1-dario.binacchi@amarulasolutions.com> References: <20220925175209.1528960-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since commit ad440432d1f9 ("dt-bindings: mfd: Ensure 'syscon' has a more specific compatible") It is required to provide at least 2 compatibles string for syscon node. This patch documents the new compatible for stm32f4 SoC to support global/shared CAN registers access for bxCAN controllers. Signed-off-by: Dario Binacchi --- (no changes since v1) .../devicetree/bindings/arm/stm32/st,stm32-syscon.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index 6f846d69c5e1..8646350dac44 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -20,6 +20,7 @@ properties: - st,stm32-syscfg - st,stm32-power-config - st,stm32-tamp + - st,stm32f4-gcan - const: syscon - items: - const: st,stm32-tamp @@ -42,6 +43,7 @@ if: contains: enum: - st,stm32mp157-syscfg + - st,stm32f4-gcan then: required: - clocks From patchwork Sun Sep 25 17:52:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 609242 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 276C6C04A95 for ; Sun, 25 Sep 2022 17:52:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232871AbiIYRw1 (ORCPT ); Sun, 25 Sep 2022 13:52:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46746 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229674AbiIYRwY (ORCPT ); Sun, 25 Sep 2022 13:52:24 -0400 Received: from mail-ej1-x630.google.com (mail-ej1-x630.google.com [IPv6:2a00:1450:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A85FA1F2DE for ; Sun, 25 Sep 2022 10:52:22 -0700 (PDT) Received: by mail-ej1-x630.google.com with SMTP id z13so9860560ejp.6 for ; Sun, 25 Sep 2022 10:52:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=dOPE1L7q5E7QdZRAYhm0K2Z1Q5vapQyABM0Y6Kwo/zE=; b=rpXllgi1ui0C+7mDAPG3UTMJMKX3GqJkXwVqkF+rT3uGpiGSLf62ihJPuG3CrAO29p cRw4A0eLtVJGfsdxFTl89+sNm9OMd/yJTYiqKk2U84orUKiBk2K4xlK7gzMbcEOTARY/ 56WOCSemX4jGl5BmH2khUUmFEpCsQmBUAM/ww= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=dOPE1L7q5E7QdZRAYhm0K2Z1Q5vapQyABM0Y6Kwo/zE=; b=Wp5T0LNL8XncbNnkfBIDbgfcRHrSGf8VCGPe3x023oEbRnm2ys9xVIw1YjguUYdNwU MPnz3JMhol2NPz041+TIG62er7AFJAuKc+Ih6L/CrjXvpCteLEK/Xy+mVIAg3IBoGWg9 J8Y0vpVtwSwHCO96cX86+j9T1jfhfScAddRS38DTs+BqZAjauWdmSbaC64W9CT/FBZnH +5YkpbvAWAzMguisFVqNH9t8Tpvjees4MYWqEinJkc0Pcd4vGvnQ4iWocnwa2nd/qLG0 4CfuThgo6r3zIpiBiteKUQbWi0acYExnCqW5leXvLfVWihP7RuKrLeCJF5ekjU+ssVrL 21Bg== X-Gm-Message-State: ACrzQf2htn8a4xHmn4DWYTJx+8HvZhJyX/o1Gc5GkIWh/bBzCNbaVZGD BWaPWqE9DIMEWiEI572fzVtmiA== X-Google-Smtp-Source: AMsMyM7aJJDiFqfcUqHoW3X3EVzo65dZxU25xJIKTVawhR1ThjMIQqAHd5wMOFH5AhT+XV1BFlOEPw== X-Received: by 2002:a17:907:6e17:b0:783:7839:ff3f with SMTP id sd23-20020a1709076e1700b007837839ff3fmr1778971ejc.300.1664128341028; Sun, 25 Sep 2022 10:52:21 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-95-232-92-192.retail.telecomitalia.it. [95.232.92.192]) by smtp.gmail.com with ESMTPSA id f23-20020a056402161700b0045703d699b9sm3252594edv.78.2022.09.25.10.52.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 25 Sep 2022 10:52:20 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Rob Herring , Krzysztof Kozlowski , Marc Kleine-Budde , Vincent Mailhol , michael@amarulasolutions.com, Amarula patchwork , Alexandre Torgue , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH v4 3/5] ARM: dts: stm32: add CAN support on stm32f429 Date: Sun, 25 Sep 2022 19:52:07 +0200 Message-Id: <20220925175209.1528960-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220925175209.1528960-1-dario.binacchi@amarulasolutions.com> References: <20220925175209.1528960-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for bxcan (Basic eXtended CAN controller) to STM32F429. The chip contains two CAN peripherals, CAN1 the master and CAN2 the slave, that share some of the required logic like clock and filters. This means that the slave CAN can't be used without the master CAN. Signed-off-by: Dario Binacchi --- Changes in v4: - Replace the node can@40006400 (compatible "st,stm32f4-bxcan-core") with the gcan@40006600 node ("sysnode" compatible). The gcan node contains clocks and memory addresses shared by the two can nodes of which it's no longer the parent. - Add to can nodes the "st,gcan" property (global can memory) which references the gcan@40006600 node ("sysnode compatibble). Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add "clocks" to can@0 node. arch/arm/boot/dts/stm32f429.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c31ceb821231..ce08872109b8 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -362,6 +362,35 @@ i2c3: i2c@40005c00 { status = "disabled"; }; + gcan: gcan@40006600 { + compatible = "st,stm32f4-gcan", "syscon"; + reg = <0x40006600 0x200>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + }; + + can1: can@40006400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006400 0x200>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-master; + st,gcan = <&gcan>; + status = "disabled"; + }; + + can2: can@40006800 { + compatible = "st,stm32f4-bxcan"; + reg = <0x40006800 0x200>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + st,gcan = <&gcan>; + status = "disabled"; + }; + dac: dac@40007400 { compatible = "st,stm32f4-dac-core"; reg = <0x40007400 0x400>;