From patchwork Thu Sep 22 11:33:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 608805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FEA4C6FA82 for ; Thu, 22 Sep 2022 11:42:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231622AbiIVLmn (ORCPT ); Thu, 22 Sep 2022 07:42:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45868 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231516AbiIVLmj (ORCPT ); Thu, 22 Sep 2022 07:42:39 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9F3959B87A; Thu, 22 Sep 2022 04:42:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846950; x=1695382950; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NIg+JBCR/twJ2RBPvKp6tEpiUcTMk/K+NCKOIit58vM=; b=0jVPYqjO19it8z6oJ2pd2HTZ+L0pHmh9oAqAlWEC+IQGjQUAoDZ2HZVe O2i9/CzES4eGR/hGH+zUYKeB6S2I9aNsY83drqJqY0W5wREvmmOLqDDU5 pw0P5Uh+yhgx2cPssX5tcAwtAXrLBDGQRq0ma+ZJC7ODMIYAokHV/vtGu CYNQ2VOigCVw2lfm//jDK9o1QR7GdKc431a+yRW7fJ0C/cNxDfRhQmsbJ EtMu5OPWJFD7eW5wqV4tFZnL2tPjJ13WgQq61bBOA0u9jPLnRDaq9uxw8 FQ4Mw8vHqEkPtlpEAUEuN3w8JPLSaMaeCXTJyLduQjjKrdOuYSZvxCI0+ g==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="181504730" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:42:28 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:42:27 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:42:20 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v5 2/9] dt-bindings: serial: atmel,at91-usart: convert to json-schema Date: Thu, 22 Sep 2022 14:33:40 +0300 Message-ID: <20220922113347.144383-3-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Convert at91 USART DT Binding for Atmel/Microchip SoCs to json-schema format. Furthermore, move this binding to the serial directory, since binding directories match hardware, unlike the driver subsystems which match Linux convention. Signed-off-by: Sergiu Moga Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: - only do what the commit says, split the addition of other compatibles and properties in other patches - remove unnecessary "|"'s - mention header in `atmel,usart-mode`'s description - place `if:` under `allOf:` - respect order of spi0's DT properties: compatible, then reg then the reset of properties v2 -> v3: - Previously [PATCH 5] - Check value of `atmel,usart-mode` instead of the node regex - Define all properties top level and disallow them explicitly for other type, since additionalProperties:false conflicts with referencing other schemas - Remove useless else if: after else: v3 -> v4: - add R-b tag, this was previously [PATCH 6] v4 -> v5: - Nothing .../devicetree/bindings/mfd/atmel-usart.txt | 98 ---------- .../bindings/serial/atmel,at91-usart.yaml | 182 ++++++++++++++++++ 2 files changed, 182 insertions(+), 98 deletions(-) delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-usart.txt create mode 100644 Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt deleted file mode 100644 index a09133066aff..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt +++ /dev/null @@ -1,98 +0,0 @@ -* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) - -Required properties for USART: -- compatible: Should be one of the following: - - "atmel,at91rm9200-usart" - - "atmel,at91sam9260-usart" - - "microchip,sam9x60-usart" - - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart" - - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart" - - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt -- clock-names: tuple listing input clock names. - Required elements: "usart" -- clocks: phandles to input clocks. - -Required properties for USART in SPI mode: -- #size-cells : Must be <0> -- #address-cells : Must be <1> -- cs-gpios: chipselects (internal cs not supported) -- atmel,usart-mode : Must be (found in dt-bindings/mfd/at91-usart.h) - -Optional properties in serial and SPI mode: -- dma bindings for dma transfer: - - dmas: DMA specifier, consisting of a phandle to DMA controller node, - memory peripheral interface and USART DMA channel ID, FIFO configuration. - The order of DMA channels is fixed. The first DMA channel must be TX - associated channel and the second one must be RX associated channel. - Refer to dma.txt and atmel-dma.txt for details. - - dma-names: "tx" for TX channel. - "rx" for RX channel. - The order of dma-names is also fixed. The first name must be "tx" - and the second one must be "rx" as in the examples below. - -Optional properties in serial mode: -- atmel,use-dma-rx: use of PDC or DMA for receiving data -- atmel,use-dma-tx: use of PDC or DMA for transmitting data -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. - It will use specified PIO instead of the peripheral function pin for the USART feature. - If unsure, don't specify this property. -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO - capable USARTs. -- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt - - compatible description: -- at91rm9200: legacy USART support -- at91sam9260: generic USART implementation for SAM9 SoCs - -Example: -- use PDC: - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x4000>; - interrupts = <7>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; - cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; - dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; - dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; - dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; - rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; - }; - -- use DMA: - usart0: serial@f001c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf001c000 0x100>; - interrupts = <12 4 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - dmas = <&dma0 2 0x3>, - <&dma0 2 0x204>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - }; - -- SPI mode: - #include - - spi0: spi@f001c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart"; - atmel,usart-mode = ; - reg = <0xf001c000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - cs-gpios = <&pioB 3 0>; - }; diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml new file mode 100644 index 000000000000..bb1b5ed431f7 --- /dev/null +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -0,0 +1,182 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/serial/atmel,at91-usart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) + +maintainers: + - Richard Genoud + +properties: + compatible: + oneOf: + - enum: + - atmel,at91rm9200-usart + - atmel,at91sam9260-usart + - microchip,sam9x60-usart + - items: + - const: atmel,at91rm9200-dbgu + - const: atmel,at91rm9200-usart + - items: + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x60-dbgu + - const: microchip,sam9x60-usart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + const: usart + + clocks: + maxItems: 1 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + atmel,usart-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Must be either for SPI or + for USART (found in dt-bindings/mfd/at91-usart.h). + enum: [ 0, 1 ] + + atmel,use-dma-rx: + type: boolean + description: use of PDC or DMA for receiving data + + atmel,use-dma-tx: + type: boolean + description: use of PDC or DMA for transmitting data + + atmel,fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Maximum number of data the RX and TX FIFOs can store for FIFO + capable USARTS. + enum: [ 16, 32 ] + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + - atmel,usart-mode + +allOf: + - if: + properties: + atmel,usart-mode: + const: 1 + then: + allOf: + - $ref: /schemas/spi/spi-controller.yaml# + + properties: + atmel,use-dma-rx: false + + atmel,use-dma-tx: false + + atmel,fifo-size: false + + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + + required: + - "#size-cells" + - "#address-cells" + + else: + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + /* use PDC */ + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x4000>; + atmel,usart-mode = ; + interrupts = <7>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; + cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; + dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; + dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; + dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; + rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; + }; + + - | + #include + #include + #include + #include + + /* use DMA */ + usart1: serial@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + atmel,usart-mode = ; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + }; + + - | + #include + #include + #include + #include + + /* SPI mode */ + spi0: spi@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + #address-cells = <1>; + #size-cells = <0>; + atmel,usart-mode = ; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; + }; From patchwork Thu Sep 22 11:33:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 608804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26A31C6FA86 for ; Thu, 22 Sep 2022 11:43:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231657AbiIVLn1 (ORCPT ); Thu, 22 Sep 2022 07:43:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231607AbiIVLnD (ORCPT ); Thu, 22 Sep 2022 07:43:03 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B51CE9B84B; Thu, 22 Sep 2022 04:42:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846963; x=1695382963; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CDmfB3LXHlTY7cYfzI1AY48LKvPYcljTNoK8CbnBZSU=; b=RZMyvFiRMg61io61NtC+Jtxbx2v4I71/RMZUMnduy8ISnUGlyWOxIMR7 x8pDzz5bUGnxbChTzba1xEFOD1B8BY5j3O7CsGvQTsYixaHqZ1F4dFo6L Ht9BXDGK4+LnxKLyydwBN37Mgw06oBGXdiZFiZ9dYpB+Ae4D5t8CiOB5F +Mo0pO/wc7jRNjYJMQacouWaiFtthg12lP41NJm7QwwAMbq9Dqpat4+Sd a1QoYpqZ5r7HEjs4pKfPZw2qqXT1JFzoEDwuUkFYXxfgjDP82BeXAbO3i 35Bws9dJNFcWwbHsajSnMhthlBrYTgxN0BE5/Uc0CqNvjTo+lmUgYvWKG g==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="178390512" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:42:42 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:42:42 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:42:36 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v5 4/9] dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref binding Date: Thu, 22 Sep 2022 14:33:42 +0300 Message-ID: <20220922113347.144383-5-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org FLEXCOM, among other functionalities, has the ability to offer the USART serial communication protocol. To have the FLEXCOM binding properly validate its USART children nodes, we must reference the correct binding. To differentiate between the SPI of FLEXCOM and the SPI of USART in SPI mode, use the compatible string. Signed-off-by: Sergiu Moga Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing v2 -> v3: - Previously [PATCH 7] - Compare devices based on the compatible instead of the clock v3 -> v4: - add A-b tag, this was previously [PATCH 8] v4 -> v5: - Nothing .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index f283cfd84b2d..0ebe624c2d32 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -72,13 +72,21 @@ properties: patternProperties: "^serial@[0-9a-f]+$": - type: object + $ref: /schemas/serial/atmel,at91-usart.yaml description: - Child node describing USART. See atmel-usart.txt for details - of USART bindings. + Child node describing USART. "^spi@[0-9a-f]+$": - $ref: /schemas/spi/atmel,at91rm9200-spi.yaml + allOf: + - if: + properties: + compatible: + contains: + const: atmel,at91sam9260-usart + then: + $ref: /schemas/serial/atmel,at91-usart.yaml + else: + $ref: /schemas/spi/atmel,at91rm9200-spi.yaml description: Child node describing SPI. From patchwork Thu Sep 22 11:33:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 608803 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DBC7C54EE9 for ; Thu, 22 Sep 2022 11:43:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231593AbiIVLnt (ORCPT ); Thu, 22 Sep 2022 07:43:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45782 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231652AbiIVLnY (ORCPT ); Thu, 22 Sep 2022 07:43:24 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E87F8E5127; Thu, 22 Sep 2022 04:43:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846981; x=1695382981; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PkvW2+v4ra7Kos8RB8EjzdxzU827BFV7cqmkcNq8EWY=; b=KIMc6MU4uEa2K28bTfNUvvLFMLEsOLude3k5R8mmO9CsBx3ozbUL1/dM nLmWrHc1zM9MLA/Ovz1An7/gC84ZOp2gaT0frY8M5nTIbMRyHLVIFfjRK chL8BM4gpEZ5ngtcXIAfy2ta8LfabS6kDPTvFPZAVGqhAS2X1XZY5WwBF kgNvP7c+asLxs2IamJMSmmLUy8AiA/Thz/iBha0zCbiOcHw9CY2uOJKsU V25I/OTQDK4iTPwNCyaN9fJ8PorH9zqYBAqVgoJ2GWtrrXypUlVg1e4fn ZWmMUCALP0tXb4Ql11Whel7YgJ8jBQqzxxPvntsHu9D0KpEaQ0XcFxdYc Q==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="114897503" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:43:00 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:42:58 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:42:52 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v5 6/9] tty: serial: atmel: Separate mode clearing between UART and USART Date: Thu, 22 Sep 2022 14:33:44 +0300 Message-ID: <20220922113347.144383-7-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org When clearing the mode of the serial IP inside the atmel_set_termios() method, make sure that the difference between the bitfields placement of the UART IP's and USART IP's is taken into account, as some of them overlap with each other. For example, ATMEL_UA_BRSRCCK overlaps with ATMEL_US_NBSTOP and ATMEL_US_USCLKS overlaps with ATMEL_UA_FILTER. Furthermore, add definitions for the Baud Rate Source Clock and the Filter bitfields of the Mode Register of UART IP's, since they were missing. Signed-off-by: Sergiu Moga Reviewed-by: Claudiu Beznea --- v1 -> v5: - This patch was not here before but it also includes the previous patch: `[PATCH v4 7/9] tty: serial: atmel: Define BRSRCCK bitmask of UART IP's Mode Register` squashed into it and define BRSRCCK as a bitfield instead of a bitmask, since it is only 1 bit. drivers/tty/serial/atmel_serial.c | 7 +++++-- drivers/tty/serial/atmel_serial.h | 2 ++ 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index ab4a9dfae07d..e3e14cb7668b 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -2134,8 +2134,11 @@ static void atmel_set_termios(struct uart_port *port, mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); /* reset the mode, clock divisor, parity, stop bits and data size */ - mode &= ~(ATMEL_US_USCLKS | ATMEL_US_CHRL | ATMEL_US_NBSTOP | - ATMEL_US_PAR | ATMEL_US_USMODE); + if (atmel_port->is_usart) + mode &= ~(ATMEL_US_NBSTOP | ATMEL_US_PAR | ATMEL_US_CHRL | + ATMEL_US_USCLKS | ATMEL_US_USMODE); + else + mode &= ~(ATMEL_UA_BRSRCCK | ATMEL_US_PAR | ATMEL_UA_FILTER); baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk / 16); diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 0d8a0f9cc5c3..2a525b58e11a 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -50,6 +50,7 @@ #define ATMEL_US_USCLKS_MCK (0 << 4) #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) #define ATMEL_US_USCLKS_SCK (3 << 4) +#define ATMEL_UA_FILTER BIT(4) #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */ #define ATMEL_US_CHRL_5 (0 << 6) #define ATMEL_US_CHRL_6 (1 << 6) @@ -67,6 +68,7 @@ #define ATMEL_US_NBSTOP_1 (0 << 12) #define ATMEL_US_NBSTOP_1_5 (1 << 12) #define ATMEL_US_NBSTOP_2 (2 << 12) +#define ATMEL_UA_BRSRCCK BIT(12) /* Clock Selection for UART */ #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */ #define ATMEL_US_CHMODE_NORMAL (0 << 14) #define ATMEL_US_CHMODE_ECHO (1 << 14) From patchwork Thu Sep 22 11:33:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 608802 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 739D9C6FA86 for ; Thu, 22 Sep 2022 11:44:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231727AbiIVLo2 (ORCPT ); Thu, 22 Sep 2022 07:44:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46752 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231749AbiIVLni (ORCPT ); Thu, 22 Sep 2022 07:43:38 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A338E5133; Thu, 22 Sep 2022 04:43:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663846999; x=1695382999; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LcX022xRUzBf++bl2M+uwrENEsDp/g+PctVotxaJa3c=; b=17WLRBSMrstz6uIvRN8n/AsuVpzV01AeN6PYourLNTu10Zk9DNZ1yqqk 13uEOLLr1BzNWQs1X4POH29WXPnku0tYGMJURdGsZi5DNaH8+boweu6Hr 0dHIY6P+5Ycv8nubWd7Gy8/zP40+JnZ5ue89KYKBv+tgm3dY0PVaG4wpD +xp8hDCyTiIcGgr3FmvCLoASazduSxv4sH+uSXishzlHx8mr0GnYf8PSW 7bFs8RmMSrX+UWNsGCoy3P3TsPhJoZbsqoXtunzPj6C2QHRGN8JReLuPY uHTOxlALzCs6/daU8U7fTphNKbBqm2Omf0vv/PhNspOqXV5BuPuXHKwl+ g==; X-IronPort-AV: E=Sophos;i="5.93,335,1654585200"; d="scan'208";a="178390576" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 22 Sep 2022 04:43:18 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 22 Sep 2022 04:43:15 -0700 Received: from ROB-ULT-M68701.amer.actel.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 22 Sep 2022 04:43:06 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v5 8/9] tty: serial: atmel: Make the driver aware of the existence of GCLK Date: Thu, 22 Sep 2022 14:33:46 +0300 Message-ID: <20220922113347.144383-9-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220922113347.144383-1-sergiu.moga@microchip.com> References: <20220922113347.144383-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-spi@vger.kernel.org Previously, the atmel serial driver did not take into account the possibility of using the more customizable generic clock as its baudrate generator. Unless there is a Fractional Part available to increase accuracy, there is a high chance that we may be able to generate a baudrate closer to the desired one by using the GCLK as the clock source. Now, depending on the error rate between the desired baudrate and the actual baudrate, the serial driver will fallback on the generic clock. The generic clock must be provided in the DT node of the serial that may need a more flexible clock source. Furthermore, define the bit that represents the choice of having GCLK as a baudrate source clock inside the USCLKS bitmask of the Mode Register of USART IP's. Signed-off-by: Sergiu Moga Reviewed-by: Claudiu Beznea --- v1 -> v2: - take into account the different placement of the baudrate clock source into the IP's Mode Register (USART vs UART) - don't check for atmel_port->gclk != NULL - use clk_round_rate instead of clk_set_rate + clk_get_rate - remove clk_disable_unprepare from the end of the probe method v2 -> v3: - add the error rate calculation function as an inline function instead of a macro definition - add `gclk_fail` goto - replace `goto err` with `goto err_clk_disable_unprepare;` v3 -> v4: - Nothing, this was previously [PATCH 14] v4 -> v5: - Squashed the previous `[PATCH v4 6/9] tty: serial: atmel: Define GCLK as USART baudrate source clock` into this current commit - No more BRSRCCK bitmask as it is only 1 bit drivers/tty/serial/atmel_serial.c | 58 ++++++++++++++++++++++++++++++- drivers/tty/serial/atmel_serial.h | 1 + 2 files changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index acbf6b82d687..bd07f79a2df9 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -110,6 +111,7 @@ struct atmel_uart_char { struct atmel_uart_port { struct uart_port uart; /* uart */ struct clk *clk; /* uart clock */ + struct clk *gclk; /* uart generic clock */ int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ u32 backup_imr; /* IMR saved during suspend */ int break_active; /* break being received */ @@ -229,6 +231,11 @@ static inline int atmel_uart_is_half_duplex(struct uart_port *port) (port->iso7816.flags & SER_ISO7816_ENABLED); } +static inline int atmel_error_rate(int desired_value, int actual_value) +{ + return 100 - (desired_value * 100) / actual_value; +} + #ifdef CONFIG_SERIAL_ATMEL_PDC static bool atmel_use_pdc_rx(struct uart_port *port) { @@ -2117,6 +2124,8 @@ static void atmel_serial_pm(struct uart_port *port, unsigned int state, * This is called on uart_close() or a suspend event. */ clk_disable_unprepare(atmel_port->clk); + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); break; default: dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); @@ -2132,7 +2141,9 @@ static void atmel_set_termios(struct uart_port *port, { struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); unsigned long flags; - unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0; + unsigned int old_mode, mode, imr, quot, div, cd, fp = 0; + unsigned int baud, actual_baud, gclk_rate; + int ret; /* save the current mode register */ mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); @@ -2305,6 +2316,45 @@ static void atmel_set_termios(struct uart_port *port, cd = min_t(unsigned int, cd, ATMEL_US_CD); } + /* + * If there is no Fractional Part, there is a high chance that + * we may be able to generate a baudrate closer to the desired one + * if we use the GCLK as the clock source driving the baudrate + * generator. + */ + if (!atmel_port->has_frac_baudrate) { + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); + gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud); + actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd); + if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) > + abs(atmel_error_rate(baud, gclk_rate / 16))) { + clk_set_rate(atmel_port->gclk, 16 * baud); + ret = clk_prepare_enable(atmel_port->gclk); + if (ret) + goto gclk_fail; + + if (atmel_port->is_usart) { + mode &= ~ATMEL_US_USCLKS; + mode |= ATMEL_US_USCLKS_GCLK; + } else { + mode |= ATMEL_UA_BRSRCCK; + } + + /* + * Set the Clock Divisor for GCLK to 1. + * Since we were able to generate the smallest + * multiple of the desired baudrate times 16, + * then we surely can generate a bigger multiple + * with the exact error rate for an equally increased + * CD. Thus no need to take into account + * a higher value for CD. + */ + cd = 1; + } + } + +gclk_fail: quot = cd | fp << ATMEL_US_FP_OFFSET; if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) @@ -2900,6 +2950,12 @@ static int atmel_serial_probe(struct platform_device *pdev) if (ret) goto err; + atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk"); + if (IS_ERR(atmel_port->gclk)) { + ret = PTR_ERR(atmel_port->gclk); + goto err_clk_disable_unprepare; + } + ret = atmel_init_port(atmel_port, pdev); if (ret) goto err_clk_disable_unprepare; diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 2a525b58e11a..0fcadbeabc6c 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -49,6 +49,7 @@ #define ATMEL_US_USCLKS GENMASK(5, 4) /* Clock Selection */ #define ATMEL_US_USCLKS_MCK (0 << 4) #define ATMEL_US_USCLKS_MCK_DIV8 (1 << 4) +#define ATMEL_US_USCLKS_GCLK (2 << 4) #define ATMEL_US_USCLKS_SCK (3 << 4) #define ATMEL_UA_FILTER BIT(4) #define ATMEL_US_CHRL GENMASK(7, 6) /* Character Length */