From patchwork Fri Sep 23 12:17:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: matthew.gerlach@linux.intel.com X-Patchwork-Id: 608798 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0C963C6FA8E for ; Fri, 23 Sep 2022 12:22:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232107AbiIWMWl (ORCPT ); Fri, 23 Sep 2022 08:22:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41624 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231588AbiIWMV6 (ORCPT ); Fri, 23 Sep 2022 08:21:58 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06E18135046; Fri, 23 Sep 2022 05:17:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663935450; x=1695471450; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HyCYvT4MS9aixSrjDPMIu3T0VuZk0mTl3XzcDjq7QLc=; b=Pfin51E61Eha6ZMYr0qpf63pT4sqikWy2dx9kpPO9oXhe3TgnsiHy1kB UF81lhbIP8XfBCL/OUuoIrm6z0+cYZcDalKqwJcCCSTSmQSsd4wpnudaM 7NG0R29Q7qHmoN70g6AU3c9l+3/ACgDp3umtBumXHIbYF7ZtS+T66OxSn 0i7hPEJnr7oHJYIsc6DKNv6XH7BoVIXFTo0CXG5SToeMniHbb4HgG/o2b 6HDpIJzXfyuR+4guEek+sHumRc725ihEORyAmm2BLDxKBKebdzsGZgOgT DlyMfwySP/TYEE8T+dFWLpCaccGIuPuuK4ok974MrsnA7oDeWpdsG4xgx g==; X-IronPort-AV: E=McAfee;i="6500,9779,10478"; a="364595264" X-IronPort-AV: E=Sophos;i="5.93,339,1654585200"; d="scan'208";a="364595264" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2022 05:17:29 -0700 X-IronPort-AV: E=Sophos;i="5.93,339,1654585200"; d="scan'208";a="762597729" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.139]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2022 05:17:29 -0700 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de Cc: Matthew Gerlach Subject: [PATCH v2 1/6] Documentation: fpga: dfl: Add documentation for DFHv1 Date: Fri, 23 Sep 2022 05:17:40 -0700 Message-Id: <20220923121745.129167-2-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> References: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Matthew Gerlach Add documentation describing the extensions provided by Version 1 of the Device Feature Header (DFHv1). Signed-off-by: Matthew Gerlach --- v2: s/GUILD/GUID/ add picture --- Documentation/fpga/dfl.rst | 49 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 49 insertions(+) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index 15b670926084..7c786b75b498 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -561,6 +561,55 @@ new DFL feature via UIO direct access, its feature id should be added to the driver's id_table. +Extending the Device Feature Header - DFHv1 +=========================================== +The current 8 bytes of the Device Feature Header, hereafter referred to as +to DFHv0, provide very little opportunity for the hardware to describe itself +to software. Version 1 of the Device Feature Header (DFHv1) is being introduced +to provide increased flexibility and extensibility to hardware designs using +Device Feature Lists. The list below describes some of the goals behind the +changes in DFHv1: + +* Provide a standardized mechanism for features to describe + parameters/capabilities to software. +* Standardize the use of a GUID for all DFHv1 types. +* Decouple the location of the DFH from the register space of the feature itself. + +Modeled after PCI Capabilities, DFHv1 Parameters provide a mechanism to associate +a list of parameter values to a particular feature. + +With DFHv0, not all features types contained a GUID. DFHv1 makes the GUID standard +across all types. + +With DFHv0, the register map of a given feature is located immediately following +the DFHv0 in the memory space. With DFHv1, the location of the feature register +map can be specified as an offset to the DFHv1 or as an absolute address. The DFHv1 +structure is shown below: + + +-----------------------------------------------------------------------+ + |63 Type 60|59 DFH VER 52|51 Rsvd 41|40 EOL|39 Next 16|15 VER 12|11 ID 0| + +-----------------------------------------------------------------------+ + |63 GUID_L 0| + +-----------------------------------------------------------------------+ + |63 GUID_H 0| + +-----------------------------------------------------------------------+ + |63 Address/Offset 1| Rel 0| + +-----------------------------------------------------------------------+ + |63 Size of register set 32|Params 31|30 Group 16|15 Instance 0| + +-----------------------------------------------------------------------+ + |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0| + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| + +-----------------------------------------------------------------------+ + + ... + + +-----------------------------------------------------------------------+ + |63 Next parameter offset 32|31 Param Version 16|15 Param ID 0| + +-----------------------------------------------------------------------+ + |63 Parameter Data 0| + +-----------------------------------------------------------------------+ + Open discussion =============== FME driver exports one ioctl (DFL_FPGA_FME_PORT_PR) for partial reconfiguration From patchwork Fri Sep 23 12:17:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: matthew.gerlach@linux.intel.com X-Patchwork-Id: 608797 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2229C6FA95 for ; Fri, 23 Sep 2022 12:22:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232124AbiIWMWn (ORCPT ); Fri, 23 Sep 2022 08:22:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231474AbiIWMV6 (ORCPT ); Fri, 23 Sep 2022 08:21:58 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25108135047; Fri, 23 Sep 2022 05:17:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663935451; x=1695471451; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=G3/jDHfEgmt1mU16f2cag46kqaswEiQqco0ejWollM4=; b=VYXetGqXpU9SMfAdQIVeDkI86yECh6mGv77EkcCLk2j5vddFZ+IE8o1C jTlxdcfeOJ7bqzychE8XFgI541V5vO/aLdRuBGTfmavZC3wzHcqVGARlh IVHNAPpeemXaibAAb7o6o1w9sXAB933Z5vCDYhWbmSgNceKfwH69iT/4l vdVZmj3GlnwSlUxlHHUG3Yu9BYlluXlUPRaSxxQUREu5AJT49BASvkwbd +mhnmboiJNnMbdwV1j89qj0Q6cJcdEX2vSHZEtOfDiy2clyB63ZFSGf29 JgJ1755WJELHl7EwB24ECOGYyrF+VzubQwpNqoArDB+In2ovmMK6NWsQI Q==; X-IronPort-AV: E=McAfee;i="6500,9779,10478"; a="364595273" X-IronPort-AV: E=Sophos;i="5.93,339,1654585200"; d="scan'208";a="364595273" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2022 05:17:30 -0700 X-IronPort-AV: E=Sophos;i="5.93,339,1654585200"; d="scan'208";a="762597732" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.139]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2022 05:17:30 -0700 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de Cc: Basheer Ahmed Muddebihal , Matthew Gerlach Subject: [PATCH v2 2/6] fpga: dfl: Move the DFH definitions Date: Fri, 23 Sep 2022 05:17:41 -0700 Message-Id: <20220923121745.129167-3-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> References: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Basheer Ahmed Muddebihal Moving the DFH register offset and register definitions from drivers/fpga/dfl.h to include/linux/dfl.h. These definitions need to be accessed by dfl drivers that are outside of drivers/fpga. Signed-off-by: Basheer Ahmed Muddebihal Signed-off-by: Matthew Gerlach --- v2: remove extra space in commit use uniform number of digits in constants don't change copyright date because of removed content --- drivers/fpga/dfl-afu-main.c | 4 ++-- drivers/fpga/dfl.c | 2 +- drivers/fpga/dfl.h | 20 +------------------- include/linux/dfl.h | 33 ++++++++++++++++++++++++++++++++- 4 files changed, 36 insertions(+), 23 deletions(-) diff --git a/drivers/fpga/dfl-afu-main.c b/drivers/fpga/dfl-afu-main.c index 7f621e96d3b8..c26961ee33db 100644 --- a/drivers/fpga/dfl-afu-main.c +++ b/drivers/fpga/dfl-afu-main.c @@ -468,8 +468,8 @@ afu_id_show(struct device *dev, struct device_attribute *attr, char *buf) return -EBUSY; } - guidl = readq(base + GUID_L); - guidh = readq(base + GUID_H); + guidl = readq(base + DFH_GUID_L); + guidh = readq(base + DFH_GUID_H); mutex_unlock(&pdata->lock); return scnprintf(buf, PAGE_SIZE, "%016llx%016llx\n", guidh, guidl); diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index b9aae85ba930..1132f3c10440 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -1163,7 +1163,7 @@ static int parse_feature_fiu(struct build_feature_devs_info *binfo, * find and parse FIU's child AFU via its NEXT_AFU register. * please note that only Port has valid NEXT_AFU pointer per spec. */ - v = readq(binfo->ioaddr + NEXT_AFU); + v = readq(binfo->ioaddr + DFH_NEXT_AFU); offset = FIELD_GET(NEXT_AFU_NEXT_DFH_OFST, v); if (offset) diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 06cfcd5e84bb..e620fcb02b5a 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -53,28 +54,9 @@ #define PORT_FEATURE_ID_UINT 0x12 #define PORT_FEATURE_ID_STP 0x13 -/* - * Device Feature Header Register Set - * - * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. - * For AFUs, they have DFH + GUID as common header registers. - * For private features, they only have DFH register as common header. - */ -#define DFH 0x0 -#define GUID_L 0x8 -#define GUID_H 0x10 -#define NEXT_AFU 0x18 - -#define DFH_SIZE 0x8 - /* Device Feature Header Register Bitfield */ -#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ #define DFH_ID_FIU_FME 0 #define DFH_ID_FIU_PORT 1 -#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ -#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ -#define DFH_EOL BIT_ULL(40) /* End of list */ -#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ #define DFH_TYPE_AFU 1 #define DFH_TYPE_PRIVATE 3 #define DFH_TYPE_FIU 4 diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 431636a0dc78..33d167c53b09 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -2,7 +2,7 @@ /* * Header file for DFL driver and device API * - * Copyright (C) 2020 Intel Corporation, Inc. + * Copyright (C) 2020-2022 Intel Corporation, Inc. */ #ifndef __LINUX_DFL_H @@ -11,6 +11,37 @@ #include #include +/* + * Device Feature Header Register Set + * + * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. + * For AFUs, they have DFH + GUID as common header registers. + * For private features, they only have DFH register as common header. + */ +#define DFH 0x00 +#define DFH_GUID_L 0x08 +#define DFH_GUID_H 0x10 +#define DFH_NEXT_AFU 0x18 + +/* + * DFHv1 Register Offset definitons + * In DHFv1, DFH + GUID + CSR_START + CSR_SIZE_GROUP + PARAM_HDR + PARAM_DATA + * as common header registers + */ +#define DFHv1_CSR_ADDR 0x18 /* CSR Register start address */ +#define DFHv1_CSR_SIZE_GRP 0x20 /* Size of Reg Block and Group/tag */ +#define DFHv1_PARAM_HDR 0x28 /* Optional First Param header */ +#define DFHv1_PARAM_DATA 0x08 /* Offset of Param data from Param header */ + +#define DFH_SIZE 0x08 + +/* Device Feature Header Register Bitfield */ +#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ +#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ +#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ +#define DFH_EOL BIT_ULL(40) /* End of list */ +#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ + /** * enum dfl_id_type - define the DFL FIU types */ From patchwork Fri Sep 23 12:17:44 2022 Content-Type: text/plain; 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23 Sep 2022 05:17:32 -0700 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de Cc: Matthew Gerlach , Matthew Gerlach Subject: [PATCH v2 5/6] fpga: dfl: parse the location of the feature's registers from DFHv1 Date: Fri, 23 Sep 2022 05:17:44 -0700 Message-Id: <20220923121745.129167-6-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> References: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Matthew Gerlach The location of a feature's registers is explicitly described in DFHv1 and can be relative to the base of the DFHv1 or an absolute address. Parse the location and pass the information to DFL driver. Signed-off-by: Matthew Gerlach --- v2: Introduced in v2. --- drivers/fpga/dfl.c | 26 +++++++++++++++++++++++++- drivers/fpga/dfl.h | 4 ++++ include/linux/dfl.h | 4 ++++ 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index dfd3f563c92d..6fb4f30f93cf 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -381,6 +381,8 @@ dfl_dev_add(struct dfl_feature_platform_data *pdata, ddev->feature_id = feature->id; ddev->revision = feature->revision; ddev->cdev = pdata->dfl_cdev; + ddev->csr_start = feature->csr_start; + ddev->csr_size = feature->csr_size; /* add mmio resource */ parent_res = &pdev->resource[feature->resource_index]; @@ -708,18 +710,25 @@ struct build_feature_devs_info { * struct dfl_feature_info - sub feature info collected during feature dev build * * @fid: id of this sub feature. + * @revision: revision of this sub feature + * @dfh_version: version of Device Feature Header (DFH) * @mmio_res: mmio resource of this sub feature. * @ioaddr: mapped base address of mmio resource. * @node: node in sub_features linked list. + * @csr_start: DFHv1 start of feature registers + * @csr_size: DFHv1 size of feature registers * @irq_base: start of irq index in this sub feature. * @nr_irqs: number of irqs of this sub feature. */ struct dfl_feature_info { u16 fid; u8 revision; + u8 dfh_version; struct resource mmio_res; void __iomem *ioaddr; struct list_head node; + resource_size_t csr_start; + resource_size_t csr_size; unsigned int irq_base; unsigned int nr_irqs; }; @@ -797,6 +806,8 @@ static int build_info_commit_dev(struct build_feature_devs_info *binfo) feature->dev = fdev; feature->id = finfo->fid; feature->revision = finfo->revision; + feature->csr_start = finfo->csr_start; + feature->csr_size = finfo->csr_size; /* * the FIU header feature has some fundamental functions (sriov @@ -1054,6 +1065,7 @@ create_feature_instance(struct build_feature_devs_info *binfo, { unsigned int irq_base, nr_irqs; struct dfl_feature_info *finfo; + u8 dfh_version = 0; u8 revision = 0; int ret; u64 v; @@ -1061,7 +1073,7 @@ create_feature_instance(struct build_feature_devs_info *binfo, if (fid != FEATURE_ID_AFU) { v = readq(binfo->ioaddr + ofst); revision = FIELD_GET(DFH_REVISION, v); - + dfh_version = FIELD_GET(DFH_VERSION, v); /* read feature size and id if inputs are invalid */ size = size ? size : feature_size(v); fid = fid ? fid : feature_id(v); @@ -1080,12 +1092,24 @@ create_feature_instance(struct build_feature_devs_info *binfo, finfo->fid = fid; finfo->revision = revision; + finfo->dfh_version = dfh_version; finfo->mmio_res.start = binfo->start + ofst; finfo->mmio_res.end = finfo->mmio_res.start + size - 1; finfo->mmio_res.flags = IORESOURCE_MEM; finfo->irq_base = irq_base; finfo->nr_irqs = nr_irqs; + if (dfh_version == 1) { + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_ADDR); + if (v & DFHv1_CSR_ADDR_REL) + finfo->csr_start = FIELD_GET(DFHv1_CSR_ADDR_MASK, v); + else + finfo->csr_start = binfo->start + ofst + FIELD_GET(DFHv1_CSR_ADDR_MASK, v); + + v = readq(binfo->ioaddr + ofst + DFHv1_CSR_SIZE_GRP); + finfo->csr_size = FIELD_GET(DFHv1_CSR_SIZE_GRP_SIZE, v); + } + list_add_tail(&finfo->node, &binfo->sub_features); binfo->feature_num++; diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index e620fcb02b5a..64cedd00dca4 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -217,6 +217,8 @@ struct dfl_feature_irq_ctx { * this index is used to find its mmio resource from the * feature dev (platform device)'s resources. * @ioaddr: mapped mmio resource address. + * @csr_start: DFHv1 start of feature registers + * @csr_size: DFHv1 size of feature registers * @irq_ctx: interrupt context list. * @nr_irqs: number of interrupt contexts. * @ops: ops of this sub feature. @@ -229,6 +231,8 @@ struct dfl_feature { u8 revision; int resource_index; void __iomem *ioaddr; + resource_size_t csr_start; + resource_size_t csr_size; struct dfl_feature_irq_ctx *irq_ctx; unsigned int nr_irqs; const struct dfl_feature_ops *ops; diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 33e21c360671..7d74ef8d1d20 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -84,6 +84,8 @@ enum dfl_id_type { * @type: type of DFL FIU of the device. See enum dfl_id_type. * @feature_id: feature identifier local to its DFL FIU type. * @mmio_res: mmio resource of this dfl device. + * @csr_start: DFHv1 start of feature registers + * @csr_size: DFHv1 size of feature registers * @irqs: list of Linux IRQ numbers of this dfl device. * @num_irqs: number of IRQs supported by this dfl device. * @cdev: pointer to DFL FPGA container device this dfl device belongs to. @@ -96,6 +98,8 @@ struct dfl_device { u16 feature_id; u8 revision; struct resource mmio_res; + resource_size_t csr_start; + resource_size_t csr_size; int *irqs; unsigned int num_irqs; struct dfl_fpga_cdev *cdev; From patchwork Fri Sep 23 12:17:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: matthew.gerlach@linux.intel.com X-Patchwork-Id: 608796 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D129C6FA82 for ; Fri, 23 Sep 2022 12:22:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232185AbiIWMWq (ORCPT ); Fri, 23 Sep 2022 08:22:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41634 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231641AbiIWMWA (ORCPT ); Fri, 23 Sep 2022 08:22:00 -0400 Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B9F9C13506F; Fri, 23 Sep 2022 05:17:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1663935453; x=1695471453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=6OllXRQtgPFGbhlCOhBzLOUg1JkZUATRFajkga5SoAg=; b=DVX5T65TzM6lnfbR20+5s2rbv/5Yhr4GfxcZiClQ06n8eZOprSJyKint w80hN9xZcVJ8whfjaEOzyVgCBVt21l4MhHMxIP/rAky1j88M2E4cbUJ7Q Z2XksVRQ6OBhDyMfTOEMC823dcLXWet7vHrwWy6WqHRakkBZa7nQuCfOF R7cr7jqKo04N9yZm5VEEhKFv117rn/4mN8L8hL2L0c38+FV2CrDUg/l6/ L+BwmmpfRQbVC91ghI4Y6KQXAIm+lE8i+8Xl+q1MxpUjXl+M4Pc0zC12b o7yb1vJy+s+nJqDKUbN/vmwujm45LBh+JL2oNMMUUE0Xrd8UVL48OC3Ay w==; X-IronPort-AV: E=McAfee;i="6500,9779,10478"; a="364595297" X-IronPort-AV: E=Sophos;i="5.93,339,1654585200"; d="scan'208";a="364595297" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2022 05:17:33 -0700 X-IronPort-AV: E=Sophos;i="5.93,339,1654585200"; d="scan'208";a="762597753" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.139]) by fmsmga001-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Sep 2022 05:17:33 -0700 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de Cc: Matthew Gerlach , kernel test robot Subject: [PATCH v2 6/6] tty: serial: 8250: add DFL bus driver for Altera 16550. Date: Fri, 23 Sep 2022 05:17:45 -0700 Message-Id: <20220923121745.129167-7-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> References: <20220923121745.129167-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Matthew Gerlach Add a Device Feature List (DFL) bus driver for the Altera 16550 implementation of UART. Signed-off-by: Matthew Gerlach Reported-by: kernel test robot --- v2: clean up error messages alphabetize header files fix 'missing prototype' error by making function static tried to sort Makefile and Kconfig better --- drivers/tty/serial/8250/8250_dfl.c | 177 +++++++++++++++++++++++++++++ drivers/tty/serial/8250/Kconfig | 9 ++ drivers/tty/serial/8250/Makefile | 1 + include/linux/dfl.h | 7 ++ 4 files changed, 194 insertions(+) create mode 100644 drivers/tty/serial/8250/8250_dfl.c diff --git a/drivers/tty/serial/8250/8250_dfl.c b/drivers/tty/serial/8250/8250_dfl.c new file mode 100644 index 000000000000..539ca6138eda --- /dev/null +++ b/drivers/tty/serial/8250/8250_dfl.c @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for FPGA UART + * + * Copyright (C) 2022 Intel Corporation, Inc. + * + * Authors: + * Ananda Ravuri + * Matthew Gerlach + */ + +#include +#include +#include +#include +#include +#include +#include + +struct dfl_uart { + void __iomem *csr_base; + struct device *dev; + u64 uart_clk; + u64 fifo_len; + unsigned int fifo_size; + unsigned int reg_shift; + unsigned int line; +}; + +static int feature_uart_walk(struct dfl_uart *dfluart, resource_size_t max) +{ + void __iomem *param_base; + int off; + u64 v; + + v = readq(dfluart->csr_base + DFHv1_CSR_SIZE_GRP); + + if (!FIELD_GET(DFHv1_CSR_SIZE_GRP_HAS_PARAMS, v)) { + dev_err(dfluart->dev, "missing required DFH parameters\n"); + return -EINVAL; + } + + param_base = dfluart->csr_base + DFHv1_PARAM_HDR; + + off = dfl_find_param(param_base, max, DFHv1_PARAM_ID_CLK_FRQ); + if (off < 0) { + dev_err(dfluart->dev, "missing CLK_FRQ param\n"); + return -EINVAL; + } + + dfluart->uart_clk = readq(param_base + off + DFHv1_PARAM_DATA); + dev_dbg(dfluart->dev, "UART_CLK_ID %llu Hz\n", dfluart->uart_clk); + + off = dfl_find_param(param_base, max, DFHv1_PARAM_ID_FIFO_LEN); + if (off < 0) { + dev_err(dfluart->dev, "missing FIFO_LEN param\n"); + return -EINVAL; + } + + dfluart->fifo_len = readq(param_base + off + DFHv1_PARAM_DATA); + dev_dbg(dfluart->dev, "UART_FIFO_ID fifo_len %llu\n", dfluart->fifo_len); + + off = dfl_find_param(param_base, max, DFHv1_PARAM_ID_REG_LAYOUT); + if (off < 0) { + dev_err(dfluart->dev, "missing REG_LAYOUT param\n"); + return -EINVAL; + } + + v = readq(param_base + off + DFHv1_PARAM_DATA); + dfluart->fifo_size = FIELD_GET(DFHv1_PARAM_ID_REG_WIDTH, v); + dfluart->reg_shift = FIELD_GET(DFHv1_PARAM_ID_REG_SHIFT, v); + dev_dbg(dfluart->dev, "UART_LAYOUT_ID width %d shift %d\n", + dfluart->fifo_size, dfluart->reg_shift); + + return 0; +} + +static int dfl_uart_probe(struct dfl_device *dfl_dev) +{ + struct device *dev = &dfl_dev->dev; + struct uart_8250_port uart; + struct dfl_uart *dfluart; + int ret; + + memset(&uart, 0, sizeof(uart)); + + dfluart = devm_kzalloc(dev, sizeof(*dfluart), GFP_KERNEL); + if (!dfluart) + return -ENOMEM; + + dfluart->dev = dev; + + dfluart->csr_base = devm_ioremap_resource(dev, &dfl_dev->mmio_res); + if (IS_ERR(dfluart->csr_base)) { + return PTR_ERR(dfluart->csr_base); + } + + ret = feature_uart_walk(dfluart, resource_size(&dfl_dev->mmio_res)); + + devm_iounmap(dev, dfluart->csr_base); + devm_release_mem_region(dev, dfl_dev->mmio_res.start, resource_size(&dfl_dev->mmio_res)); + + if (ret < 0) + return dev_err_probe(dev, ret, "failed uart feature walk\n"); + + dev_dbg(dev, "nr_irqs %d %p\n", dfl_dev->num_irqs, dfl_dev->irqs); + + if (dfl_dev->num_irqs == 1) + uart.port.irq = dfl_dev->irqs[0]; + + switch (dfluart->fifo_len) { + case 32: + uart.port.type = PORT_ALTR_16550_F32; + break; + + case 64: + uart.port.type = PORT_ALTR_16550_F64; + break; + + case 128: + uart.port.type = PORT_ALTR_16550_F128; + break; + + default: + dev_err(dev, "bad fifo_len %llu\n", dfluart->fifo_len); + return -EINVAL; + } + + uart.port.iotype = UPIO_MEM32; + uart.port.mapbase = dfl_dev->csr_start; + uart.port.mapsize = dfl_dev->csr_size; + uart.port.regshift = dfluart->reg_shift; + uart.port.uartclk = dfluart->uart_clk; + uart.port.flags |= UPF_IOREMAP; + + /* register the port */ + ret = serial8250_register_8250_port(&uart); + if (ret < 0) { + dev_err(dev, "unable to register 8250 port %d.\n", ret); + return -EINVAL; + } + dev_info(dev, "serial8250_register_8250_port %d\n", ret); + dfluart->line = ret; + dev_set_drvdata(dev, dfluart); + + return 0; +} + +static void dfl_uart_remove(struct dfl_device *dfl_dev) +{ + struct dfl_uart *dfluart = dev_get_drvdata(&dfl_dev->dev); + + if (dfluart->line > 0) + serial8250_unregister_port(dfluart->line); +} + +#define FME_FEATURE_ID_UART 0x24 + +static const struct dfl_device_id dfl_uart_ids[] = { + { FME_ID, FME_FEATURE_ID_UART }, + { } +}; +MODULE_DEVICE_TABLE(dfl, dfl_uart_ids); + +static struct dfl_driver dfl_uart_driver = { + .drv = { + .name = "dfl-uart", + }, + .id_table = dfl_uart_ids, + .probe = dfl_uart_probe, + .remove = dfl_uart_remove, +}; +module_dfl_driver(dfl_uart_driver); + +MODULE_DESCRIPTION("DFL Intel UART driver"); +MODULE_AUTHOR("Intel Corporation"); +MODULE_LICENSE("GPL"); diff --git a/drivers/tty/serial/8250/Kconfig b/drivers/tty/serial/8250/Kconfig index d0b49e15fbf5..5c6497ce5c12 100644 --- a/drivers/tty/serial/8250/Kconfig +++ b/drivers/tty/serial/8250/Kconfig @@ -361,6 +361,15 @@ config SERIAL_8250_BCM2835AUX If unsure, say N. +config SERIAL_8250_DFL + tristate "DFL bus driver for Altera 16550 UART" + depends on SERIAL_8250 && FPGA_DFL + help + This option enables support for a Device Feature List (DFL) bus + driver for the Altera 16650 UART. One or more Altera 16650 UARTs + can be instantiated in a FPGA and then be discovered during + enumeration of the DFL bus. + config SERIAL_8250_FSL bool "Freescale 16550 UART support" if COMPILE_TEST && !(PPC || ARM || ARM64) depends on SERIAL_8250_CONSOLE diff --git a/drivers/tty/serial/8250/Makefile b/drivers/tty/serial/8250/Makefile index bee908f99ea0..32006e0982d1 100644 --- a/drivers/tty/serial/8250/Makefile +++ b/drivers/tty/serial/8250/Makefile @@ -24,6 +24,7 @@ obj-$(CONFIG_SERIAL_8250_CONSOLE) += 8250_early.o obj-$(CONFIG_SERIAL_8250_FOURPORT) += 8250_fourport.o obj-$(CONFIG_SERIAL_8250_ACCENT) += 8250_accent.o obj-$(CONFIG_SERIAL_8250_BOCA) += 8250_boca.o +obj-$(CONFIG_SERIAL_8250_DFL) += 8250_dfl.o obj-$(CONFIG_SERIAL_8250_EXAR_ST16C554) += 8250_exar_st16c554.o obj-$(CONFIG_SERIAL_8250_HUB6) += 8250_hub6.o obj-$(CONFIG_SERIAL_8250_FSL) += 8250_fsl.o diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 7d74ef8d1d20..a17aeccc501e 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -67,6 +67,13 @@ #define DFHv1_PARAM_MSIX_STARTV 0x8 #define DFHv1_PARAM_MSIX_NUMV 0xc +#define DFHv1_PARAM_ID_CLK_FRQ 0x2 +#define DFHv1_PARAM_ID_FIFO_LEN 0x3 + +#define DFHv1_PARAM_ID_REG_LAYOUT 0x4 +#define DFHv1_PARAM_ID_REG_WIDTH GENMASK_ULL(63, 32) +#define DFHv1_PARAM_ID_REG_SHIFT GENMASK_ULL(31, 0) + /** * enum dfl_id_type - define the DFL FIU types */