From patchwork Wed Feb 20 07:43:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 158795 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp4612752jaa; Tue, 19 Feb 2019 23:42:42 -0800 (PST) X-Google-Smtp-Source: AHgI3IYhrTOcG43A4HL4wgKEahZkklxM5QPnKH4BxNIUzvEMvIHl24PfXz+aCtrLrmnCKS7KkjZt X-Received: by 2002:a17:902:6a83:: with SMTP id n3mr9331388plk.313.1550648562642; Tue, 19 Feb 2019 23:42:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550648562; cv=none; d=google.com; s=arc-20160816; b=Ux5F8lmb3BYcrqEjEBmtI5lhmU8SIpckZhSug0PyvCNA3Prm6PTl8uD0zAWJk59K52 bUP2q8GT6cnIvj9h1VZ0VHZp92zBDgR41wBh6P/NTkThJUMrvRzppVmoHyTWFob6A7Ud 3/MsIle+yON9IsjDY/wD7g5C3nrc0DESMh3I4B3dONf9b1QTn3En8rpWB9RS3E4yo9jp 7TvD/WIWn+ZRzNiKZVKcFGpAHe9c18TEajVAPrG65hj2hzTmVtZD+QYoyOvFKm9gmpiX I7P0OxGLJkebQiKILCnv1O7v/jcjzg4TIJymQSOEaUSEo88YAC0bgCIRFY1ozhohs80W EKIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=6DlJUg6IdiLF7gTILSJH+0w7MmsoeqZA9rDoFwZ+iF4=; b=QreNjaIRyhAO27qPvdPLfKySktNgkUHbJyB6GYCKAiEsXp+0kk3L5eK32vZb1yqoIU LxZ8CgfpHRXygjzRRbyqx17qPYHNSzGlLNcBbQEkrvWTpIZw9Tai8BcxnmcxqlG+HApf mO6j2/aPdg+UTXk6wYUD+HENAPXDH2lWAzJRfbLdEzbebNCo6idsAOBuhKyOzpGDAgvW sGSXgE1fwdSLgP/wbaqS23UsmKKjejFdbYgGw3muzbb6dLlyXB6b4NYa24TQvazO3Epw Uw68KNIwHFyAKqBhAlPYrxGjQA2ML05vEBjQw63vn0oL/OSHaGtJAyPnm7R35KM0g1FW VUCA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b17si7464725pls.181.2019.02.19.23.42.42; Tue, 19 Feb 2019 23:42:42 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725883AbfBTHml (ORCPT + 7 others); Wed, 20 Feb 2019 02:42:41 -0500 Received: from mx.socionext.com ([202.248.49.38]:4075 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725379AbfBTHml (ORCPT ); Wed, 20 Feb 2019 02:42:41 -0500 Received: from unknown (HELO iyokan-ex.css.socionext.com) ([172.31.9.54]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:42:39 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by iyokan-ex.css.socionext.com (Postfix) with ESMTP id C727B6117D; Wed, 20 Feb 2019 16:42:39 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:42:39 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 3BCED40368; Wed, 20 Feb 2019 16:42:39 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 23959120459; Wed, 20 Feb 2019 16:42:39 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 1/9] dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram Date: Wed, 20 Feb 2019 16:43:18 +0900 Message-Id: <1550648598-10192-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Milbeaut M10V SoC needs a part of sram for smp, so this adds the M10V sram compatible and binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../devicetree/bindings/sram/milbeaut-smp-sram.txt | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+) create mode 100644 Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt new file mode 100644 index 0000000..194f6a3 --- /dev/null +++ b/Documentation/devicetree/bindings/sram/milbeaut-smp-sram.txt @@ -0,0 +1,24 @@ +Milbeaut SRAM for smp bringup + +Milbeaut SoCs use a part of the sram for the bringup of the secondary cores. +Once they get powered up in the bootloader, they stay at the specific part +of the sram. +Therefore the part needs to be added as the sub-node of mmio-sram. + +Required sub-node properties: +- compatible : should be "socionext,milbeaut-smp-sram" + +Example: + + sram: sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; From patchwork Wed Feb 20 07:43:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 158796 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp4612892jaa; Tue, 19 Feb 2019 23:42:52 -0800 (PST) X-Google-Smtp-Source: AHgI3IbvxDhICcMRHwdN9i48Sl7/QCMkT5/v0bw+Ce1ZvcsPKcmFjkS4Km2Ld8O2y/AdN0PUa+X/ X-Received: by 2002:a17:902:290b:: with SMTP id g11mr6756412plb.269.1550648572180; Tue, 19 Feb 2019 23:42:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550648572; cv=none; d=google.com; s=arc-20160816; b=KVFaMvyyr1z3KavaT1IIJrXrTyiJYZ/cjGjpdCmLGR31XWc2F4Ch1aEFXxOnjbB6Gg 37h9HCQ2ro4bMA5F/qXEx6xHr5M+ApXTNiWT0qYU+E5To3Eyh+eRi/95l9D6VhBDatQL 6FnbSEcsSKbCNsMpAHY4k74jgNmRgnVP7B6rh3OKf7V3xln9tBMG4bfIY9ebw+TmWzqX wCRlVfYaFoyh9G7iy0w2KT/wYJGIcHGMLw3wi3JXXpwkodcjLMw+k4fca/cvZMTf6Rwc NOH14ogdsH2+vyt/zLB+0i+Xtvmp72e9EXkiTv3VtFA9KULOjsIdGSdokvO6Q0GNPcWB aDGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=cra6Gkzbx5OZOvqRw6LwZ4blCHVIjetAMy5avtTHJiA=; b=KeVBUOvAadhUiKYazqhrE5I1jkyDgUXf0PxK0b18CYVR16tOzBzfvAdd8rr1+ScaRg p8N4kID4h/yqIUNH7li3S+yYgMYxwj/pIsYsUhNol2DssnGx5WP28zw3Sa2qBU9Fnu+Q FhVGQt3fdTLZbeR7lZVGP+e4OqGzAo9hMHZ+6bqVHaSNYgOTk0hogHOjky9h9BMlP3Uq 933Ucf+kkdzRv9OqCxT76wb/BLrzr5RqgaXCGHt5kri86/YAs2URMCUhJpOLpoCcC172 dcI/J559HXgKhEpDKUzB1g+3XobDQ4HZAg2PhZWYeuQdpgx2yC3x70hdT3U0YvEVJirt /IoQ== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id 128si17133912pfz.86.2019.02.19.23.42.52; Tue, 19 Feb 2019 23:42:52 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726017AbfBTHmv (ORCPT + 7 others); Wed, 20 Feb 2019 02:42:51 -0500 Received: from mx.socionext.com ([202.248.49.38]:4082 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725379AbfBTHmv (ORCPT ); Wed, 20 Feb 2019 02:42:51 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:42:50 +0900 Received: from mail.mfilter.local (m-filter-2 [10.213.24.62]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 2203E180097; Wed, 20 Feb 2019 16:42:50 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:42:50 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id E0D4E40368; Wed, 20 Feb 2019 16:42:49 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id CBE6F120459; Wed, 20 Feb 2019 16:42:49 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, soc@kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 2/9] dt-bindings: arm: Add SMP enable-method for Milbeaut Date: Wed, 20 Feb 2019 16:43:28 +0900 Message-Id: <1550648608-10343-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a compatible string "socionext,milbeaut-m10v-smp" for Milbeaut M10V to the 32 bit ARM CPU device tree binding. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/arm/cpus.yaml | 1 + 1 file changed, 1 insertion(+) -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 298c17b..365dcf3 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -228,6 +228,7 @@ patternProperties: - renesas,r9a06g032-smp - rockchip,rk3036-smp - rockchip,rk3066-smp + - socionext,milbeaut-m10v-smp - ste,dbx500-smp cpu-release-addr: From patchwork Wed Feb 20 07:43:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 158797 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp4613067jaa; Tue, 19 Feb 2019 23:43:05 -0800 (PST) X-Google-Smtp-Source: AHgI3IYHoV95x68/mMggNn+AQyCNCarEQkZCB3WMjCZelapRNXX4LUjousM8/Jd1a+6bKk4ylEsD X-Received: by 2002:a17:902:29ab:: with SMTP id h40mr35314853plb.238.1550648585087; Tue, 19 Feb 2019 23:43:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550648585; cv=none; d=google.com; s=arc-20160816; b=GdqG4K4gT661a9X/tNT6xYv4up4U1vDmHLuM0S+0F9z3FAvc+FwPfZPvMrbaAwuJRn bRP46hmV8upqk/B/bmKLCz5G3+cUiSMMoL7v4PMbwBm58t0U8WxMybRlAqoAUPUYeHdP f/NywUZM1yg/JEdVMWNHmA9cZQbxmatta5/SNci6R/OLj2nsyM3fxxGSPsmY2bFNz1kO WpDBPSH072MinrOvYu0WFQBLdbWU8MG4I6OXpnYOBnXjPvi4J9l1RmANQ9N8aK4eiFId zpkE/ZHvugdpKkRfqPcnYEcwN1/qtUdWDsyZ7DcNRkGjTYCGeaol0+pImrH0hkvS5Sbz e4AA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=V0WeYn2Uq+1pjg9mgLVZrXoRm23UzSmJ9st2ihyWeUA=; b=REz2s4HUK/r80MdD8HnJvTsoKdAArM+DvQbv1WaCdUxXMAkhLC/KtCxVaiKN85zPJb oZsHc/1waJMtPsH0cGEWR8LiAaKq5gKyqorZtaBxTBo/dEbItxCR9OselU8KcPKQk2m2 niPGAOV6vooCCtg6Dni+lC+Z6sLkp7wX4zD7bFPXzSECnop5UlsNFwHadOPCbmU5B5OM qA9sb5tPsyoIYZ4ONudcc++2TyYjKCdmDb7L8xP8/SfD1+zY/6CS2XMWYq5Qt92df5DX dHUYZriKvVnm6etayndpA2nSCqqLQKv7z6mKaZmEhi2WUqBnM0dqPYolumd+1WW8I50W zMOg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id e67si19863383plb.107.2019.02.19.23.43.04; Tue, 19 Feb 2019 23:43:05 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725779AbfBTHnE (ORCPT + 7 others); Wed, 20 Feb 2019 02:43:04 -0500 Received: from mx.socionext.com ([202.248.49.38]:4087 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725379AbfBTHnE (ORCPT ); Wed, 20 Feb 2019 02:43:04 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:43:02 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 51910180097; Wed, 20 Feb 2019 16:43:02 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:43:02 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id 11AFD1A04E0; Wed, 20 Feb 2019 16:43:02 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id EF891120459; Wed, 20 Feb 2019 16:43:01 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, soc@kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 3/9] dt-bindings: Add documentation for Milbeaut SoCs Date: Wed, 20 Feb 2019 16:43:42 +0900 Message-Id: <1550648622-10541-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This adds a DT binding documentation for the M10V and its evaluation board. Signed-off-by: Sugaya Taichi --- .../bindings/arm/socionext/milbeaut.yaml | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) create mode 100644 Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml -- 1.9.1 diff --git a/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml new file mode 100644 index 0000000..522396f --- /dev/null +++ b/Documentation/devicetree/bindings/arm/socionext/milbeaut.yaml @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/milbeaut.yaml# +$schema: http://devicetree.org/meta-schemas/milbeaut.yaml# + +title: Milbeaut platforms device tree bindings + +maintainers: + - Taichi Sugaya + - Takao Orito + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - socionext,milbeaut-m10v-evb + - const: socionext,sc2000a +... From patchwork Wed Feb 20 07:44:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 158799 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp4613337jaa; Tue, 19 Feb 2019 23:43:25 -0800 (PST) X-Google-Smtp-Source: AHgI3IZ/DnvT8dtSEZprGJoDQZSu5RSXvScqlfg4If2cTPjLXkIeCMQDcftdAtUCuK1Dh7OM0ASG X-Received: by 2002:a17:902:2867:: with SMTP id e94mr35735338plb.264.1550648605843; Tue, 19 Feb 2019 23:43:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550648605; cv=none; d=google.com; s=arc-20160816; b=rB+yyWiNg85N+QehTHSqayKU201wor/OKvZr7P+R5ab18lGnWtBT7Rsn3SyJBHfS5p 6nSkcvePYsayx4O1s2Y08C//5/j3OXytR9dlwURlMheGS5NH37sScaeIssHWEE7GseMF SJhCRZx6fJgS+R+IuSY/QOGNCwIP7Gz8zm3obTs+VRKMEU9NXMA1wkgArlwmlvkzPYxN voRrmhBNNW7nor+Mw/KyxdCL0xlhtYUPpZSXLmO6CInwOse9kf+85bc7FzS5Wl+o/om+ 9z0/V/JmVZfCnh4ADPnEMVPSxg5d88tNOJChuk1fYnq8KOdfk13u0n9owhKpupkpUXjx wpaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=K7UIx7/GIKREL+gm9Whnn5IMWi9A/6HG9N52pVuOFBA=; b=0s2FW0paHy5y/0bp1Ro71tUtkR46nn/TLXp5ZdlkFWOOeiITBKu+VmgSxvzxeZdq2L q06UoBnsJ7EJpkdZ3xX8zp6NyioNEt7FFZSZVaCOGWAZHtKzPLEVeJQigkXvpQdnlcpw BSsyfzfGS+s8zc4rBulwaujqtqJEN7t85itSyRmYHZMZ9xGcTQfozzPL4EExwo5fQWu+ 6F7a6hM03WLNIopPDRu+An9bvNdyi8oruApO4aQN9cF3vZS2lHfNssYREbIbpDlkZpMp +f92EkjqjiJrM/tWGqoi/Dx9k0JvXhnoa7U3ZybVOOabtDYajY9S/0WDMDc5V+vH5vYU ZAZg== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id j132si18067208pfc.84.2019.02.19.23.43.25; Tue, 19 Feb 2019 23:43:25 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725883AbfBTHnZ (ORCPT + 7 others); Wed, 20 Feb 2019 02:43:25 -0500 Received: from mx.socionext.com ([202.248.49.38]:4104 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725379AbfBTHnY (ORCPT ); Wed, 20 Feb 2019 02:43:24 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:43:22 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id 0FEB4180097; Wed, 20 Feb 2019 16:43:23 +0900 (JST) Received: from 172.31.9.51 (172.31.9.51) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:43:23 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by kinkan.css.socionext.com (Postfix) with ESMTP id DD2ED1A04E0; Wed, 20 Feb 2019 16:43:22 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id C3638120459; Wed, 20 Feb 2019 16:43:22 +0900 (JST) From: Sugaya Taichi To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, soc@kernel.org Cc: Daniel Lezcano , Thomas Gleixner , Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 5/9] dt-bindings: timer: Add Milbeaut M10V timer description Date: Wed, 20 Feb 2019 16:44:02 +0900 Message-Id: <1550648642-10802-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings document for Milbeaut M10V timer. Signed-off-by: Sugaya Taichi Reviewed-by: Rob Herring --- .../bindings/timer/socionext,milbeaut-timer.txt | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) create mode 100644 Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt -- 1.9.1 diff --git a/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt new file mode 100644 index 0000000..ac44c4b --- /dev/null +++ b/Documentation/devicetree/bindings/timer/socionext,milbeaut-timer.txt @@ -0,0 +1,17 @@ +Milbeaut SoCs Timer Controller + +Required properties: + +- compatible : should be "socionext,milbeaut-timer". +- reg : Specifies base physical address and size of the registers. +- interrupts : The interrupt of the first timer. +- clocks: phandle to the input clk. + +Example: + +timer { + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20> + interrupts = <0 91 4>; + clocks = <&clk 4>; +}; From patchwork Wed Feb 20 07:44:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sugaya Taichi X-Patchwork-Id: 158802 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp4614046jaa; Tue, 19 Feb 2019 23:44:18 -0800 (PST) X-Google-Smtp-Source: AHgI3IZCDjkjjPcMCGBSHo8rTfHyLf5E+qXWylX3vzju9rzlu8rC47QuxgsdYa2+Ysf1eZwwUx0E X-Received: by 2002:a63:eb56:: with SMTP id b22mr20568821pgk.287.1550648658396; Tue, 19 Feb 2019 23:44:18 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550648658; cv=none; d=google.com; s=arc-20160816; b=nHFj5+OdXUD5Mt3d/O82sPiFSc9nd8Er1EaAvwOGc5Lf7dljwCqsA21jKj3VFnqp69 ewzJbVYSLnC328uIfPh177J7NxrR82uSVpWRucDjj4djItryfJg5KUT+MZyphQ55TrqE TA0Kut/SKOXttNM2ELeh0StuFK1WXASyMi5t3qZCAc4AJc7w2aC4DzV1pz3g3MFrNg8c DEch7x3OaBB3h0V1ucoREqbycPymLX8umTUKhuPLulGuDDs14PTIm56YCWOuk7D9cv4v uh+a6vt35UlUBhnZFLcxmNhDbztas28fP0+3HCBj+wj8FTqUollqCuQiSlKi3qcnijKn XIhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:message-id:date:subject:cc:to:from; bh=OY+ztoZajuLytihlukaHddPZ2VPdYxlcaeLam1fvCJM=; b=FopB64wYAPX3Ax303nVKIWBB6QVpLo0sImyPgRmQ8Ph8lazYki8AYRQgwwDzh5Qz6T AVUX9iD9DB6KF6hQfICLoRYBv5vySL00BClhO3LweQhjktuwnVnziPrHlzEz3JRfpKKO 7DRfme44mL4qDo46n3mHMm/dcRp2Gn3l8Rm+QNsfLdvr5LdkGxLPs1OBU7oel4Uy5q+b EG0riBMQ5JRVnTOcVGbGAglKn7F9N/GcpS7wGcyFxcadQQakr9wMNpfCXaZhNSONczbO JkG9Rcj2iJ4yCJGiugNH2kiOAchmi3KTzWa5ys6B0aWQD3qvlOhfiz1P+ycOPBip/1DW cArw== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id ay7si19523849plb.410.2019.02.19.23.44.18; Tue, 19 Feb 2019 23:44:18 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725830AbfBTHoR (ORCPT + 7 others); Wed, 20 Feb 2019 02:44:17 -0500 Received: from mx.socionext.com ([202.248.49.38]:4138 "EHLO mx.socionext.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725804AbfBTHoR (ORCPT ); Wed, 20 Feb 2019 02:44:17 -0500 Received: from unknown (HELO kinkan-ex.css.socionext.com) ([172.31.9.52]) by mx.socionext.com with ESMTP; 20 Feb 2019 16:44:15 +0900 Received: from mail.mfilter.local (m-filter-1 [10.213.24.61]) by kinkan-ex.css.socionext.com (Postfix) with ESMTP id B0E5E180097; Wed, 20 Feb 2019 16:44:15 +0900 (JST) Received: from 172.31.9.53 (172.31.9.53) by m-FILTER with ESMTP; Wed, 20 Feb 2019 16:44:15 +0900 Received: from yuzu.css.socionext.com (yuzu [172.31.8.45]) by iyokan.css.socionext.com (Postfix) with ESMTP id 2185440368; Wed, 20 Feb 2019 16:44:15 +0900 (JST) Received: from M20VSDK.e01.socionext.com (unknown [10.213.118.34]) by yuzu.css.socionext.com (Postfix) with ESMTP id 0A80F120459; Wed, 20 Feb 2019 16:44:15 +0900 (JST) From: Sugaya Taichi To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, soc@kernel.org Cc: Rob Herring , Mark Rutland , Takao Orito , Kazuhiro Kasai , Shinji Kanematsu , Jassi Brar , Masami Hiramatsu , Sugaya Taichi Subject: [PATCH v3 8/9] ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board Date: Wed, 20 Feb 2019 16:44:53 +0900 Message-Id: <1550648693-11382-1-git-send-email-sugaya.taichi@socionext.com> X-Mailer: git-send-email 1.9.1 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add devicetree for Milbeaut M10V SoC and M10V Evaluation board. Signed-off-by: Sugaya Taichi --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/milbeaut-m10v-evb.dts | 32 +++++++++++ arch/arm/boot/dts/milbeaut-m10v.dtsi | 95 +++++++++++++++++++++++++++++++++ 3 files changed, 128 insertions(+) create mode 100644 arch/arm/boot/dts/milbeaut-m10v-evb.dts create mode 100644 arch/arm/boot/dts/milbeaut-m10v.dtsi -- 1.9.1 diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index bd40148..f697d87 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1233,6 +1233,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7623n-bananapi-bpi-r2.dtb \ mt8127-moose.dtb \ mt8135-evbp1.dtb +dtb-$(CONFIG_ARCH_MILBEAUT) += milbeaut-m10v-evb.dtb dtb-$(CONFIG_ARCH_ZX) += zx296702-ad1.dtb dtb-$(CONFIG_ARCH_ASPEED) += \ aspeed-ast2500-evb.dtb \ diff --git a/arch/arm/boot/dts/milbeaut-m10v-evb.dts b/arch/arm/boot/dts/milbeaut-m10v-evb.dts new file mode 100644 index 0000000..614f60c --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v-evb.dts @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0 +/* Socionext Milbeaut M10V Evaluation Board */ +/dts-v1/; +#include "milbeaut-m10v.dtsi" + +/ { + model = "Socionext M10V EVB"; + compatible = "socionext,milbeaut-m10v-evb", "socionext,sc2000a"; + + aliases { + serial0 = &uart1; + }; + + chosen { + bootargs = "rootwait earlycon"; + stdout-path = "serial0:115200n8"; + }; + + clocks { + uclk40xi: uclk40xi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <40000000>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0x40000000 0x80000000>; + }; + +}; diff --git a/arch/arm/boot/dts/milbeaut-m10v.dtsi b/arch/arm/boot/dts/milbeaut-m10v.dtsi new file mode 100644 index 0000000..aa7c6ca --- /dev/null +++ b/arch/arm/boot/dts/milbeaut-m10v.dtsi @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0 +#include +#include +#include +#include + +/ { + compatible = "socionext,sc2000a"; + interrupt-parent = <&gic>; + #address-cells = <1>; + #size-cells = <1>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "socionext,milbeaut-m10v-smp"; + cpu@f00 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf00>; + }; + cpu@f01 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf01>; + }; + cpu@f02 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf02>; + }; + cpu@f03 { + device_type = "cpu"; + compatible = "arm,cortex-a7"; + reg = <0xf03>; + }; + }; + + timer { /* The Generic Timer */ + compatible = "arm,armv7-timer"; + interrupts = , + , + , + ; + clock-frequency = <40000000>; + always-on; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&gic>; + + gic: interrupt-controller@1d000000 { + compatible = "arm,cortex-a7-gic"; + interrupt-controller; + #interrupt-cells = <3>; + reg = <0x1d001000 0x1000>, + <0x1d002000 0x1000>; /* CPU I/f base and size */ + }; + + timer@1e000050 { /* 32-bit Reload Timers */ + compatible = "socionext,milbeaut-timer"; + reg = <0x1e000050 0x20>; + interrupts = <0 91 4>; + }; + + uart1: serial@1e700010 { /* PE4, PE5 */ + /* Enable this as ttyUSI0 */ + compatible = "socionext,milbeaut-usio-uart"; + reg = <0x1e700010 0x10>; + interrupts = <0 141 0x4>, <0 149 0x4>; + interrupt-names = "rx", "tx"; + }; + + }; + + sram@0 { + compatible = "mmio-sram"; + reg = <0x0 0x10000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x0 0x10000>; + smp-sram@f100 { + compatible = "socionext,milbeaut-smp-sram"; + reg = <0xf100 0x20>; + }; + }; +};