From patchwork Thu Sep 22 08:06:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 608388 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AC65C6FA93 for ; Thu, 22 Sep 2022 08:07:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229905AbiIVIHK (ORCPT ); Thu, 22 Sep 2022 04:07:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45028 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229783AbiIVIHI (ORCPT ); Thu, 22 Sep 2022 04:07:08 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7098EB40DD; Thu, 22 Sep 2022 01:07:07 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,335,1654527600"; d="scan'208";a="133637558" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 22 Sep 2022 17:07:06 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id C259E418538D; Thu, 22 Sep 2022 17:07:06 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda , Rob Herring Subject: [PATCH v6 01/10] dt-bindings: PCI: renesas: Add R-Car Gen4 PCIe Host Date: Thu, 22 Sep 2022 17:06:38 +0900 Message-Id: <20220922080647.3489791-2-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220922080647.3489791-1-yoshihiro.shimoda.uh@renesas.com> References: <20220922080647.3489791-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Document bindings for Renesas R-Car Gen4 and R-Car S4-8 (R8A779F0) PCIe host module. Signed-off-by: Yoshihiro Shimoda Reviewed-by: Rob Herring --- .../bindings/pci/rcar-gen4-pci-host.yaml | 97 +++++++++++++++++++ 1 file changed, 97 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml diff --git a/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml new file mode 100644 index 000000000000..8ac4c2041a81 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/rcar-gen4-pci-host.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Renesas Electronics Corp. +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/rcar-gen4-pci-host.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas R-Car Gen4 PCIe Host + +maintainers: + - Yoshihiro Shimoda + +allOf: + - $ref: snps,dw-pcie.yaml# + +properties: + compatible: + items: + - const: renesas,r8a779f0-pcie # R-Car S4-8 + - const: renesas,rcar-gen4-pcie # R-Car Gen4 + + interrupts: + maxItems: 7 + + interrupt-names: + items: + - const: others + - const: dma + - const: correctable + - const: fatal + - const: nonfatal + - const: lp + - const: vndmsg + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + pcie: pcie@e65d0000 { + compatible = "renesas,r8a779f0-pcie", "renesas,rcar-gen4-pcie"; + reg = <0 0xe65d0000 0 0x3000>, <0 0xe65d3000 0 0x2000>, + <0 0xe65d6200 0 0x0e00>, <0 0xfe000000 0 0x400000>; + reg-names = "dbi", "atu", "app", "config"; + #address-cells = <3>; + #size-cells = <2>; + bus-range = <0x00 0xff>; + device_type = "pci"; + ranges = <0x81000000 0 0x00000000 0 0xfe000000 0 0x00010000 + 0x82000000 0 0x30000000 0 0x30000000 0 0x10000000>; + dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x80000000>; + interrupts = , + , + , + , + , + , + ; + interrupt-names = "others", "dma", "correctable", "fatal", + "nonfatal", "lp", "vndmsg"; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0 0 0 1 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 2 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 3 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH + 0 0 0 4 &gic GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD 624>; + power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>; + resets = <&cpg 624>; + num-lanes = <2>; + snps,enable-cdm-check; + max-link-speed = <2>; + }; + }; From patchwork Thu Sep 22 08:06:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 608387 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D53FAC6FA8B for ; Thu, 22 Sep 2022 08:07:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229865AbiIVIHL (ORCPT ); Thu, 22 Sep 2022 04:07:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45046 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229851AbiIVIHJ (ORCPT ); Thu, 22 Sep 2022 04:07:09 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id B4BAEB40DB; Thu, 22 Sep 2022 01:07:08 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,335,1654527600"; d="scan'208";a="133637561" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 22 Sep 2022 17:07:07 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 050D74185388; Thu, 22 Sep 2022 17:07:07 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v6 03/10] PCI: Add PCI_EXP_LNKCAP_MLW macros Date: Thu, 22 Sep 2022 17:06:40 +0900 Message-Id: <20220922080647.3489791-4-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220922080647.3489791-1-yoshihiro.shimoda.uh@renesas.com> References: <20220922080647.3489791-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add macros defining Maximum Link Width bits in Link Capabilities Register. Signed-off-by: Yoshihiro Shimoda Acked-by: Bjorn Helgaas --- include/uapi/linux/pci_regs.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/include/uapi/linux/pci_regs.h b/include/uapi/linux/pci_regs.h index 57b8e2ffb1dd..06c9e5d0ef33 100644 --- a/include/uapi/linux/pci_regs.h +++ b/include/uapi/linux/pci_regs.h @@ -538,6 +538,12 @@ #define PCI_EXP_LNKCAP_SLS_16_0GB 0x00000004 /* LNKCAP2 SLS Vector bit 3 */ #define PCI_EXP_LNKCAP_SLS_32_0GB 0x00000005 /* LNKCAP2 SLS Vector bit 4 */ #define PCI_EXP_LNKCAP_SLS_64_0GB 0x00000006 /* LNKCAP2 SLS Vector bit 5 */ +#define PCI_EXP_LNKCAP_MLW_X1 0x00000010 /* Maximum Link Width x1 */ +#define PCI_EXP_LNKCAP_MLW_X2 0x00000020 /* Maximum Link Width x2 */ +#define PCI_EXP_LNKCAP_MLW_X4 0x00000040 /* Maximum Link Width x4 */ +#define PCI_EXP_LNKCAP_MLW_X8 0x00000080 /* Maximum Link Width x8 */ +#define PCI_EXP_LNKCAP_MLW_X12 0x000000c0 /* Maximum Link Width x12 */ +#define PCI_EXP_LNKCAP_MLW_X16 0x00000100 /* Maximum Link Width x16 */ #define PCI_EXP_LNKCAP_MLW 0x000003f0 /* Maximum Link Width */ #define PCI_EXP_LNKCAP_ASPMS 0x00000c00 /* ASPM Support */ #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */ From patchwork Thu Sep 22 08:06:42 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 608386 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8494AC6FA9D for ; Thu, 22 Sep 2022 08:07:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229461AbiIVIHN (ORCPT ); Thu, 22 Sep 2022 04:07:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45054 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229902AbiIVIHK (ORCPT ); Thu, 22 Sep 2022 04:07:10 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 160C8B3B0F; Thu, 22 Sep 2022 01:07:08 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,335,1654527600"; d="scan'208";a="133637564" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 22 Sep 2022 17:07:07 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 4C186418538D; Thu, 22 Sep 2022 17:07:07 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v6 05/10] PCI: designware-ep: Add ep_pre_init() callback to dw_pcie_ep_ops Date: Thu, 22 Sep 2022 17:06:42 +0900 Message-Id: <20220922080647.3489791-6-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220922080647.3489791-1-yoshihiro.shimoda.uh@renesas.com> References: <20220922080647.3489791-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some PCIe endpoint controllers need vendor-specific initialization before the common code initialization. Add a new callback function ep_pre_init() for it. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware-ep.c | 3 +++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware-ep.c b/drivers/pci/controller/dwc/pcie-designware-ep.c index ca8f1804ee10..1b7e9e1b8d52 100644 --- a/drivers/pci/controller/dwc/pcie-designware-ep.c +++ b/drivers/pci/controller/dwc/pcie-designware-ep.c @@ -709,6 +709,9 @@ int dw_pcie_ep_init(struct dw_pcie_ep *ep) dw_pcie_version_detect(pci); + if (ep->ops->ep_pre_init) + ep->ops->ep_pre_init(ep); + dw_pcie_iatu_detect(pci); ep->ib_window_map = devm_bitmap_zalloc(dev, pci->num_ib_windows, diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/controller/dwc/pcie-designware.h index b541f653c209..9ed9621a12e4 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -317,6 +317,7 @@ struct dw_pcie_rp { }; struct dw_pcie_ep_ops { + void (*ep_pre_init)(struct dw_pcie_ep *ep); void (*ep_init)(struct dw_pcie_ep *ep); int (*raise_irq)(struct dw_pcie_ep *ep, u8 func_no, enum pci_epc_irq_type type, u16 interrupt_num); From patchwork Thu Sep 22 08:06:44 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 608385 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C52AC6FA92 for ; Thu, 22 Sep 2022 08:07:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230089AbiIVIHP (ORCPT ); Thu, 22 Sep 2022 04:07:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45094 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229977AbiIVIHL (ORCPT ); Thu, 22 Sep 2022 04:07:11 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3AFAEB5E56; Thu, 22 Sep 2022 01:07:10 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,335,1654527600"; d="scan'208";a="133637567" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 22 Sep 2022 17:07:07 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id 7DC714185388; Thu, 22 Sep 2022 17:07:07 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v6 07/10] PCI: dwc: Avoid reading a register to detect whether eDMA exists Date: Thu, 22 Sep 2022 17:06:44 +0900 Message-Id: <20220922080647.3489791-8-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220922080647.3489791-1-yoshihiro.shimoda.uh@renesas.com> References: <20220922080647.3489791-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since reading value of PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL was 0x00000000 on one of SoCs (R-Car S4-8), it cannot find the eDMA. So, directly read the eDMA register if edma.reg_base is not zero. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/pcie-designware.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c index 72f9620a374d..08f91a6bbe4b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -844,8 +844,7 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) { u32 val; - val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); - if (val == 0xFFFFFFFF && pci->edma.reg_base) { + if (pci->edma.reg_base) { pci->edma.mf = EDMA_MF_EDMA_UNROLL; val = dw_pcie_readl_dma(pci, PCIE_DMA_CTRL); @@ -853,6 +852,7 @@ static int dw_pcie_edma_find_chip(struct dw_pcie *pci) pci->edma.mf = EDMA_MF_EDMA_LEGACY; pci->edma.reg_base = pci->dbi_base + PCIE_DMA_VIEWPORT_BASE; + val = dw_pcie_readl_dbi(pci, PCIE_DMA_VIEWPORT_BASE + PCIE_DMA_CTRL); } else { return -ENODEV; } From patchwork Thu Sep 22 08:06:46 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yoshihiro Shimoda X-Patchwork-Id: 608384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DBF8DC6FA95 for ; Thu, 22 Sep 2022 08:07:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230098AbiIVIHQ (ORCPT ); Thu, 22 Sep 2022 04:07:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45106 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230020AbiIVIHM (ORCPT ); Thu, 22 Sep 2022 04:07:12 -0400 Received: from relmlie5.idc.renesas.com (relmlor1.renesas.com [210.160.252.171]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 4C13EB40D5; Thu, 22 Sep 2022 01:07:10 -0700 (PDT) X-IronPort-AV: E=Sophos;i="5.93,335,1654527600"; d="scan'208";a="133637571" Received: from unknown (HELO relmlir6.idc.renesas.com) ([10.200.68.152]) by relmlie5.idc.renesas.com with ESMTP; 22 Sep 2022 17:07:07 +0900 Received: from localhost.localdomain (unknown [10.166.15.32]) by relmlir6.idc.renesas.com (Postfix) with ESMTP id BDB5E41C7965; Thu, 22 Sep 2022 17:07:07 +0900 (JST) From: Yoshihiro Shimoda To: lpieralisi@kernel.org, robh+dt@kernel.org, kw@linux.com, bhelgaas@google.com, krzk+dt@kernel.org Cc: marek.vasut+renesas@gmail.com, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Yoshihiro Shimoda Subject: [PATCH v6 09/10] PCI: rcar-gen4-ep: Add R-Car Gen4 PCIe Endpoint support Date: Thu, 22 Sep 2022 17:06:46 +0900 Message-Id: <20220922080647.3489791-10-yoshihiro.shimoda.uh@renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220922080647.3489791-1-yoshihiro.shimoda.uh@renesas.com> References: <20220922080647.3489791-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add R-Car Gen4 PCIe Endpoint support. This controller is based on Synopsys DesignWare PCIe. Signed-off-by: Yoshihiro Shimoda --- drivers/pci/controller/dwc/Kconfig | 9 + drivers/pci/controller/dwc/Makefile | 2 + .../pci/controller/dwc/pcie-rcar-gen4-ep.c | 182 ++++++++++++++++++ 3 files changed, 193 insertions(+) create mode 100644 drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dwc/Kconfig index 99717b0f4e50..4889bde3471b 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -402,4 +402,13 @@ config PCIE_RCAR_GEN4 Say Y here if you want PCIe host controller support on R-Car Gen4 SoCs. This uses the DesignWare core. +config PCIE_RCAR_GEN4_EP + tristate "Renesas R-Car Gen4 PCIe Endpoint controller" + depends on ARCH_RENESAS || COMPILE_TEST + depends on PCI_ENDPOINT + select PCIE_DW_EP + help + Say Y here if you want PCIe endpoint controller support on R-Car Gen4 + SoCs. This uses the DesignWare core. + endmenu diff --git a/drivers/pci/controller/dwc/Makefile b/drivers/pci/controller/dwc/Makefile index 486cf706b53d..0fb0bde26ac4 100644 --- a/drivers/pci/controller/dwc/Makefile +++ b/drivers/pci/controller/dwc/Makefile @@ -28,6 +28,8 @@ obj-$(CONFIG_PCIE_UNIPHIER_EP) += pcie-uniphier-ep.o obj-$(CONFIG_PCIE_VISCONTI_HOST) += pcie-visconti.o pcie-rcar-gen4-host-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-host.o obj-$(CONFIG_PCIE_RCAR_GEN4) += pcie-rcar-gen4-host-drv.o +pcie-rcar-gen4-ep-drv-objs := pcie-rcar-gen4.o pcie-rcar-gen4-ep.o +obj-$(CONFIG_PCIE_RCAR_GEN4_EP) += pcie-rcar-gen4-ep-drv.o # The following drivers are for devices that use the generic ACPI # pci_root.c driver but don't support standard ECAM config access. diff --git a/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c new file mode 100644 index 000000000000..79677cf40ebf --- /dev/null +++ b/drivers/pci/controller/dwc/pcie-rcar-gen4-ep.c @@ -0,0 +1,182 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe Endpoint driver for Renesas R-Car Gen4 Series SoCs + * Copyright (C) 2022 Renesas Electronics Corporation + */ + +#include +#include +#include +#include +#include + +#include "pcie-rcar-gen4.h" +#include "pcie-designware.h" + +/* Configuration */ +#define PCICONF3 0x000c +#define MULTI_FUNC BIT(23) + +static void rcar_gen4_pcie_ep_pre_init(struct dw_pcie_ep *ep) +{ + struct dw_pcie *dw = to_dw_pcie_from_ep(ep); + struct rcar_gen4_pcie *rcar = to_rcar_gen4_pcie(dw); + int val; + + rcar_gen4_pcie_set_device_type(rcar, false, dw->num_lanes); + + dw_pcie_dbi_ro_wr_en(dw); + + /* Single function */ + val = dw_pcie_readl_dbi(dw, PCICONF3); + val &= ~MULTI_FUNC; + dw_pcie_writel_dbi(dw, PCICONF3, val); + + rcar_gen4_pcie_disable_bar(dw, BAR2MASKF); + rcar_gen4_pcie_disable_bar(dw, BAR3MASKF); + + rcar_gen4_pcie_set_max_link_width(dw, dw->num_lanes); + + dw_pcie_dbi_ro_wr_dis(dw); +} + +static int rcar_gen4_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no, + enum pci_epc_irq_type type, + u16 interrupt_num) +{ + struct dw_pcie *dw = to_dw_pcie_from_ep(ep); + + switch (type) { + case PCI_EPC_IRQ_LEGACY: + return dw_pcie_ep_raise_legacy_irq(ep, func_no); + case PCI_EPC_IRQ_MSI: + return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num); + default: + dev_err(dw->dev, "UNKNOWN IRQ type\n"); + return -EINVAL; + } + + return 0; +} + +static const struct pci_epc_features rcar_gen4_pcie_epc_features = { + .linkup_notifier = false, + .msi_capable = true, + .msix_capable = false, + .align = SZ_1M, +}; + +static const struct pci_epc_features* +rcar_gen4_pcie_ep_get_features(struct dw_pcie_ep *ep) +{ + return &rcar_gen4_pcie_epc_features; +} + +static const struct dw_pcie_ep_ops pcie_ep_ops = { + .ep_pre_init = rcar_gen4_pcie_ep_pre_init, + .raise_irq = rcar_gen4_pcie_ep_raise_irq, + .get_features = rcar_gen4_pcie_ep_get_features, +}; + +static int rcar_gen4_add_pcie_ep(struct rcar_gen4_pcie *rcar, + struct platform_device *pdev) +{ + struct dw_pcie *dw = &rcar->dw; + struct dw_pcie_ep *ep; + int ret; + + ep = &dw->ep; + ep->ops = &pcie_ep_ops; + ep->reset_all_bars = true; + + ret = dw_pcie_ep_init(ep); + if (ret) { + dev_err(&pdev->dev, "failed to initialize endpoint\n"); + return ret; + } + + dw->ops->start_link(dw); + + return 0; +} + +static void rcar_gen4_remove_pcie_ep(struct rcar_gen4_pcie *rcar) +{ + dw_pcie_ep_exit(&rcar->dw.ep); +} + +static int rcar_gen4_pcie_ep_get_resources(struct rcar_gen4_pcie *rcar, + struct platform_device *pdev) +{ + struct dw_pcie *dw = &rcar->dw; + struct device *dev = dw->dev; + + /* Renesas-specific registers */ + rcar->base = devm_platform_ioremap_resource_byname(pdev, "appl"); + if (IS_ERR(rcar->base)) + return PTR_ERR(rcar->base); + + return rcar_gen4_pcie_devm_reset_get(rcar, dev); +} + +static int rcar_gen4_pcie_ep_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct rcar_gen4_pcie *rcar; + int err; + + rcar = rcar_gen4_pcie_devm_alloc(dev); + if (!rcar) + return -ENOMEM; + + err = rcar_gen4_pcie_ep_get_resources(rcar, pdev); + if (err < 0) { + dev_err(dev, "failed to request resource: %d\n", err); + return err; + } + + platform_set_drvdata(pdev, rcar); + + err = rcar_gen4_pcie_prepare(rcar); + if (err < 0) + return err; + + err = rcar_gen4_add_pcie_ep(rcar, pdev); + if (err < 0) + goto err_add; + + return 0; + +err_add: + rcar_gen4_pcie_unprepare(rcar); + + return err; +} + +static int rcar_gen4_pcie_ep_remove(struct platform_device *pdev) +{ + struct rcar_gen4_pcie *rcar = platform_get_drvdata(pdev); + + rcar_gen4_remove_pcie_ep(rcar); + rcar_gen4_pcie_unprepare(rcar); + + return 0; +} + +static const struct of_device_id rcar_gen4_pcie_of_match[] = { + { .compatible = "renesas,rcar-gen4-pcie-ep", }, + {}, +}; + +static struct platform_driver rcar_gen4_pcie_ep_driver = { + .driver = { + .name = "pcie-rcar-gen4-ep", + .of_match_table = rcar_gen4_pcie_of_match, + }, + .probe = rcar_gen4_pcie_ep_probe, + .remove = rcar_gen4_pcie_ep_remove, +}; +module_platform_driver(rcar_gen4_pcie_ep_driver); + +MODULE_DESCRIPTION("Renesas R-Car Gen4 PCIe endpoint controller driver"); +MODULE_LICENSE("GPL");