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Tue, 20 Sep 2022 00:23:04 -0500 From: Piyush Mehta To: , , , , CC: , , , , , Piyush Mehta , Krzysztof Kozlowski Subject: [PATCH V3 1/2] dt-bindings: usb: snps,dwc3: Add 'snps,resume-hs-terminations' quirk Date: Tue, 20 Sep 2022 10:52:34 +0530 Message-ID: <20220920052235.194272-2-piyush.mehta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220920052235.194272-1-piyush.mehta@amd.com> References: <20220920052235.194272-1-piyush.mehta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT032:EE_|DM4PR12MB5295:EE_ X-MS-Office365-Filtering-Correlation-Id: a0562285-9b86-48ae-3216-08da9ac834c1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: 4vAdOPaiXumTcGwI4YdgR9pwgkn3Q0c0BymXOSjY7BtVPTFKcddWzFg/P7xcAsTDipEJj8yGLp9755ZZzVWEmY571ne/D7baFqdqCxuvh87uAXmnlrJi1U9qssCcHl4EwlsQvcnyBCagm4EUXZoGpYoX+AiT9Anf/H7y29zg/wBhvPVtNWmz3BDQwCvl0wB8Oo11CCbf2I7F8YIt9pVjpEFOIefMyEvTZ/160+VydSF+q8r+nvTY/Ff9kN9WPf+ccBUYPVGDNh9SEvKN70p1SezzTEEAt5pJQNsGZ6X+Uv0EJVP2LCWFvcc3W/irI+dClz4JMfKzZ5LWwF0pj8x9GtLKoqs0qPawSQMAocfFdDuJecP1vH8jcJKY0HgcDUldg+RRueTZ/K5/oyGT7aDbh3D6vLKR+sR4lkKLA6cif8O41LJrxY78Y/yBEsFnDUUT4t2dnT54E8BJTCCf65tKEq24Qs8SNUsVJ9lIaNv5oabpHkk1UgynHJl94IQLMK0v+Mut5e7OMuQQGeajLqXcIRWcCa8CgHzVjKNOKI2r03iiZZpNUqs4JGjcxli0iGjHKpVfGnbwQN8n+Fv84vunF47oi26P7J9tD9bOKj/58P5jx7UPtTCi1r3Hfpio+2uAX0iVCac5RUMadenIN/gWwVY2lAMj4U3Ag91dRGPV6k5dQZgk8rT6jUkgvKiEOQr3au/EuLtQAgE9BSnNSBHBpzm6j4H90pNFAOdviEPEAHRqWjUlgDE66eNdxhj2jjnIgRYaE4EpA5XNhv85QyiM4LsIrmRNIm0M5ulhXvQ+9My948gz5vI7u9bRlvOkMkWtY3c1GUs9BVUTBMfWb57c+18z5axw9uiG/WSyaPkNesY9fHV+DPgFvgKrLR6adc84 X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(136003)(39860400002)(346002)(376002)(396003)(451199015)(36840700001)(40470700004)(46966006)(426003)(1076003)(82310400005)(336012)(356005)(2616005)(186003)(8936002)(2906002)(40480700001)(26005)(81166007)(54906003)(40460700003)(478600001)(316002)(110136005)(41300700001)(70586007)(70206006)(966005)(6666004)(36756003)(4326008)(8676002)(86362001)(44832011)(36860700001)(5660300002)(83380400001)(47076005)(82740400003)(36900700001); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Sep 2022 05:23:09.3528 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a0562285-9b86-48ae-3216-08da9ac834c1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT032.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5295 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Add a new 'snps,resume-hs-terminations' DT quirk to dwc3 core to resolved issue of CRC failed error. On the resume path, U3/U2 exit controller fails to send proper CRC checksum in CRC5 field. As result Transaction Error is generated. Enabling bit 10 of GUCTL1 will correct this problem. When this bit is set to '1', the UTMI/ULPI opmode will be changed to "normal" along with HS terminations and term/xcvr select signals after EOR. This option is to support certain legacy UTMI/ULPI PHYs. Signed-off-by: Piyush Mehta Acked-by: Krzysztof Kozlowski --- Changes in V3: - Addressed Krzysztof Kozlowski review comments: - Switch to amd.com with amd SoB and ownership. - Added Krzysztof Ack for DT patch Link: https://lore.kernel.org/all/6499fa0e-3e07-85b4-0800-849db7c2593b@linaro.org/ Changes in V2: - Addressed Krzysztof Kozlowski review comments: - Update the quirk name and No underscores in properties. - Modified the quirk description. Link: https://lore.kernel.org/all/e15168ac-b5a1-0c15-cfb3-34fb518e737f@linaro.org/ --- Documentation/devicetree/bindings/usb/snps,dwc3.yaml | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml index 1779d08ba1c0..6f9107fca6f1 100644 --- a/Documentation/devicetree/bindings/usb/snps,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/snps,dwc3.yaml @@ -234,6 +234,13 @@ properties: avoid -EPROTO errors with usbhid on some devices (Hikey 970). type: boolean + snps,resume-hs-terminations: + description: + Fix the issue of HS terminations CRC error on resume by enabling this + quirk. When set, all the termsel, xcvrsel, opmode becomes 0 during end + of resume. This option is to support certain legacy ULPI PHYs. + type: boolean + snps,is-utmi-l1-suspend: description: True when DWC3 asserts output signal utmi_l1_suspend_n, false when From patchwork Tue Sep 20 05:22:35 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Mehta, Piyush" X-Patchwork-Id: 608201 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9265AC6FA93 for ; Tue, 20 Sep 2022 05:24:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229919AbiITFYX (ORCPT ); Tue, 20 Sep 2022 01:24:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230172AbiITFYD (ORCPT ); Tue, 20 Sep 2022 01:24:03 -0400 Received: from NAM12-DM6-obe.outbound.protection.outlook.com (mail-dm6nam12on2069.outbound.protection.outlook.com [40.107.243.69]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 28C5054C91; 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Tue, 20 Sep 2022 00:23:12 -0500 Received: from xhdnavam40.xilinx.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server id 15.1.2375.28 via Frontend Transport; Tue, 20 Sep 2022 00:23:08 -0500 From: Piyush Mehta To: , , , , CC: , , , , , Piyush Mehta Subject: [PATCH V3 2/2] usb: dwc3: core: Enable GUCTL1 bit 10 for fixing termination error after resume bug Date: Tue, 20 Sep 2022 10:52:35 +0530 Message-ID: <20220920052235.194272-3-piyush.mehta@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220920052235.194272-1-piyush.mehta@amd.com> References: <20220920052235.194272-1-piyush.mehta@amd.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT054:EE_|BY5PR12MB5015:EE_ X-MS-Office365-Filtering-Correlation-Id: 035c3baf-3c28-43ce-ea5d-08da9ac8372c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: ExIIJFZYmqB7OdL2yy3Gso7QztqJuTjYu+7nY7wpLOY3JryJIEgZXy12ZN1odITDhlgqO9iCpP1LkpSpcQf7/osJob225X0EFoRihP5gdwViBpUMAc4GBVoTAlOPaO+caCjvvvPNsnZAYmbS3ovsj1ohKs7bQpGeEmziiAZB6z1tPo9D66/R6xHGTSEc/k+HAW9J7Qu/ZITf6zKEwJwC24KA3gPYN0k1MinM9ieRIvWuRMRgpecwsytQgt9V9M5Y9qHQzB2R5h7Pd/koyF2nyy8UsRlHYHXSvl8q+MyJV51P+KhXVt61be8/Ng9pqZ1lVTPovPokwq6g6Dgmxd36P4KvmkWne+hcG05W10HQZRSdhDqTATg28niu7JCTSzi2hMC51NZ9RnzQabD2u7vMKidoJpPUv60nYsJDHJauM+wo0hYNLac5V4Edd1os6lLsYOPiEU5/UhjHl75nBDLCDOMl+I+bqJajV3/ih3bz9mfFpQqYS/TTi8Ai9AvCZbs32rC8KjiIZhMqGo4qWocBoB6RKGao8bmkjNm528ezWRVyY0tk7WgoVbZ1l9CFkWsccwxAiD/xWgCQDAfybTzxrAD8oAOVbjjOOidRFEL1hoTZVqJPq18ZUkToP7PytClaL4h7jRoyRLdTXcGkZ1iopTyENmaPwarR8L/sFHffhRea9F4y1IIXpQrRADr+PiLeWjnnkno+nNjTeWLqeOwp/E9XKu/j0adlPiWJ6iLcMb3XZC0/XHsj9zgwbA7Ggj99gagPR8S6AhTH20pvs/s7f9Uq95rToLQumSrD6JwE+9FP0iMmuxLwggAl290TOetF X-Forefront-Antispam-Report: CIP:165.204.84.17; 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Because of this behavior Transaction Error is generated, resulting in reset and re-enumeration of usb device attached. Enabling chicken bit 10 of GUCTL1 will correct this problem. When this bit is set to '1', the UTMI/ULPI opmode will be changed to "normal" along with HS terminations, term, and xcvr signals after EOR. This option is to support certain legacy UTMI/ULPI PHYs. Added "snps,resume-hs-terminations" quirk to resolved the above issue. Signed-off-by: Piyush Mehta --- drivers/usb/dwc3/core.c | 17 +++++++++++++++++ drivers/usb/dwc3/core.h | 4 ++++ 2 files changed, 21 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 8c8e32651473..7223074be6be 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -1180,6 +1180,21 @@ static int dwc3_core_init(struct dwc3 *dwc) dwc3_writel(dwc->regs, DWC3_GUCTL2, reg); } + /* + * When configured in HOST mode, after issuing U3/L2 exit controller + * fails to send proper CRC checksum in CRC5 feild. Because of this + * behaviour Transaction Error is generated, resulting in reset and + * re-enumeration of usb device attached. All the termsel, xcvrsel, + * opmode becomes 0 during end of resume. Enabling bit 10 of GUCTL1 + * will correct this problem. This option is to support certain + * legacy ULPI PHYs. + */ + if (dwc->resume_hs_terminations) { + reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); + reg |= DWC3_GUCTL1_RESUME_OPMODE_HS_HOST; + dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); + } + if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) { reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); @@ -1523,6 +1538,8 @@ static void dwc3_get_properties(struct dwc3 *dwc) "snps,dis-del-phy-power-chg-quirk"); dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev, "snps,dis-tx-ipgap-linecheck-quirk"); + dwc->resume_hs_terminations = device_property_read_bool(dev, + "snps,resume-hs-terminations"); dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev, "snps,parkmode-disable-ss-quirk"); diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 4fe4287dc934..bc5ac4d0d61f 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -263,6 +263,7 @@ #define DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK BIT(26) #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) #define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) +#define DWC3_GUCTL1_RESUME_OPMODE_HS_HOST BIT(10) /* Global Status Register */ #define DWC3_GSTS_OTG_IP BIT(10) @@ -1096,6 +1097,8 @@ struct dwc3_scratchpad_array { * change quirk. * @dis_tx_ipgap_linecheck_quirk: set if we disable u2mac linestate * check during HS transmit. + * @resume-hs-terminations: Set if we enable quirk for fixing improper crc + * generation after resume from suspend. * @parkmode_disable_ss_quirk: set if we need to disable all SuperSpeed * instances in park mode. * @tx_de_emphasis_quirk: set if we enable Tx de-emphasis quirk @@ -1311,6 +1314,7 @@ struct dwc3 { unsigned dis_u2_freeclk_exists_quirk:1; unsigned dis_del_phy_power_chg_quirk:1; unsigned dis_tx_ipgap_linecheck_quirk:1; + unsigned resume_hs_terminations:1; unsigned parkmode_disable_ss_quirk:1; unsigned tx_de_emphasis_quirk:1;