From patchwork Tue Sep 20 18:48:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 607781 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F505C54EE9 for ; Tue, 20 Sep 2022 18:50:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230517AbiITSuR (ORCPT ); Tue, 20 Sep 2022 14:50:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56222 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230270AbiITSuQ (ORCPT ); Tue, 20 Sep 2022 14:50:16 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93862606A6; Tue, 20 Sep 2022 11:50:13 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id e16so5945808wrx.7; Tue, 20 Sep 2022 11:50:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=PvYfwd2nPuMUYkxu6YqzbYYwaZvTVZWZRcfAOAojG1g=; b=XvqfCxUWw7Ob93m1pCW+Yo3ZDVF8JTbPLKM+69O0aP8qjXz8rQoXy9zm9mAboPkuDs wFptWyweOJhrxbhrsloM2xwYI2b8pGPhzbIxJKL9X0rvGNf3z/VJ5eD7WQyzGxSran5c fQlS67sZZUYeAtrT5VYuopmyaAASMcZ7EPQPoNv0ugP8hxMAE7OCuM3Dlkq1ocROp3VL d2Dn8OGyXQTMi2gbGPBg5lgtDlwyDqdO05ohE9Hv1gdkt7khCjd+3Xwiv2Enr6C8lf9r mR3vfwHlK6h837Oe8tchU7jJLWdFYrhsK2G8MW+yQbzVuS20p/1LltM5U+1vwCo/VQI/ rRxw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=PvYfwd2nPuMUYkxu6YqzbYYwaZvTVZWZRcfAOAojG1g=; b=uN95kl+qSXbSgVwsEWj5ziBLxejndbGWCqOeXYC+WEZ/WbvuG9ph4cJMoHkVdKn3oc 5/WTkkI72i5MBeTQ6ozSMxXaoTtgcYtPGykVAeAr1Przl0d6s25XuF8oE1dPXOVxXXol FIdwdWl1+QWuMEFWUCL/6spNGaJe/6DC/EcWge6yePk7wLvgQ4anKWOsneK8Y9HAd4gd QKF3aAjEHnGxrnirE/UG+9XwRwAn4mC62QklOJYUEGjaT4grxIdXIWe6G6j1ylDEnVYO QghUnPDiIL4dZXCzzXQCkWGbM8S9pz8XE19RgOFKhppoT0HidbOVD9Q0zY3eiLyrBMiP AtpA== X-Gm-Message-State: ACrzQf0ypy2nChYlVHGagVu05aLZYxAD1ctGtqABbtxy0HCIOi7wPPjh Zpg/AkLYoixCfgl0G+4jRLw= X-Google-Smtp-Source: AMsMyM76OQSXwK5sY+9A35aBFOAgfcDsYqF2PChfuGlLLSZuTZZv7QbLJ2jvApEs1oRsa52efQYETQ== X-Received: by 2002:a5d:598f:0:b0:22a:f77e:869a with SMTP id n15-20020a5d598f000000b0022af77e869amr9719128wri.357.1663699811661; Tue, 20 Sep 2022 11:50:11 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:e9a4:d6c9:505d:20d0]) by smtp.gmail.com with ESMTPSA id cc4-20020a5d5c04000000b00228de351fc0sm582722wrb.38.2022.09.20.11.50.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Sep 2022 11:50:11 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Conor Dooley Cc: Heiko Stuebner , Heinrich Schuchardt , Atish Patra , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v4 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Date: Tue, 20 Sep 2022 19:48:57 +0100 Message-Id: <20220920184904.90495-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. In preparation to add support for RZ/Five SoC add the Andes AX45MP core to the list. More details about Andes AX45MP core can be found here: [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v3 -> v4 * No change v2 -> v3 * Included RB tag from Geert v1 -> v2 * Included ack from Krzysztof --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 2a1c5ae5b0aa..1681767790c5 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -27,6 +27,7 @@ properties: oneOf: - items: - enum: + - andestech,ax45mp - canaan,k210 - sifive,bullet0 - sifive,e5 From patchwork Tue Sep 20 18:48:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 607780 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64DB1C6FA93 for ; Tue, 20 Sep 2022 18:50:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231191AbiITSuV (ORCPT ); Tue, 20 Sep 2022 14:50:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56332 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230522AbiITSuR (ORCPT ); Tue, 20 Sep 2022 14:50:17 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A84B1606AA; Tue, 20 Sep 2022 11:50:14 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id g3so5874926wrq.13; Tue, 20 Sep 2022 11:50:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=PIml5h9yfGZM8hFj0DM2cpSK5N9+Jc9EevGrYn1++vQ=; b=LR7YtcMxhe3P0sEoEbJcH+IkBqrOkuc6o8e6zFaIH3s6hCMkvbaoX0KeIil8ejenWE jddSYjFaJ1eXffm98pgu4B8UsyZ3805SytCXEvlU6HFY19IQ7wytoXQTYtdMNXR4Y4Uu UF5heYpMAZWUxTsPfNc6mi7iecR8SCO5gWsBBj9bx6hDhVa7XaVvwM+PjpYm+xPqH5gS pYjljuCUtbgOc9W5YnW7gRo+HwpDSbwKNODmxr3vhnfntwpf4hKvY30l7Wu7TuprisUh i4Kd079fwNxBqMniHL9S35KyW5pU6OA999s+81FLD1xOQhNKhq2NDzXlh2ISaDAE5aJL 9c8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=PIml5h9yfGZM8hFj0DM2cpSK5N9+Jc9EevGrYn1++vQ=; b=1Al1+3pVbppgplZJxcTLvoN+A87kHkMBDLTN2A4wx3isomLPZqGkWiU+TURItWWui6 6eQJgRJg3wSNLgJGCM+kdZPvcmUlepgtWHKV/CtZ/qQAj6F3rJybSep4nRxwAIQT68PF YjUGvpge+tAjBelZBM1d+eiGnb2pz9uOMNMzxHjZAJpX8TJZmWTnDGoTbQpHPFV56gI9 5sgnYflghRW9hrzmYGhakCKMlzHcu3J/qTOHHQtaW/qESZjXLimOeHLGsl9x4OQu+8HZ g/1rtdw/gtLS4CcOjqi/baGcXSbCrvRoLC8uVUUzYJfmBmkwTJUd4ALAazbp+BlLAt3t AKLw== X-Gm-Message-State: ACrzQf2zb0XsJimLnKaQateW/WhqPn3W2kleXZNiTDo6BBASFxUeeCYo BHneEQWYa2cpi7+XTDgHAx4= X-Google-Smtp-Source: AMsMyM5YuEsIkz/ZbwCy+LfECoAJ6wOTpSpMRW2lh6ErlpsbZS7wKSEoBVSfZwsTS9ij5ivNi33RTg== X-Received: by 2002:a05:6000:1689:b0:22a:a66d:1f37 with SMTP id y9-20020a056000168900b0022aa66d1f37mr15201522wrd.197.1663699812700; Tue, 20 Sep 2022 11:50:12 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:e9a4:d6c9:505d:20d0]) by smtp.gmail.com with ESMTPSA id cc4-20020a5d5c04000000b00228de351fc0sm582722wrb.38.2022.09.20.11.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Sep 2022 11:50:12 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Conor Dooley Cc: Heiko Stuebner , Heinrich Schuchardt , Atish Patra , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v4 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Date: Tue, 20 Sep 2022 19:48:58 +0100 Message-Id: <20220920184904.90495-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Document Renesas RZ/Five (R9A07G043) SoC. More info about RZ/Five SoC: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v3 -> v4 * No change v2 -> v3 * Dropped "(RISC-V core)" comment * Included ACK and RB tags v1 -> v2 * New patch --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 07c5e6ebd5a0..2789022b52eb 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -431,11 +431,12 @@ properties: - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) - const: renesas,r9a06g032 - - description: RZ/G2UL (R9A07G043) + - description: RZ/Five and RZ/G2UL (R9A07G043) items: - enum: - renesas,smarc-evk # SMARC EVK - enum: + - renesas,r9a07g043f01 # RZ/Five - renesas,r9a07g043u11 # RZ/G2UL Type-1 - renesas,r9a07g043u12 # RZ/G2UL Type-2 - const: renesas,r9a07g043 From patchwork Tue Sep 20 18:49:02 2022 Content-Type: text/plain; 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Tue, 20 Sep 2022 11:50:16 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:e9a4:d6c9:505d:20d0]) by smtp.gmail.com with ESMTPSA id cc4-20020a5d5c04000000b00228de351fc0sm582722wrb.38.2022.09.20.11.50.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Sep 2022 11:50:16 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Conor Dooley Cc: Heiko Stuebner , Heinrich Schuchardt , Atish Patra , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v4 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Date: Tue, 20 Sep 2022 19:49:02 +0100 Message-Id: <20220920184904.90495-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Enable the minimal blocks required for booting the Renesas RZ/Five SMARC EVK with initramfs. Below are the which are enabled: - CPG - CPU0 - DDR (memory regions) - PINCTRL - PLIC - SCIF0 As we are reusing the RZ/G2UL SMARC SoM [0] and carrier [1] board DTSIs which enables almost all the blocks supported by the RZ/G2UL SoC and whereas on RZ/Five SoC we will be gradually adding the blocks hence the aliases for ETH and I2C are deleted as support for these blocks is not yet enabled on RZ/Five SoC. [0] arch/arm64/boot/dts/renesas/rzg2ul-smarc-som.dtsi [1] arch/arm64/boot/dts/renesas/rzg2ul-smarc.dtsi Signed-off-by: Lad Prabhakar --- v3 -> v4 * Dropped deleting place holder nodes * Updated SW1 settings comment * Update commit message v2 -> v3 * Dropped RB tags from Conor and Geert * Now re-using the SoM and carrier board DTS/I from RZ/G2UL v1 -> v2 * New patch --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/Makefile | 2 ++ .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++++++++++++++++++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 19 +++++++++++++ arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 15 +++++++++++ 5 files changed, 64 insertions(+) create mode 100644 arch/riscv/boot/dts/renesas/Makefile create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..b0ff5fbabb0c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -3,5 +3,6 @@ subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip +subdir-y += renesas obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile new file mode 100644 index 000000000000..2d3f5751a649 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts new file mode 100644 index 000000000000..487d0d5e6d2e --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; + +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) + * Please change below macros according to SW1 setting on the SoM + */ +#define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 + +#include "r9a07g043.dtsi" +#include "rzfive-smarc-som.dtsi" +#include "rzfive-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g043f01"; + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043"; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi new file mode 100644 index 000000000000..d8168eb920ab --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK SOM + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include + +/ { + aliases { + /delete-property/ ethernet0; + /delete-property/ ethernet1; + }; + + chosen { + bootargs = "ignore_loglevel"; + }; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi new file mode 100644 index 000000000000..6f44a6946897 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK carrier board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include + +/ { + aliases { + /delete-property/ i2c0; + /delete-property/ i2c1; + }; +}; From patchwork Tue Sep 20 18:49:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Lad, Prabhakar" X-Patchwork-Id: 607778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1CCC3C6FA94 for ; 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Tue, 20 Sep 2022 11:50:17 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Geert Uytterhoeven , Magnus Damm , Conor Dooley Cc: Heiko Stuebner , Heinrich Schuchardt , Atish Patra , devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v4 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Date: Tue, 20 Sep 2022 19:49:03 +0100 Message-Id: <20220920184904.90495-10-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220920184904.90495-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Add RISC-V architecture as part of ARM/Renesas architecture, as they have the same maintainers, use the same development collaboration infrastructure, and share many files. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v3 -> v4 * Included RB tag from Geert v2 -> v3 * Merged as part of ARM v1 -> v2 * New patch --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 48c5a152f743..fbf507cd3f41 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2671,7 +2671,7 @@ F: arch/arm/boot/dts/rtd* F: arch/arm/mach-realtek/ F: arch/arm64/boot/dts/realtek/ -ARM/RENESAS ARCHITECTURE +ARM/RISC-V/RENESAS ARCHITECTURE M: Geert Uytterhoeven M: Magnus Damm L: linux-renesas-soc@vger.kernel.org @@ -2692,6 +2692,7 @@ F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S F: arch/arm/mach-shmobile/ F: arch/arm64/boot/dts/renesas/ +F: arch/riscv/boot/dts/renesas/ F: drivers/soc/renesas/ F: include/linux/soc/renesas/