From patchwork Tue Feb 19 06:04:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 158666 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3296688jaa; Mon, 18 Feb 2019 22:03:58 -0800 (PST) X-Google-Smtp-Source: AHgI3IYT87QELOR7OjK/w0OSGcsv6JVSAN0DfiSq4hSc2amWbCpB6YdqcJS3hmN/ojICpdn1f/AC X-Received: by 2002:a17:902:28c1:: with SMTP id f59mr29271764plb.37.1550556238369; Mon, 18 Feb 2019 22:03:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550556238; cv=none; d=google.com; s=arc-20160816; b=GnxfVC3/yyH0KjyShl4PNirkL1WcM88W9Fjpd3em+gWY9nRQPJ1js+rfw8zTgvsD2Z 1/4PJc368GJo4U04Yuc0ocbPVJAumKi8B80TnPRVBIIhJJVQHqeSC9sESnLvh/nWcRZt Idg6pcj0BE6dHetibqKM01FxoxiTaauduVxY1DdFDILVPrgOERKfkE7u4ZTkimZS8eBT pTAJ2UHYjvlOxE5S8gXufmnrmhqr+7LeTYCmXl1nYf4Xb7Eu3LMDF5adaDf0QHy+q9G9 pquLrY1QPIWxBriWEbl1c1rSfsMiTlg3R0DQwXF4wHYLycWErFpZhaeTZBr2AVBDuRAD lIVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=GyjR1K+SCkiQJRz7sqZ/Dyo0n3Et48Yb+zUiZSu0/dQ=; b=qkgajrPNtTd6dBrNkBj5Cjoe6BqG5wXSvj5z9T7W65JlOIARGI6PUmbXq0787Vg+d/ LRsiQhCwmIQzK+kBNlerR8Vv+n+lwbkP0E3Papg1KxEnbCB6LFdRGQskzNU+O7yhUHQk rfEZlDJNn6zSuEJmoTcaFaFsAuFMPa53Kj+puOHMQbCnB0K1qH0c3zIK1o3+QKiV4xYd Rx2MB+pr1K7HNy/r5eCg+wBn+Sup406tmyiBvn52ZeAfRbD0xmHY/Ng8xZeYHBLlX/58 +2qR7CctjwJoyB+kIMunwXY/9kZYtLSS548MQZSYQWblhNZoG8HYrqLG+RpVrGI2z6TU hZEQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ANiDQy+k; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id h62si15255939pfb.143.2019.02.18.22.03.57; Mon, 18 Feb 2019 22:03:58 -0800 (PST) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ANiDQy+k; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726360AbfBSGDx (ORCPT + 32 others); Tue, 19 Feb 2019 01:03:53 -0500 Received: from mail-pg1-f194.google.com ([209.85.215.194]:42820 "EHLO mail-pg1-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726092AbfBSGDw (ORCPT ); Tue, 19 Feb 2019 01:03:52 -0500 Received: by mail-pg1-f194.google.com with SMTP id b2so3844365pgl.9 for ; Mon, 18 Feb 2019 22:03:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=GyjR1K+SCkiQJRz7sqZ/Dyo0n3Et48Yb+zUiZSu0/dQ=; b=ANiDQy+khlnfvD/w1RKC5rOs+Q2wteA0b4ldJqmxAFgowdd/bphom+Cz+tWc2FUAwj SM4t1zeZL5sK4TCY/qDKjyYxPd7Q80aTk75sjo2bkeY1B85g++OUiwYFv3GJIUK0JF76 Tw3fsaITrSP94oFVYgbXhaQ6U5S2UK1r/AUvRZMGn5ufrEPta1NcMnob6upo6i6pr4ud 5t4Ro4s12GPpjTwDYbg8sPHi/wLggL6Mrn5FXTsar3TEBznzfuN95ngIMWb7VQx8GzYe ylLi/kYUXkSYupzA1OUzArx3jOR6YDcwxlU1H0TFykPwYmnicAOqN3lwoKdzoK0EznLx /fKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=GyjR1K+SCkiQJRz7sqZ/Dyo0n3Et48Yb+zUiZSu0/dQ=; b=aKNsJ2TPALkNReEmKmDfx040/0ce5sd2Wsjm5V1WncAmwHFwuj+IQ+D1FeDcpgNQgx nU6VA4MEtA7GivzVxwWLcCKk92vniEqooDLP5QdN7e8lS8A3kc6/AeWB6gszlZbFkYlh 2zsNSMEdOhy/E/eXextlKv0s67STGGi4sjlsHY9TsyudFT+EvN8SWClaDG7kGCQamq1y 6vfEuN9yoiSsM5VvQddV7OCQqGiXISeK0DzkRnb+qyfFjpyd4NVn+ImBG4tjSwdcdqAB QdUE5SonEaIeXik8/BPkoAppCg6JMq86O2FFQywn0VpZLGvikm7+MVyiHcNS4fiWL4RJ /bmw== X-Gm-Message-State: AHQUAua97kVcGSIPJq1xDWKwLTxgmHuaGGck7EkjTjjK31T7nGji0J7G TDnwa5BlV/1rHLiPKF9AbSiusA== X-Received: by 2002:a63:6506:: with SMTP id z6mr22343021pgb.334.1550556231327; Mon, 18 Feb 2019 22:03:51 -0800 (PST) Received: from localhost.localdomain (104-188-17-28.lightspeed.sndgca.sbcglobal.net. [104.188.17.28]) by smtp.gmail.com with ESMTPSA id 86sm31914838pfk.157.2019.02.18.22.03.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Feb 2019 22:03:50 -0800 (PST) From: Bjorn Andersson To: Michael Turquette , Stephen Boyd Cc: Andy Gross , David Brown , Bjorn Helgaas , Rob Herring , Mark Rutland , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 1/7] clk: gcc-qcs404: Add PCIe resets Date: Mon, 18 Feb 2019 22:04:01 -0800 Message-Id: <20190219060407.15263-2-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190219060407.15263-1-bjorn.andersson@linaro.org> References: <20190219060407.15263-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Enabling PCIe requires several of the PCIe related resets from GCC, so add them all. Reviewed-by: Niklas Cassel Acked-by: Stephen Boyd Signed-off-by: Bjorn Andersson --- drivers/clk/qcom/gcc-qcs404.c | 7 +++++++ include/dt-bindings/clock/qcom,gcc-qcs404.h | 7 +++++++ 2 files changed, 14 insertions(+) -- 2.18.0 diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c index 64da032bb9ed..5aed43923239 100644 --- a/drivers/clk/qcom/gcc-qcs404.c +++ b/drivers/clk/qcom/gcc-qcs404.c @@ -2675,6 +2675,13 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = { [GCC_PCIE_0_PHY_BCR] = { 0x3e004 }, [GCC_PCIE_0_LINK_DOWN_BCR] = { 0x3e038 }, [GCC_PCIEPHY_0_PHY_BCR] = { 0x3e03c }, + [GCC_PCIE_0_AXI_MASTER_STICKY_ARES] = { 0x3e040, 6}, + [GCC_PCIE_0_AHB_ARES] = { 0x3e040, 5 }, + [GCC_PCIE_0_AXI_SLAVE_ARES] = { 0x3e040, 4 }, + [GCC_PCIE_0_AXI_MASTER_ARES] = { 0x3e040, 3 }, + [GCC_PCIE_0_CORE_STICKY_ARES] = { 0x3e040, 2 }, + [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, + [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, [GCC_EMAC_BCR] = { 0x4e000 }, }; diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h index 6ceb55ed72c6..00ab0d77b38a 100644 --- a/include/dt-bindings/clock/qcom,gcc-qcs404.h +++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h @@ -161,5 +161,12 @@ #define GCC_PCIE_0_LINK_DOWN_BCR 11 #define GCC_PCIEPHY_0_PHY_BCR 12 #define GCC_EMAC_BCR 13 +#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES 14 +#define GCC_PCIE_0_AHB_ARES 15 +#define GCC_PCIE_0_AXI_SLAVE_ARES 16 +#define GCC_PCIE_0_AXI_MASTER_ARES 17 +#define GCC_PCIE_0_CORE_STICKY_ARES 18 +#define GCC_PCIE_0_SLEEP_ARES 19 +#define GCC_PCIE_0_PIPE_ARES 20 #endif From patchwork Tue Feb 19 06:04:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bjorn Andersson X-Patchwork-Id: 158672 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3297204jaa; Mon, 18 Feb 2019 22:04:36 -0800 (PST) X-Google-Smtp-Source: AHgI3IZPBB5r1yRC6kwJdRQEKDLi1jeg825dRoeskHdS4FZbXevPlz0f5cHWZNP2palVFTBG95yR X-Received: by 2002:a63:d846:: with SMTP id k6mr22725069pgj.251.1550556276586; Mon, 18 Feb 2019 22:04:36 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550556276; cv=none; d=google.com; s=arc-20160816; b=Z3c5UlF/UCX+4FCwStX5BCdBlwl8w8EKQ3YqaGPN1Q0LuHtT8Rb6XbHPy7MJ8a55cv XK98Av/ZPVQtEmrS0BVuyDBZkhvixOG5XSIHzmri+9HOnQCXEr6oGA1Ab18kWFRu8E1r fyD1vq1VvPt5JZigexp9KWLfgL0ja66ZBvrr3scZpIeRIno9+ZZbbluhied6bdTEmwmf rsqB32Xw1AecS32gbSBdEinGLYicmxd3jq1XlgittKheb7cyx9YyLNQFXo0CKPECBl/6 wMFxKYnIGl1j4jOj1XvaJMvs15uNKZMB7bzJxFtZ7QnWug+6fGCvTMexkBGdXYpZWOCE PzbA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=uK46UagMeCc0KFc0YPlTS4qrXQgdBZIe1DAGlyy2xmU=; b=zneUAbfCzRmJ1UYguHRXz9IwkZyCXrmUOXvtCSwqwEHn9Ks7XDZjgBno+5bmDJwP3z xc/1u60SqVdyxNRj2Y1wn1RA2ro1mNZakiycAVBM1zetYS1Mv+fZQTVfLXBgrauVxcOb 77GMl0uoeCN4oYM0kXfKEIweCg4Gg1S5OgAJjovZSevE6gPnABxDXRh4UrehxStPyOpe 2NchhVfwhJMMQkqnl6AqGp2vRXO9sF4tv6g+uJcSu/RR6d8AGCHIjl6CqYftJcyHhUqI IWUyi9jP3XAWfgBUh7t4mUPbiB9647cJjTwIJrU40OFtGcw9mMZhTCdxe4gG6G6hbgtM eJkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m30cXDa7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[104.188.17.28]) by smtp.gmail.com with ESMTPSA id 86sm31914838pfk.157.2019.02.18.22.03.51 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Feb 2019 22:03:52 -0800 (PST) From: Bjorn Andersson To: Rob Herring , Mark Rutland , Kishon Vijay Abraham I Cc: Andy Gross , David Brown , Bjorn Helgaas , Michael Turquette , Stephen Boyd , Stanimir Varbanov , Lorenzo Pieralisi , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: [PATCH v2 2/7] dt-bindings: phy: Add binding for Qualcomm PCIe2 PHY Date: Mon, 18 Feb 2019 22:04:02 -0800 Message-Id: <20190219060407.15263-3-bjorn.andersson@linaro.org> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190219060407.15263-1-bjorn.andersson@linaro.org> References: <20190219060407.15263-1-bjorn.andersson@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org The Qualcomm PCIe2 PHY is a Synopsys based PCIe PHY found in a number of Qualcomm platforms, add a binding to describe this. Signed-off-by: Bjorn Andersson --- .../bindings/phy/qcom-pcie2-phy.txt | 40 +++++++++++++++++++ 1 file changed, 40 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt -- 2.18.0 diff --git a/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt new file mode 100644 index 000000000000..7da02f9d78c7 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/qcom-pcie2-phy.txt @@ -0,0 +1,40 @@ +Qualcomm PCIe2 PHY controller +============================= + +The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm +platforms. + +Required properties: + - compatible: compatible list, should be: + "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy" + + - reg: offset and length of the PHY register set. + - #phy-cells: must be 0. + + - clocks: a clock-specifier pair for the "pipe" clock + + - vdda-vp-supply: phandle to low voltage regulator + - vdda-vph-supply: phandle to high voltage regulator + + - resets: reset-specifier pairs for the "phy" and "pipe" resets + - reset-names: list of resets, should contain: + "phy" and "pipe" + + - clock-output-names: name of the outgoing clock signal from the PHY PLL + +Example: + phy@7786000 { + compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"; + reg = <0x07786000 0xb8>; + + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; + resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>, + <&gcc GCC_PCIE_0_PIPE_ARES>; + reset-names = "phy", "pipe"; + + vdda-vp-supply = <&vreg_l3_1p05>; + vdda-vph-supply = <&vreg_l5_1p8>; + + clock-output-names = "pcie_0_pipe_clk"; + #phy-cells = <0>; + };