From patchwork Mon Sep 19 15:08:39 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 607485 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 79A80ECAAD3 for ; Mon, 19 Sep 2022 15:14:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229803AbiISPN7 (ORCPT ); Mon, 19 Sep 2022 11:13:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33524 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229731AbiISPNx (ORCPT ); Mon, 19 Sep 2022 11:13:53 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 15DDC3057E; Mon, 19 Sep 2022 08:13:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600429; x=1695136429; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=PEAr6TVpDp2c/6ZQZm9V8R/nrF0G8eQ7kqrLgzUvUe8=; b=BDog0Chh/rBWVP/ynWEjshO2o7xY+i8jhSrNM/snGfl3vQ5b2L4JtYzX WC2dLh2vKhnUfpMg47y/WcalvZutTV3/viMLKMv54cdD7PDkJnGOSl1N6 Y80Nl4sCv+L54D3i+fGM5hkT3T/dgKMdjlzYbgrN5I3WLK0xgS82yz0AB aMTSPMSNd5hZSnMlPfDQBf1xSuEa16IStBUuds+0hXlXmxoqLkkJVl2Wg /fyrhN+FMmkFLWm2RAxfH3uSZaCmwswRWFdd1yBVO3DzSoNcND0jAdgu0 yac6D6zGZS8zE8sRJAiweDjLU0Ixjqw2tSE2WYkN6gPpWXpR4dND7+FsF A==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="181106628" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:13:49 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:13:43 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:13:39 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v4 1/9] dt-bindings: mfd: atmel, sama5d2-flexcom: Add SPI child node ref binding Date: Mon, 19 Sep 2022 18:08:39 +0300 Message-ID: <20220919150846.1148783-2-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Another functionality of FLEXCOM is that of SPI. In order for the proper validation of the SPI children nodes through the binding to occur, the proper binding for SPI must be referenced. Signed-off-by: Sergiu Moga Reviewed-by: Krzysztof Kozlowski --- v1 -> v2: - use full schema paths v2 -> v3: - Added Reviewed-by tag, previously this was [PATCH 3] v3 -> v4: - Nothing, previously this was [PATCH 5] .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 0c80f4e98c54..f283cfd84b2d 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -78,10 +78,9 @@ patternProperties: of USART bindings. "^spi@[0-9a-f]+$": - type: object + $ref: /schemas/spi/atmel,at91rm9200-spi.yaml description: - Child node describing SPI. See ../spi/spi_atmel.txt for details - of SPI bindings. + Child node describing SPI. "^i2c@[0-9a-f]+$": $ref: /schemas/i2c/atmel,at91sam-i2c.yaml From patchwork Mon Sep 19 15:08:41 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 607484 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C7669C6FA86 for ; Mon, 19 Sep 2022 15:14:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229844AbiISPOG (ORCPT ); Mon, 19 Sep 2022 11:14:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33614 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229787AbiISPN7 (ORCPT ); Mon, 19 Sep 2022 11:13:59 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B371F33A0F; Mon, 19 Sep 2022 08:13:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600436; x=1695136436; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=P+rRI+9QkN+nmmcOSQoEFYqOSkgSlS8wWGf5Qdv3RC8=; b=bA//AGMnC8agnxYnwwo66+6CAztAbi8ohfKuDk7rS1Kck0OGWJWw+xUJ 1kboJcR5S3T1cE8v4DbhDKjIMPU/BBgpfPLk24u+VRwqhGKri5zZzIFVa jggz7o3EzztV14OpOZkTubL+YXzgrOiqIawwDMOectQPQPjX3I1JSSe44 E6gpL1yw9/AIsEln4lAX5O2tFx7ao/VwMD8GfstEZzZkOYsbBK+LaZJQw lwsLRHQiwkvd7fSYmU0oSuIRntXhscAWS7KEZJu6nKc0+RqEK0ES3PlwG AEo5qrsKCPF9jTZS57FlwBBwZuMDXmmN8B4CaiuhtIDcN+VkBMQDn0shp g==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="177851474" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:13:55 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:13:52 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:13:48 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v4 3/9] dt-bindings: serial: atmel,at91-usart: Add SAM9260 compatibles to SAM9X60 Date: Mon, 19 Sep 2022 18:08:41 +0300 Message-ID: <20220919150846.1148783-4-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Require SAM9260 fallback compatible for SAM9X60, because SAM9X60 is fully compatible with SAM9260 and Linux driver requires the latter. Signed-off-by: Sergiu Moga Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Use the commit message suggested by Krzysztof Kozlowski v3 -> v4: - add A-b tag, this was previously [PATCH 7] Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index bb1b5ed431f7..4da642763bef 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -26,6 +26,8 @@ properties: - items: - const: microchip,sam9x60-dbgu - const: microchip,sam9x60-usart + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart reg: maxItems: 1 From patchwork Mon Sep 19 15:08:43 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 607483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A292BC54EE9 for ; Mon, 19 Sep 2022 15:14:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229724AbiISPO2 (ORCPT ); Mon, 19 Sep 2022 11:14:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229761AbiISPOD (ORCPT ); Mon, 19 Sep 2022 11:14:03 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7ABDC3137B; Mon, 19 Sep 2022 08:14:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600442; x=1695136442; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LWPKpBW+FzEpHyrvfDs1eab0UJz+OP3Fs1bFiL2379w=; b=j1nNvczXnh2DBDm880EHlSFmrtezFsEOfcmRu/hXkGGaw3cYptXijBLr 2KbcgX1r5COyB9HB54mV+1kI0kx0o3yLZU199RaVxiIbkkpkjyiAEYjIu GbqDKuo14I9ZQsv/GkDxrUQ1+14/Et8aJTjL1iIeYTmbG98GcwIXSKsw1 Oivszgn8BoCOG995JfIhMlMzETkjJUNGCawc4VG+vE5W7TuhkApI4A5kG fOAiS0YvBUbs96TPkZMHs/A7cIxDFHmZcqizYKOP18l4Bm36bH2P1zZ2G YNxtWkyhyIu4JUOy4Q9Jaf+zwfsdxCYCF/6zGUdqafgi4PpLMebJUvrFm A==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="177851583" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:14:01 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:14:00 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:13:56 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga , Krzysztof Kozlowski Subject: [PATCH v4 5/9] dt-bindings: serial: atmel,at91-usart: Add gclk as a possible USART clock Date: Mon, 19 Sep 2022 18:08:43 +0300 Message-ID: <20220919150846.1148783-6-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Devicetree nodes for FLEXCOM's USART can also have an alternative clock source for the baudrate generator (other than the peripheral clock), namely the Generick Clock. Thus make the binding aware of this clock that someone may place in the clock related properties of the USART node. Signed-off-by: Sergiu Moga Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Nothing, Previously this was [PATCH 13] v3 -> v4: - Add A-b tag, this was previously [PATCH 9] .../devicetree/bindings/serial/atmel,at91-usart.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index 4da642763bef..30b2131b5860 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -36,10 +36,16 @@ properties: maxItems: 1 clock-names: - const: usart + minItems: 1 + items: + - const: usart + - const: gclk clocks: - maxItems: 1 + minItems: 1 + items: + - description: USART Peripheral Clock + - description: USART Generic Clock dmas: items: From patchwork Mon Sep 19 15:08:45 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 607482 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9779BC54EE9 for ; Mon, 19 Sep 2022 15:14:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229995AbiISPOw (ORCPT ); Mon, 19 Sep 2022 11:14:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229916AbiISPOa (ORCPT ); Mon, 19 Sep 2022 11:14:30 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 68ABE356E9; Mon, 19 Sep 2022 08:14:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600453; x=1695136453; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9l85M5Mmw+iMAkBceErn0IPu5335FhxC7YxeDPx3hLA=; b=iAMrjHpJcHEGSHviZERNBWQaf6IoSPLI8M8AiLHs/Bdyf4H2sf4XzWSe xCRfvapbEOHVSbHpMZYOlowVQ0w5DfZ37JN7TACwJjMULhxGTSNiwuyJs BueZjamDv8c7Fc34gMenklvlBxBeTc2OMTMrqbn3XxGvDn2kBUNg0I4yv Xn9ZlSQm7+d1agSmPveXPJqH+ZbT2FefhmY4mWT9/qrmCAbl8Iq7leak0 ljep3wWiuVAOos5lGFyFveJTCrtrQGi2w9xbu+Cjg09gRXG+nBdSXgWli 2jF90D8V2/TVUC0YA8/wlmFfIMlls3Th5120DUj31A8FV7CGdnu92AX5P A==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="177851613" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:14:12 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:14:08 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:14:05 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v4 7/9] tty: serial: atmel: Define BRSRCCK bitmask of UART IP's Mode Register Date: Mon, 19 Sep 2022 18:08:45 +0300 Message-ID: <20220919150846.1148783-8-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add definitions for the Baud Rate Source Clock bitmask of the Mode Register of UART IP's and its bitfields. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Nothing, previously this was [PATCH 9] V3 -> v4: - Nothing, this was previously [PATCH 11] drivers/tty/serial/atmel_serial.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 70d0611e56fd..ed64035ba6c3 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -68,6 +68,9 @@ #define ATMEL_US_NBSTOP_1 (0 << 12) #define ATMEL_US_NBSTOP_1_5 (1 << 12) #define ATMEL_US_NBSTOP_2 (2 << 12) +#define ATMEL_UA_BRSRCCK GENMASK(13, 12) /* Clock Selection for UART */ +#define ATMEL_UA_BRSRCCK_PERIPH_CLK (0 << 12) +#define ATMEL_UA_BRSRCCK_GCLK (1 << 12) #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */ #define ATMEL_US_CHMODE_NORMAL (0 << 14) #define ATMEL_US_CHMODE_ECHO (1 << 14) From patchwork Mon Sep 19 15:08:47 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 607481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29D3BECAAD3 for ; Mon, 19 Sep 2022 15:15:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229885AbiISPPG (ORCPT ); Mon, 19 Sep 2022 11:15:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33690 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229875AbiISPOr (ORCPT ); Mon, 19 Sep 2022 11:14:47 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 20245357D8; Mon, 19 Sep 2022 08:14:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663600460; x=1695136460; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=c870c32AhfgZVg4pwd9ZMePlL4mjnVCOQA4N7lzg7uk=; b=k60+i5P5Mqyl8vfrc1i+E1GdVv6KyNK+2bguKeMU95I3ACooU2eHHgkd U2FUrfHj+dkYm7W3mLRABpD/Mh8XRGgIjtbUYeOeQ/9JE+fIXcVb8GVT4 Fw/qzGqFNIy4KlA7VSJLqXIw614mloVUq6kmbaF19zFcqTK7vl8E5Pnh0 JQqijtCIUzB/+YLNky7fiYYPepD2z2cKyZvIk/9YrZDbwXfGWHeQ9oTx8 TfthvTR+nY/ysH1UYups6CpvsO21qmDUFW8wK5/ofYzR3iR3kojrtNfIs 54jLBMeF2SFzhvrz8gRZsiDcn65t13Wv+0ZKkFXxjB65sMCa5IoatevgV w==; X-IronPort-AV: E=Sophos;i="5.93,328,1654585200"; d="scan'208";a="114368422" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 19 Sep 2022 08:14:19 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Mon, 19 Sep 2022 08:14:17 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Mon, 19 Sep 2022 08:14:13 -0700 From: Sergiu Moga To: , , , , , , , , , , CC: , , , , , Sergiu Moga Subject: [PATCH v4 9/9] tty: serial: atmel: Make the driver aware of the existence of GCLK Date: Mon, 19 Sep 2022 18:08:47 +0300 Message-ID: <20220919150846.1148783-10-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220919150846.1148783-1-sergiu.moga@microchip.com> References: <20220919150846.1148783-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Previously, the atmel serial driver did not take into account the possibility of using the more customizable generic clock as its baudrate generator. Unless there is a Fractional Part available to increase accuracy, there is a high chance that we may be able to generate a baudrate closer to the desired one by using the GCLK as the clock source. Now, depending on the error rate between the desired baudrate and the actual baudrate, the serial driver will fallback on the generic clock. The generic clock must be provided in the DT node of the serial that may need a more flexible clock source. Signed-off-by: Sergiu Moga --- v1 -> v2: - take into account the different placement of the baudrate clock source into the IP's Mode Register (USART vs UART) - don't check for atmel_port->gclk != NULL - use clk_round_rate instead of clk_set_rate + clk_get_rate - remove clk_disable_unprepare from the end of the probe method v2 -> v3: - add the error rate calculation function as an inline function instead of a macro definition - add `gclk_fail` goto - replace `goto err` with `goto err_clk_disable_unprepare;` v3 -> v4: - Nothing, this was previously [PATCH 14] drivers/tty/serial/atmel_serial.c | 59 ++++++++++++++++++++++++++++++- 1 file changed, 58 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index c983798a4ab2..426f9d4f9a5a 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -110,6 +111,7 @@ struct atmel_uart_char { struct atmel_uart_port { struct uart_port uart; /* uart */ struct clk *clk; /* uart clock */ + struct clk *gclk; /* uart generic clock */ int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ u32 backup_imr; /* IMR saved during suspend */ int break_active; /* break being received */ @@ -229,6 +231,11 @@ static inline int atmel_uart_is_half_duplex(struct uart_port *port) (port->iso7816.flags & SER_ISO7816_ENABLED); } +static inline int atmel_error_rate(int desired_value, int actual_value) +{ + return 100 - (desired_value * 100) / actual_value; +} + #ifdef CONFIG_SERIAL_ATMEL_PDC static bool atmel_use_pdc_rx(struct uart_port *port) { @@ -2117,6 +2124,8 @@ static void atmel_serial_pm(struct uart_port *port, unsigned int state, * This is called on uart_close() or a suspend event. */ clk_disable_unprepare(atmel_port->clk); + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); break; default: dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); @@ -2132,7 +2141,9 @@ static void atmel_set_termios(struct uart_port *port, { struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); unsigned long flags; - unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0; + unsigned int old_mode, mode, imr, quot, div, cd, fp = 0; + unsigned int baud, actual_baud, gclk_rate; + int ret; /* save the current mode register */ mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); @@ -2302,6 +2313,46 @@ static void atmel_set_termios(struct uart_port *port, cd = min_t(unsigned int, cd, ATMEL_US_CD); } + /* + * If there is no Fractional Part, there is a high chance that + * we may be able to generate a baudrate closer to the desired one + * if we use the GCLK as the clock source driving the baudrate + * generator. + */ + if (!atmel_port->has_frac_baudrate) { + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); + gclk_rate = clk_round_rate(atmel_port->gclk, 16 * baud); + actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd); + if (gclk_rate && abs(atmel_error_rate(baud, actual_baud)) > + abs(atmel_error_rate(baud, gclk_rate / 16))) { + clk_set_rate(atmel_port->gclk, 16 * baud); + ret = clk_prepare_enable(atmel_port->gclk); + if (ret) + goto gclk_fail; + + if (atmel_port->is_usart) { + mode &= ~ATMEL_US_USCLKS; + mode |= ATMEL_US_USCLKS_GCLK; + } else { + mode &= ~ATMEL_UA_BRSRCCK; + mode |= ATMEL_UA_BRSRCCK_GCLK; + } + + /* + * Set the Clock Divisor for GCLK to 1. + * Since we were able to generate the smallest + * multiple of the desired baudrate times 16, + * then we surely can generate a bigger multiple + * with the exact error rate for an equally increased + * CD. Thus no need to take into account + * a higher value for CD. + */ + cd = 1; + } + } + +gclk_fail: quot = cd | fp << ATMEL_US_FP_OFFSET; if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) @@ -2897,6 +2948,12 @@ static int atmel_serial_probe(struct platform_device *pdev) if (ret) goto err; + atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk"); + if (IS_ERR(atmel_port->gclk)) { + ret = PTR_ERR(atmel_port->gclk); + goto err_clk_disable_unprepare; + } + ret = atmel_init_port(atmel_port, pdev); if (ret) goto err_clk_disable_unprepare;