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Mon, 19 Sep 2022 15:41:11 +0000 From: Frank Li To: maz@kernel.org, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kw@linux.com, bhelgaas@google.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, jdmason@kudzu.us, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com, ntb@lists.linux.dev, lznuaa@gmail.com, imx@lists.linux.dev, manivannan.sadhasivam@linaro.org Subject: [PATCH v11 2/6] irqchip: allow pass down .pm field at IRQCHIP_PLATFORM_DRIVER_END Date: Mon, 19 Sep 2022 10:40:34 -0500 Message-Id: <20220919154038.187168-3-Frank.Li@nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220919154038.187168-1-Frank.Li@nxp.com> References: <20220919154038.187168-1-Frank.Li@nxp.com> X-ClientProxiedBy: BY3PR05CA0059.namprd05.prod.outlook.com (2603:10b6:a03:39b::34) To AM9PR04MB8793.eurprd04.prod.outlook.com (2603:10a6:20b:408::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8793:EE_|AM0PR04MB6945:EE_ X-MS-Office365-Filtering-Correlation-Id: b8555b49-e1c4-4d66-36bb-08da9a5560e2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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But can't set .pm field of platform_driver. Added variadic macros to set .pm field or other field if need. Signed-off-by: Frank Li --- include/linux/irqchip.h | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/include/linux/irqchip.h b/include/linux/irqchip.h index 3a091d0710ae1..d5e6024cb2a8c 100644 --- a/include/linux/irqchip.h +++ b/include/linux/irqchip.h @@ -44,7 +44,8 @@ static const struct of_device_id drv_name##_irqchip_match_table[] = { #define IRQCHIP_MATCH(compat, fn) { .compatible = compat, \ .data = typecheck_irq_init_cb(fn), }, -#define IRQCHIP_PLATFORM_DRIVER_END(drv_name) \ + +#define IRQCHIP_PLATFORM_DRIVER_END(drv_name, ...) \ {}, \ }; \ MODULE_DEVICE_TABLE(of, drv_name##_irqchip_match_table); \ @@ -56,6 +57,7 @@ static struct platform_driver drv_name##_driver = { \ .owner = THIS_MODULE, \ .of_match_table = drv_name##_irqchip_match_table, \ .suppress_bind_attrs = true, \ + __VA_ARGS__ \ }, \ }; \ builtin_platform_driver(drv_name##_driver) From patchwork Mon Sep 19 15:40:36 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 607474 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 71DF8ECAAD3 for ; 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Provide msi controller support so other driver such as PCI EP can use it by standard msi interface as doorbell. Reviewed-by: Rob Herring Signed-off-by: Frank Li --- .../interrupt-controller/fsl,mu-msi.yaml | 99 +++++++++++++++++++ 1 file changed, 99 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml new file mode 100644 index 0000000000000..799ae5c3e32ae --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,mu-msi.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/fsl,mu-msi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale/NXP i.MX Messaging Unit (MU) work as msi controller + +maintainers: + - Frank Li + +description: | + The Messaging Unit module enables two processors within the SoC to + communicate and coordinate by passing messages (e.g. data, status + and control) through the MU interface. The MU also provides the ability + for one processor (A side) to signal the other processor (B side) using + interrupts. + + Because the MU manages the messaging between processors, the MU uses + different clocks (from each side of the different peripheral buses). + Therefore, the MU must synchronize the accesses from one side to the + other. The MU accomplishes synchronization using two sets of matching + registers (Processor A-side, Processor B-side). + + MU can work as msi interrupt controller to do doorbell + +allOf: + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + enum: + - fsl,imx6sx-mu-msi + - fsl,imx7ulp-mu-msi + - fsl,imx8ulp-mu-msi + - fsl,imx8ulp-mu-msi-s4 + + reg: + items: + - description: a side register base address + - description: b side register base address + + reg-names: + items: + - const: processor-a-side + - const: processor-b-side + + interrupts: + description: a side interrupt number. + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + items: + - description: a side power domain + - description: b side power domain + + power-domain-names: + items: + - const: processor-a-side + - const: processor-b-side + + interrupt-controller: true + + msi-controller: true + + "#msi-cells": + const: 0 + +required: + - compatible + - reg + - interrupts + - interrupt-controller + - msi-controller + - "#msi-cells" + +additionalProperties: false + +examples: + - | + #include + #include + + msi-controller@5d270000 { + compatible = "fsl,imx6sx-mu-msi"; + msi-controller; + #msi-cells = <0>; + interrupt-controller; + reg = <0x5d270000 0x10000>, /* A side */ + <0x5d300000 0x10000>; /* B side */ + reg-names = "processor-a-side", "processor-b-side"; + interrupts = ; + power-domains = <&pd IMX_SC_R_MU_12A>, + <&pd IMX_SC_R_MU_12B>; + power-domain-names = "processor-a-side", "processor-b-side"; + }; From patchwork Mon Sep 19 15:40:38 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Frank Li X-Patchwork-Id: 607473 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CD1E5C54EE9 for ; Mon, 19 Sep 2022 15:42:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230310AbiISPmL (ORCPT ); Mon, 19 Sep 2022 11:42:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230307AbiISPl5 (ORCPT ); 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Received: from AM9PR04MB8793.eurprd04.prod.outlook.com (2603:10a6:20b:408::22) by VI1PR04MB7165.eurprd04.prod.outlook.com (2603:10a6:800:125::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.5632.19; Mon, 19 Sep 2022 15:41:34 +0000 Received: from AM9PR04MB8793.eurprd04.prod.outlook.com ([fe80::5a3:ff70:317d:a99e]) by AM9PR04MB8793.eurprd04.prod.outlook.com ([fe80::5a3:ff70:317d:a99e%7]) with mapi id 15.20.5632.021; Mon, 19 Sep 2022 15:41:34 +0000 From: Frank Li To: maz@kernel.org, tglx@linutronix.de, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kw@linux.com, bhelgaas@google.com Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pci@vger.kernel.org, peng.fan@nxp.com, aisheng.dong@nxp.com, jdmason@kudzu.us, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, kishon@ti.com, lorenzo.pieralisi@arm.com, ntb@lists.linux.dev, lznuaa@gmail.com, imx@lists.linux.dev, manivannan.sadhasivam@linaro.org Subject: [PATCH v11 6/6] PCI: endpoint: Add vNTB MSI support Date: Mon, 19 Sep 2022 10:40:38 -0500 Message-Id: <20220919154038.187168-7-Frank.Li@nxp.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220919154038.187168-1-Frank.Li@nxp.com> References: <20220919154038.187168-1-Frank.Li@nxp.com> X-ClientProxiedBy: BY3PR05CA0059.namprd05.prod.outlook.com (2603:10b6:a03:39b::34) To AM9PR04MB8793.eurprd04.prod.outlook.com (2603:10a6:20b:408::22) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AM9PR04MB8793:EE_|VI1PR04MB7165:EE_ X-MS-Office365-Filtering-Correlation-Id: 5bf9d996-843c-4df6-f113-08da9a556e7c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?utf-8?q?xVhyj2g3+l4Q1B17WKzNM7Be4Sj2?= =?utf-8?q?mDGEQsqE0EaYmQ+iBB7WBV9M8Z4h1vPqWUdTPZvXnmdsWuhe1e/hU9xQZLGDp5Svj?= =?utf-8?q?MmX5/yVejcCotPnXNJmIrnijE2TIp9c6u9h9d+TKj5eaeY+aO7ePL4i3tvJcH81RY?= =?utf-8?q?1mw9tp9bvqi+CflCs1wXvTiSYGAZfnoiXXAGsfGDkZ2V+irUpdSUW/YYYwp8nga8K?= =?utf-8?q?/sPFuaZEcNphiu/xJuL9i342vasJo3ZwFCVcu+wuRFs50RfVwQ+GnPyrzAwwlZj+y?= =?utf-8?q?kX8GniPP/mmYSz6AGVjpy3OkiLv5MsuXMA9/bHsPUhXJWfcVkrhOyzvAN0p3Vg57t?= =?utf-8?q?eaMljNNmkYvO6Wn4O4tj4iP/aJuLoICX1JBcsZzZWNK6fyUK6GBBSN7FYgj3xKOBf?= =?utf-8?q?aDYdGOj8sqM1Kkmp8U7/OaA0TAzAAxINYs2D+ZkbqTonKsqhbWgw7fIfglCmc/GC+?= =?utf-8?q?VlN3Il2FYz/2ry8MELj67HBKXKj/22QIGUF/gschaQr7UzROKtzyh3zxKOVTGKOlB?= =?utf-8?q?28bzT1fG2KpI9QeaDwiRa4jKjbtQ/mSZLFydczjMgLjMDRrfLhC3i+yjA+H2iFH+l?= =?utf-8?q?nMnqUd6pTH1RtGerHPlNhn517FeTQgpwfZyHSJMEfh+ZZXY+vM4bCbWrRiFxbrbbW?= =?utf-8?q?c3YBeI2jPCCPjswl/UYf3dGBxjY8p3oPlSzXqOdNKFLWLqdKxxhd/2wM+qUAIRW5T?= =?utf-8?q?oGRV3OLhNGgSDG2sy2+YXC6EuQmaBcm1v2z5yTGR5qs72PRKov+MdwbZAQsI0OYEm?= =?utf-8?q?oc+iEWvK5vZO6cJFMG59VgmSqVao0Uy86jkGj04wsslXSnyP4uKQ1smNnDfifGoGR?= =?utf-8?q?olsD2ROSLXBd7vLev6kb81uXo2fdcmIoySBJXM4U0yTdUPmky/jSsyVASB4O39Fgq?= =?utf-8?q?cNahcYvGJn0V9n8CeePaB1nvarY5ALp5EAWKo5eKKdDuFXmPR7u0fy0VivuOW6SeD?= =?utf-8?q?Whb+NAZ9AmQDb34lQx8lVQbB8rHE9MgTv0eAZ+S7M2glxVPuSpDP3kTQJSb/LzN33?= =?utf-8?q?DPQJgnefjxc/jWezGbY0EdXozLKmFobZlqq9mkhazNRic9vjy91RanI/Pvf6L/pcJ?= =?utf-8?q?9eBGbYn3DjYG5n+E9iAahRU2pIuV/FQ9136a9/iox1SyID2cQXp8uYq4y5cPLN/TQ?= =?utf-8?q?wLhwlUCfuOpI5F4+2/EVR0a+RsTHiki7dnsrdPlNko/5WKFx1eUBawUclm9Lv0nw7?= =?utf-8?q?pM3RJ/JDJXKHzq2XUKjse6PbskgqSiHtaU3fYB+s2s1kxhSEfSpEC5/r0XNoiNyLZ?= =?utf-8?q?mMKBWLnb8rQi/p/T5m/oEEXwjhEAfQDPXuRlA02GoKiMi5n2j8geTQaxWQ5bqPxoT?= =?utf-8?q?mqp+4aenWtvjolzMViIkU7+77De3edYakIDbv0qTWAjKpsJe4Un4oK1xLoalTStOm?= =?utf-8?q?Waw6l1kK1jicdmne3qdPLsRiNmycAhf5HvKZ13iCTPhYGghzJ8fCLDc+ZtpB4GMtG?= =?utf-8?q?QaeHD1+q1kN62ljoZYUlyhobwV2r81gy/XtY4oFUa2ryvwxYsNzaHwc62LwkTLpcD?= =?utf-8?q?ygsnTd8bc084?= X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 5bf9d996-843c-4df6-f113-08da9a556e7c X-MS-Exchange-CrossTenant-AuthSource: AM9PR04MB8793.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 19 Sep 2022 15:41:34.7299 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: qoUQVLjzwSH/cAwj5amgKUGYDSlDc3lSzAHa9xh9hi4H7bmq1k09Kaea+C9LIoTraUx5f9ikZDhHuxeA9eJghg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB7165 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org ┌───────┐ ┌──────────┐ │ │ │ │ ┌─────────────┐ │ PCI │ │ PCI Host │ │ MSI │◄┐ │ EP │ │ │ │ Controller │ │ │ │ 3.MSI Write │ │ └────────┬────┘ └─┼───────┼───────────────────┤ │ ▲ │ │ │ ├─BAR_n │ │ └────────┼───────┼──────────────────►│ │ │ │ │ 2.Call Back │ │ │ │ │ write_msi_msg() │ │ │ │ │ │ │ │ └───┬───┘ └──────────┘ │ │ └───────────────────┘ 1.platform_msi_domain_alloc_irqs() There is no defined way of raising IRQs by PCI host to the PCI endpoint. Only define MSI/MSI-X to let EP notified RC status change. The memory assigned for BAR region by the PCI host is mapped to the message address of platform msi interrupt controller in PCI Endpoint. Such that, whenever the PCI host writes to the BAR region, it will trigger an IRQ in the Endpoint. Basic working follow as 1. EP function driver call platform_msi_domain_alloc_irqs() alloc a MSI irq from MSI controller with call back function write_msi_msg(); 2. write_msg_msg will config BAR and map to address defined in msi_msg; 3. Host side trigger an IRQ in Endpoint by write to BAR region. Add MSI support for pci-epf-vntb. Query if system has an MSI controller. Set up doorbell address according to struct msi_msg. So PCI RC can write this doorbell address to trigger EP side's IRQ. If no MSI controller exists, fall back to software polling. Signed-off-by: Frank Li --- drivers/pci/endpoint/functions/pci-epf-vntb.c | 149 +++++++++++++++--- 1 file changed, 128 insertions(+), 21 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-vntb.c b/drivers/pci/endpoint/functions/pci-epf-vntb.c index 90522de00c6a9..34e01c30aea41 100644 --- a/drivers/pci/endpoint/functions/pci-epf-vntb.c +++ b/drivers/pci/endpoint/functions/pci-epf-vntb.c @@ -44,6 +44,7 @@ #include #include #include +#include static struct workqueue_struct *kpcintb_workqueue; @@ -137,11 +138,14 @@ struct epf_ntb { struct epf_ntb_ctrl *reg; u32 *epf_db; + phys_addr_t epf_db_phys; phys_addr_t vpci_mw_phy[MAX_MW]; void __iomem *vpci_mw_addr[MAX_MW]; struct delayed_work cmd_handler; + + int msi_virqbase; }; #define to_epf_ntb(epf_group) container_of((epf_group), struct epf_ntb, group) @@ -256,10 +260,13 @@ static void epf_ntb_cmd_handler(struct work_struct *work) ntb = container_of(work, struct epf_ntb, cmd_handler.work); - for (i = 1; i < ntb->db_count; i++) { - if (ntb->epf_db[i]) { - ntb_db_event(&ntb->ntb, i); - ntb->epf_db[i] = 0; + if (!ntb->epf_db_phys) { + for (i = 1; i < ntb->db_count; i++) { + if (ntb->epf_db[i]) { + ntb->db |= 1 << (i - 1); + ntb_db_event(&ntb->ntb, i); + ntb->epf_db[i] = 0; + } } } @@ -464,7 +471,7 @@ static int epf_ntb_config_spad_bar_alloc(struct epf_ntb *ntb) for (i = 0; i < ntb->db_count; i++) { ntb->reg->db_data[i] = 1 + i; - ntb->reg->db_offset[i] = 0; + ntb->reg->db_offset[i] = sizeof(u32) * i; } return 0; @@ -517,6 +524,28 @@ static int epf_ntb_configure_interrupt(struct epf_ntb *ntb) return 0; } +static int epf_ntb_db_size(struct epf_ntb *ntb) +{ + const struct pci_epc_features *epc_features; + size_t size = sizeof(u32) * ntb->db_count; + u32 align; + + epc_features = pci_epc_get_features(ntb->epf->epc, + ntb->epf->func_no, + ntb->epf->vfunc_no); + align = epc_features->align; + + if (size < 128) + size = 128; + + if (align) + size = ALIGN(size, align); + else + size = roundup_pow_of_two(size); + + return size; +} + /** * epf_ntb_db_bar_init() - Configure Doorbell window BARs * @ntb: NTB device that facilitates communication between HOST and VHOST @@ -540,27 +569,26 @@ static int epf_ntb_db_bar_init(struct epf_ntb *ntb) ntb->epf->func_no, ntb->epf->vfunc_no); align = epc_features->align; - - if (size < 128) - size = 128; - - if (align) - size = ALIGN(size, align); - else - size = roundup_pow_of_two(size); + size = epf_ntb_db_size(ntb); barno = ntb->epf_ntb_bar[BAR_DB]; + epf_bar = &ntb->epf->bar[barno]; - mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0); - if (!mw_addr) { - dev_err(dev, "Failed to allocate OB address\n"); - return -ENOMEM; + if (ntb->epf_db_phys) { + mw_addr = NULL; + epf_bar->phys_addr = ntb->epf_db_phys; + epf_bar->barno = barno; + epf_bar->size = size; + } else { + mw_addr = pci_epf_alloc_space(ntb->epf, size, barno, align, 0); + if (!mw_addr) { + dev_err(dev, "Failed to allocate doorbell address\n"); + return -ENOMEM; + } } ntb->epf_db = mw_addr; - epf_bar = &ntb->epf->bar[barno]; - ret = pci_epc_set_bar(ntb->epf->epc, ntb->epf->func_no, ntb->epf->vfunc_no, epf_bar); if (ret) { dev_err(dev, "Doorbell BAR set failed\n"); @@ -719,6 +747,84 @@ static int epf_ntb_init_epc_bar(struct epf_ntb *ntb) return 0; } +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN +static void epf_ntb_write_msi_msg(struct msi_desc *desc, struct msi_msg *msg) +{ + struct epf_ntb *ntb = dev_get_drvdata(desc->dev); + struct epf_ntb_ctrl *reg = ntb->reg; + int size = epf_ntb_db_size(ntb); + u64 addr; + + addr = msg->address_hi; + addr <<= 32; + addr |= msg->address_lo; + + reg->db_data[desc->msi_index] = msg->data; + + if (!desc->msi_index) + ntb->epf_db_phys = round_down(addr, size); + + reg->db_offset[desc->msi_index] = addr - ntb->epf_db_phys; +} +#endif + +static irqreturn_t epf_ntb_interrupt_handler(int irq, void *data) +{ + struct epf_ntb *ntb = data; + int index; + + index = irq - ntb->msi_virqbase; + ntb->db |= 1 << (index - 1); + ntb_db_event(&ntb->ntb, index); + + return IRQ_HANDLED; +} + +#ifdef CONFIG_GENERIC_MSI_IRQ_DOMAIN +static void epf_ntb_epc_msi_init(struct epf_ntb *ntb) +{ + struct device *dev = &ntb->epf->dev; + struct irq_domain *domain; + int virq; + int ret; + int i; + + domain = dev_get_msi_domain(ntb->epf->epc->dev.parent); + if (!domain) + return; + + dev_set_msi_domain(dev, domain); + + if (platform_msi_domain_alloc_irqs(&ntb->epf->dev, + ntb->db_count, + epf_ntb_write_msi_msg)) { + dev_err(dev, "Can't allocate MSI, falling back to polling mode\n"); + return; + } + dev_info(dev, "Using MSI as doorbell\n"); + + for (i = 0; i < ntb->db_count; i++) { + virq = msi_get_virq(dev, i); + ret = devm_request_irq(dev, virq, + epf_ntb_interrupt_handler, 0, + "pci_epf_vntb", ntb); + + if (ret) { + dev_err(dev, "Failed to request doorbell IRQ! Falling back to polling mode"); + ntb->epf_db_phys = 0; + break; + } + + if (!i) + ntb->msi_virqbase = virq; /* msi start virq number */ + } +} +#else +static void epf_ntb_epc_msi_init(struct epf_ntb *ntb) +{ + return; +} +#endif /* CONFIG_GENERIC_MSI_IRQ_DOMAIN */ /** * epf_ntb_epc_init() - Initialize NTB interface * @ntb: NTB device that facilitates communication between HOST and VHOST @@ -1320,14 +1426,15 @@ static int epf_ntb_bind(struct pci_epf *epf) goto err_bar_alloc; } + epf_set_drvdata(epf, ntb); + epf_ntb_epc_msi_init(ntb); + ret = epf_ntb_epc_init(ntb); if (ret) { dev_err(dev, "Failed to initialize EPC\n"); goto err_bar_alloc; } - epf_set_drvdata(epf, ntb); - pci_space[0] = (ntb->vntb_pid << 16) | ntb->vntb_vid; pci_vntb_table[0].vendor = ntb->vntb_vid; pci_vntb_table[0].device = ntb->vntb_pid;