From patchwork Thu Sep 15 09:46:37 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 606679 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EAD7FC6FA8B for ; Thu, 15 Sep 2022 09:48:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230038AbiIOJsD (ORCPT ); Thu, 15 Sep 2022 05:48:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230094AbiIOJrd (ORCPT ); Thu, 15 Sep 2022 05:47:33 -0400 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 93E849A6B6; Thu, 15 Sep 2022 02:46:49 -0700 (PDT) X-UUID: 3e433b46dd624de4ab70071a45a1e5eb-20220915 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=xgfFopHRoYeA1RQ6DEpp5+/B5hYSDxuNukCqQVXBOr0=; b=kUaagV3vHqXQ7drxiFc2/5wS0cNA8OGk5YEXPBXkZ0ZUt+1fpH7ecfZ6suSNVwOsD/5o0SvoF3/W/X3MqsBISYYZHbbirhZSl0lNyrmsecvZGlAFQJpak87mQInG5Mkue3rFI1yaE5GkVtsAV4mij3z/RAN4fJ6rQizDXUJoebg=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:1392d9b1-ec75-4aa8-85f1-f70415536f30, IP:0, U RL:0,TC:0,Content:-5,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION :release,TS:-5 X-CID-META: VersionHash:39a5ff1, CLOUDID:4500be7b-ea28-4199-b57e-003c7d60873a, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 3e433b46dd624de4ab70071a45a1e5eb-20220915 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 2019624178; Thu, 15 Sep 2022 17:46:42 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.15; Thu, 15 Sep 2022 17:46:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 15 Sep 2022 17:46:41 +0800 From: Bo-Chen Chen To: , CC: , , , , , , , Bo-Chen Chen Subject: [PATCH v2 1/4] arm64: dts: mt8195: Add dp-intf nodes Date: Thu, 15 Sep 2022 17:46:37 +0800 Message-ID: <20220915094640.5571-2-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220915094640.5571-1-rex-bc.chen@mediatek.com> References: <20220915094640.5571-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Dp-intfs provide the pixel data to edptx and dptx. To support edptx and dptx, we need to add dp-intf0 and dp-intf1 nodes. Dp-intf0 is for edptx and dp-intf1 is for dptx. Signed-off-by: Bo-Chen Chen --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 905d1a90b406..82d28e9f60c3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -2067,6 +2067,17 @@ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>; }; + dp_intf0: dp-intf@1c015000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c015000 0 0x1000>; + interrupts = ; + clocks = <&vdosys0 CLK_VDO0_DP_INTF0>, + <&vdosys0 CLK_VDO0_DP_INTF0_DP_INTF>, + <&apmixedsys CLK_APMIXED_TVDPLL1>; + clock-names = "engine", "pixel", "pll"; + status = "disabled"; + }; + mutex: mutex@1c016000 { compatible = "mediatek,mt8195-disp-mutex"; reg = <0 0x1c016000 0 0x1000>; @@ -2155,5 +2166,17 @@ clock-names = "apb", "smi", "gals"; power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; }; + + dp_intf1: dp-intf@1c113000 { + compatible = "mediatek,mt8195-dp-intf"; + reg = <0 0x1c113000 0 0x1000>; + interrupts = ; + power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>; + clocks = <&vdosys1 CLK_VDO1_DP_INTF0_MM>, + <&vdosys1 CLK_VDO1_DPINTF>, + <&apmixedsys CLK_APMIXED_TVDPLL2>; + clock-names = "engine", "pixel", "pll"; + status = "disabled"; + }; }; }; From patchwork Thu Sep 15 09:46:40 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?UmV4LUJDIENoZW4gKOmZs+afj+i+sCk=?= X-Patchwork-Id: 606680 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42F15C6FA8B for ; Thu, 15 Sep 2022 09:48:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230203AbiIOJsA (ORCPT ); Thu, 15 Sep 2022 05:48:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43562 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230052AbiIOJrc (ORCPT ); Thu, 15 Sep 2022 05:47:32 -0400 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 56FD460692; Thu, 15 Sep 2022 02:46:47 -0700 (PDT) X-UUID: 683d22a59c5a464fb2d8d47b4de456c0-20220915 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=aleWP+Qc0EQlETQZQ8wzJbVsDpW6Hr549VkiF5sGFxs=; b=FhblS9C2WgOiwFLScPeAtq1uox9E2UO4DFv3t91pYsPZZlntKzuSDQUE4o+xBz6JZbs9Z46QhEhWqeuPuTkho+C86gJermM0Anpsky0/bfZ8D1E93hKhb0n/+gL9y5/RDoSySkKl+Q7MWyKYet3gEAPrAn7owtDI67fb0dgzgMA=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.1.11, REQID:0e3605fd-3b8f-46b1-abbb-d8b13a090c3f, IP:0, U RL:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION: release,TS:0 X-CID-META: VersionHash:39a5ff1, CLOUDID:4900be7b-ea28-4199-b57e-003c7d60873a, B ulkID:nil,BulkQuantity:0,Recheck:0,SF:nil,TC:nil,Content:0,EDM:-3,IP:nil,U RL:0,File:nil,Bulk:nil,QS:nil,BEC:nil,COL:0 X-UUID: 683d22a59c5a464fb2d8d47b4de456c0-20220915 Received: from mtkmbs11n2.mediatek.inc [(172.21.101.187)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 1630742314; Thu, 15 Sep 2022 17:46:42 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.792.3; Thu, 15 Sep 2022 17:46:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.792.15 via Frontend Transport; Thu, 15 Sep 2022 17:46:41 +0800 From: Bo-Chen Chen To: , CC: , , , , , , , Bo-Chen Chen Subject: [PATCH v2 4/4] arm64: dts: mediatek: cherry: Add edptx and dptx support Date: Thu, 15 Sep 2022 17:46:40 +0800 Message-ID: <20220915094640.5571-5-rex-bc.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20220915094640.5571-1-rex-bc.chen@mediatek.com> References: <20220915094640.5571-1-rex-bc.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In cherry projects, we use edptx as the internal display interface and use dptx as the external display interface. To support this, we need to add more properties. - Add pinctrls for edptx and dptx. - Add ports for edptx and dptx. The port connections for the internal and external display: dp-intf0 -> edptx -> panel dp-intf1 -> dptx Because it lacks port of panel, so we keep empty remote-endpoint for port1@edptx. Signed-off-by: Bo-Chen Chen --- .../boot/dts/mediatek/mt8195-cherry.dtsi | 68 +++++++++++++++++++ 1 file changed, 68 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 303dc32c64dc..560103e29017 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -125,6 +125,7 @@ port { dp_intf0_out: endpoint { + remote-endpoint = <&edp_in>; }; }; }; @@ -134,6 +135,59 @@ port { dp_intf1_out: endpoint { + remote-endpoint = <&dptx_in>; + }; + }; +}; + +&edp_tx { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&edptx_pins_default>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + edp_in: endpoint { + remote-endpoint = <&dp_intf0_out>; + }; + }; + + port@1 { + reg = <1>; + edp_out: endpoint { + data-lanes = <0 1 2 3>; + }; + }; + }; +}; + +&dp_tx { + status = "okay"; + + pinctrl-names = "default"; + pinctrl-0 = <&dptx_pin>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dptx_in: endpoint { + remote-endpoint = <&dp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dptx_out: endpoint { + data-lanes = <0 1 2 3>; + }; }; }; }; @@ -497,6 +551,20 @@ }; }; + edptx_pins_default: edptx-default-pins { + pins-cmd-dat { + pinmux = ; + bias-pull-up; + }; + }; + + dptx_pin: dptx-default-pins { + pins-cmd-dat { + pinmux = ; + bias-pull-up; + }; + }; + i2c0_pins: i2c0-default-pins { pins-bus { pinmux = ,