From patchwork Thu Sep 15 18:15:49 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 606335 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EF47AC6FA8A for ; Thu, 15 Sep 2022 18:17:30 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229797AbiIOSR3 (ORCPT ); Thu, 15 Sep 2022 14:17:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38424 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229479AbiIOSR2 (ORCPT ); Thu, 15 Sep 2022 14:17:28 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 355E98051F; Thu, 15 Sep 2022 11:17:27 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id e16so32109221wrx.7; Thu, 15 Sep 2022 11:17:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=1kMaGOYyU6bj/tvC0QnNHtm9kk+nLvr6d2aRk6glIRs=; b=QQ02RwhHzFVjmu0CTMvsqR4LNpGw08oPc7Vv9eCr/WGRACQPmttZU6QybB1rGNtYb7 jCXHS+o+6IB6HhQYuzpWvrizRX7IvpxizaGkEY4cgGdaLgLK3CAfHXe2+1aUQBB3DbCI vfB5FuHOAYooEGf2xag3Hk8K96CwSk/QEs5P2LSPGD5PZbRPWk+/7gPPPvHiBXNlO294 lCWryhApUMmYLeBOqDJFjXcEeomnrVRrErvRACENER9maugY2Yn3Eu/FbH6odtxrgsQ2 QRx1QKGHZCuPK0FzEg1pIiKSCwzsfKERg6UgmmuKRvF58TS+xlG2vXyG76nyw67avwsW 59xg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=1kMaGOYyU6bj/tvC0QnNHtm9kk+nLvr6d2aRk6glIRs=; b=2OQKdu4I+lW0pvhm6HTn4+bgL72w5htYPNJZvFw2AX3qKMNdrvE5tcQWZQ6LiSIIW1 fS6vflomt/X9pSvIjd5o9TniF5+D5mN5fMme+GywFLXgyj4watFVd2KUXt3lwBaYS4eG a9qomCjqnyQUxZwCrz0s0AkAXo0zJL6MpNvSIGkxHhbVPhC7w/LH8g+X1vWFlW3XV+oD GqJC0Ec/qlmp6UjEVICzVC6nwSo++hvPwdVguc0wByFcN20Ww4cYSDZLVqFd/tXRV6E3 YkdpyrstH6faRR4dhj8fDDfMIPJBUvkCjHpH/3vQPm9VvIRq6z2DFPEoXGOl+RT9x++L 71SQ== X-Gm-Message-State: ACrzQf3s7p9Q2LccK/iibUlvJOTMYo2VhE6+yf87Bii6VOjzV7mdbdae y/IbfsrHU3cRargFX1rNabA= X-Google-Smtp-Source: AMsMyM5pSwquDv6Z9TOe/3EQTCmIcBKd4kDwDnrHZ4I8sBfN2WGkB7fNfmNXrOljyfGoNCbfKNTyXw== X-Received: by 2002:a05:6000:1548:b0:22a:c113:c9d0 with SMTP id 8-20020a056000154800b0022ac113c9d0mr610513wry.653.1663265845601; Thu, 15 Sep 2022 11:17:25 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d411:a48b:4035:3d98]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b003b47e8a5d22sm4243151wmq.23.2022.09.15.11.17.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 11:17:24 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Date: Thu, 15 Sep 2022 19:15:49 +0100 Message-Id: <20220915181558.354737-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar renesas.yaml lists out all the Renesas SoC's and the platforms/EVK's which is either ARM32/ARM64. It would rather make sense if we move renesas.yaml to the soc/renesas folder instead. This is in preparation for adding a new SoC (RZ/Five) from Renesas which is based on RISC-V. While at it drop the old entry for renesas.yaml from MAINTAINERS file and there is no need to update the new file path of renesas.yaml as we already have an entry for Documentation/devicetree/bindings/soc/renesas/ folder. Signed-off-by: Lad Prabhakar --- v3: * New patch along with this series previously posted as a standalone patch [0]. [0] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220815111708.22302-1-prabhakar.mahadev-lad.rj@bp.renesas.com/ --- .../devicetree/bindings/{arm => soc/renesas}/renesas.yaml | 0 MAINTAINERS | 1 - 2 files changed, 1 deletion(-) rename Documentation/devicetree/bindings/{arm => soc/renesas}/renesas.yaml (100%) diff --git a/Documentation/devicetree/bindings/arm/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml similarity index 100% rename from Documentation/devicetree/bindings/arm/renesas.yaml rename to Documentation/devicetree/bindings/soc/renesas/renesas.yaml diff --git a/MAINTAINERS b/MAINTAINERS index c26a5c573a5d..f5f17c50dac3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2673,7 +2673,6 @@ S: Supported Q: http://patchwork.kernel.org/project/linux-renesas-soc/list/ C: irc://irc.libera.chat/renesas-soc T: git git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel.git next -F: Documentation/devicetree/bindings/arm/renesas.yaml F: Documentation/devicetree/bindings/hwinfo/renesas,prr.yaml F: Documentation/devicetree/bindings/soc/renesas/ F: arch/arm/boot/dts/emev2* From patchwork Thu Sep 15 18:15:50 2022 Content-Type: text/plain; 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Thu, 15 Sep 2022 11:17:27 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d411:a48b:4035:3d98]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b003b47e8a5d22sm4243151wmq.23.2022.09.15.11.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 11:17:26 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v3 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Date: Thu, 15 Sep 2022 19:15:50 +0100 Message-Id: <20220915181558.354737-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Sort the CPU cores list alphabetically for maintenance. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v2->v3 * included RB tag from Geert v1->v2 * Included RB tag from Krzysztof --- Documentation/devicetree/bindings/riscv/cpus.yaml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 873dd12f6e89..2a1c5ae5b0aa 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -27,17 +27,17 @@ properties: oneOf: - items: - enum: - - sifive,rocket0 + - canaan,k210 - sifive,bullet0 - sifive,e5 - sifive,e7 - sifive,e71 - - sifive,u74-mc - - sifive,u54 - - sifive,u74 + - sifive,rocket0 - sifive,u5 + - sifive,u54 - sifive,u7 - - canaan,k210 + - sifive,u74 + - sifive,u74-mc - const: riscv - items: - enum: From patchwork Thu Sep 15 18:15:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 606334 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E9DEC6FA89 for ; Thu, 15 Sep 2022 18:17:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230009AbiIOSRv (ORCPT ); Thu, 15 Sep 2022 14:17:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38854 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229688AbiIOSRs (ORCPT ); Thu, 15 Sep 2022 14:17:48 -0400 Received: from mail-wr1-x42d.google.com (mail-wr1-x42d.google.com [IPv6:2a00:1450:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C13638051F; Thu, 15 Sep 2022 11:17:30 -0700 (PDT) Received: by mail-wr1-x42d.google.com with SMTP id z12so13795038wrp.9; Thu, 15 Sep 2022 11:17:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=VByNharHGLanOsbOdnpEOJCaC2XQblJhvKILKud7IVA=; b=CNodDYGGDRF3F57AByDk6llGUtw61Azz9Xq6nwQaUhcHiZ2tazzJDQ7qUf/62wrxMQ cjMEKadtZLluRnMFQ2beQJ0rw7DLn30gjdXrZaZlsrLS2439dcwXpu8yOFb1czRz3ZbQ Ea+kbhjzm+Lo4TO3W2VoaJ4VdISG3aO/b2n/MZSjDxnh7Ng+Ox/lPvFpoQAZKyt9In8z VAZRZhuPsHDxcThdULcmiMNVpBeukbHO7hPaVJckfAsWDklyGKwKmnrU4isWfvHRv0VO VQtnc/X1KlZ2RL2Z6ecXc6qKLL+aMiui+kh1rvNUgKSnwe6k9jYfM+Ovao0ve9LoMVeD xbwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=VByNharHGLanOsbOdnpEOJCaC2XQblJhvKILKud7IVA=; b=69CR8BUjt1Hh8Un4p6YrAaqUu3DzJkJ98DwS08mIAp6Q05cjFOGZ6RzKmOHTZtLShq ALBKA5AP9eGruDvLG2EYsdZ8mDkaN6Lz5aWgYIOvkFztWw+q1GuBLtYHwiiHXYM454LH 62bQG8GKY0uitnnsMSTHAHxjakZZAVeY7eHX7QPeyqDLsaBQ5aDyFeQtctNm3FTjUaAN tdXrrJupjEIAzckNtNkjU3C8cCOmwQ2ammbPvdQB8XxzpQtkyXhV7IJA19LTetfPw2UH mT4DI0ck37g5ROEC/1AIo+dHrrcP5bTtbB79fLnVur6pyObQ/xlAtO28xIRggWyVNTg3 4U1g== X-Gm-Message-State: ACrzQf0T6iJtgV3y0Hugg6Mbok31qQdSEGVmAIOleVlhxc6wRHt9sw2J B4qLxovnmbHXctYvvaOHb1Q= X-Google-Smtp-Source: AMsMyM43hky2saxYh9NecZIEnEeUAsq5+QGjHuAYvAfC9WBt5PlYgNayB8FrH5f1QV3njyHRioEy2w== X-Received: by 2002:a5d:5150:0:b0:22a:43a8:145b with SMTP id u16-20020a5d5150000000b0022a43a8145bmr636108wrt.170.1663265849318; Thu, 15 Sep 2022 11:17:29 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d411:a48b:4035:3d98]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b003b47e8a5d22sm4243151wmq.23.2022.09.15.11.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 11:17:28 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v3 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Date: Thu, 15 Sep 2022 19:15:51 +0100 Message-Id: <20220915181558.354737-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar The Renesas RZ/Five microprocessor includes a RISC-V CPU Core (AX45MP Single) from Andes. In preparation to add support for RZ/Five SoC add the Andes AX45MP core to the list. More details about Andes AX45MP core can be found here: [0] http://www.andestech.com/en/products-solutions/andescore-processors/riscv-ax45mp/ Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v2->v3 * Included RB tag from Geert v1->v2 * Included ack from Krzysztof --- Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 2a1c5ae5b0aa..1681767790c5 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -27,6 +27,7 @@ properties: oneOf: - items: - enum: + - andestech,ax45mp - canaan,k210 - sifive,bullet0 - sifive,e5 From patchwork Thu Sep 15 18:15:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 606333 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D551CC6FA8A for ; Thu, 15 Sep 2022 18:17:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230040AbiIOSRw (ORCPT ); Thu, 15 Sep 2022 14:17:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38880 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229479AbiIOSRs (ORCPT ); Thu, 15 Sep 2022 14:17:48 -0400 Received: from mail-wr1-x432.google.com (mail-wr1-x432.google.com [IPv6:2a00:1450:4864:20::432]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ED533883C4; Thu, 15 Sep 2022 11:17:31 -0700 (PDT) Received: by mail-wr1-x432.google.com with SMTP id e16so32109534wrx.7; Thu, 15 Sep 2022 11:17:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=DlfLNEnJzkppJftCUUhFQByphbHbOmAnWdcgiohRW60=; b=hM0I9QdqQtIUxR1qSRvsjFP2FzHyMjgIs+Ic+QKjwiZg/1fs8IwOb3pjMsL/OqwJ8l Inqnkukb8OvL2yqEynuvwieYpmgh8DDxvEUcCbqNSyf3Xd10mw2vlq4tMAIp1R3ovKfj TunWBD953JGKSahmnTCq2I2QCocacbvER871aKS4Twb44HwhdvDmI6LpCU/+OsrzE/7i qG5MUo6qBQj5zl+8/pSDwwnqIdnJkRZ/b+/EG6sOhPn55aD7WNY70g7t6rJ+epxdW7HJ LNqv8iOfzmfV6jIJZcJtXrSrnmsrt3t/oE1Sj8cjGHVmcZOlaDX5+ZZ66iK2oyBwDa/H RF3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=DlfLNEnJzkppJftCUUhFQByphbHbOmAnWdcgiohRW60=; b=gzEjkBMWsU7+V0a+oPGo4NpZUAA7dG4f8F7PCntrRBDWtCEnqjNsSub1mMagzX0zQO JvgaNNm+eoCHlqFxj9eVjOyrw1volQrrL5EGsfjNHUvu9FHrSRYptJUcB2KuFtj4gpb0 e0vStVhbzIc8/GP736jbb8cOZyQ+5dndGkNZOkH+V+PsOMLUKL/JtRWzPnRTlqsy0MXc amj+bFM4WzG4VJChq5QRt0bE58/nMn9gvgqk/yVQEO3RLfHnANixa3Y+saFgn/5kORSp gp0DoHh9TWHYcExuGS2WwvbsrsabHtJg3zuIgC1JiAsLligoqWtyBM6VmQluARJIhcyU 3SIw== X-Gm-Message-State: ACrzQf1WIeSXxvWEe9ytOiw2Pd9LJSPCQ4DGvbWASLl5T1qrRoy2kAhW oSTfWgs8kUp0ls7R9efJrmY= X-Google-Smtp-Source: AMsMyM72fYaxbw/fQj9d07nNHvdmzMbmevob6z4j1zFc2p/Qm9ONBBcoYLu19erjaE+mJ0Qsua3FWg== X-Received: by 2002:a05:6000:2ad:b0:228:cf8f:fe85 with SMTP id l13-20020a05600002ad00b00228cf8ffe85mr649664wry.94.1663265851515; Thu, 15 Sep 2022 11:17:31 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d411:a48b:4035:3d98]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b003b47e8a5d22sm4243151wmq.23.2022.09.15.11.17.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 11:17:30 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v3 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Date: Thu, 15 Sep 2022 19:15:52 +0100 Message-Id: <20220915181558.354737-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Document Renesas RZ/Five (R9A07G043) SoC. More info about RZ/Five SoC: https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet Signed-off-by: Lad Prabhakar Acked-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v2->v3 * Dropped "(RISC-V core)" comment * Included ACK and RB tags v1->v2 * New patch --- Documentation/devicetree/bindings/soc/renesas/renesas.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index f51464a08aff..34050e7be637 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -431,11 +431,12 @@ properties: - renesas,rzn1d400-db # RZN1D-DB (RZ/N1D Demo Board for the RZ/N1D 400 pins package) - const: renesas,r9a06g032 - - description: RZ/G2UL (R9A07G043) + - description: RZ/Five and RZ/G2UL (R9A07G043) items: - enum: - renesas,smarc-evk # SMARC EVK - enum: + - renesas,r9a07g043f01 # RZ/Five - renesas,r9a07g043u11 # RZ/G2UL Type-1 - renesas,r9a07g043u12 # RZ/G2UL Type-2 - const: renesas,r9a07g043 From patchwork Thu Sep 15 18:15:53 2022 Content-Type: text/plain; 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Thu, 15 Sep 2022 11:17:33 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d411:a48b:4035:3d98]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b003b47e8a5d22sm4243151wmq.23.2022.09.15.11.17.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 11:17:32 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 05/10] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Date: Thu, 15 Sep 2022 19:15:53 +0100 Message-Id: <20220915181558.354737-6-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most of the Renesas drivers depend on this config option. Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven --- v2->v3 * Included RB tag from Geert v1->v2 * No Change --- arch/riscv/Kconfig.socs | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs index 69774bb362d6..91b7f38b77a8 100644 --- a/arch/riscv/Kconfig.socs +++ b/arch/riscv/Kconfig.socs @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE endif # SOC_CANAAN +config ARCH_RENESAS + bool + select GPIOLIB + select PINCTRL + select SOC_BUS + +config SOC_RENESAS_RZFIVE + bool "Renesas RZ/Five SoC" + select ARCH_R9A07G043 + select ARCH_RENESAS + select RESET_CONTROLLER + help + This enables support for Renesas RZ/Five SoC. + endmenu # "SoC selection" From patchwork Thu Sep 15 18:15:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 606635 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 772D3ECAAA1 for ; Thu, 15 Sep 2022 18:17:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229991AbiIOSRz (ORCPT ); Thu, 15 Sep 2022 14:17:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38882 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229994AbiIOSRu (ORCPT ); Thu, 15 Sep 2022 14:17:50 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 687238A7E1; Thu, 15 Sep 2022 11:17:36 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id h8so25148577wrf.3; Thu, 15 Sep 2022 11:17:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=O2VLizPOFB8Cw4tUD1XPYg1pr+6HOsBm1gy7frAi+N8=; b=WjEv3HYvp+P8hT/A+r1RHj7K0WdkUmFxq4Bph7B8aE9nk4YmAVR9Vtjz/ZxaZ/PgLb L1oReoZcG1UW51RdkDI6kB74J1mO0ellGTLUMWnfInG8EE8wayZCH/xablk2X+MAk6he UZKTly33tWVbNozQhmhTiyQ0c+U1xruHTxKVB/H3q5vMRRAxI8GSp6vmjDw/o/fDYV5C BcK73vgZCXhaswM6xzcG/7PyQfAg3Wz3HX8Juf319Vs1RmZL3MkjXaD4bgSt2E6tnqW/ 1vuOjUF6Cgoapvz2zrDrd9AR7nJwL+YPuf/iSQCwB1gvFvDJKpSgm1cYS5uA1vW/PXgV Ouog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=O2VLizPOFB8Cw4tUD1XPYg1pr+6HOsBm1gy7frAi+N8=; b=Gnc5Xw3Ey3uSINFEBwW3BmKqaMWLHzsfHaKUWHygRk361m9KY3t6BuNjIKnO/U7VGC 37o+TMpvltXD08uLLABNRZ48J3U0DlPks7FHXFvO2cGuuO/d3uvM/OPbSGLRadTGRWfB 8+v6HLTUaEavvfD18M8rPK0Aru9AE36JYPTJpJv69hQOvBM6IRwTFjMyw7h8yZMj0bzE fKL3jX25egJR/hvW2vU+in8AWIcIkvmG6bp81XsA+MNCoVfNjrJGM66DAf7kfjoI5m0z g//Xfe9gWul12RQmCTaBY7mJ438KUVd6lbT1sHTVX5rgd65OlTh99EBxWqm4cXNPNYCb mE0w== X-Gm-Message-State: ACrzQf2Rd9HnsImqboJo37HpGz6sUZ+sRF5fdPEL5xF5BJVBEBV5A+1t VcLvMJUDJs8FPJSPuq22i3U= X-Google-Smtp-Source: AMsMyM4GZLek6Dbkaa0Gg6W0uuQfJsrc32TNRUf+JpBGN81tL3eR5A97hx5L6vwOK3q4FrzRhi6RpA== X-Received: by 2002:a05:6000:178c:b0:222:f8ec:9977 with SMTP id e12-20020a056000178c00b00222f8ec9977mr569349wrg.509.1663265854886; Thu, 15 Sep 2022 11:17:34 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d411:a48b:4035:3d98]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b003b47e8a5d22sm4243151wmq.23.2022.09.15.11.17.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 11:17:33 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Date: Thu, 15 Sep 2022 19:15:54 +0100 Message-Id: <20220915181558.354737-7-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Add initial device tree for Renesas RZ/Five RISC-V CPU Core (AX45MP Single). Below is the list of IP blocks added in the initial SoC DTSI which can be used to boot via initramfs on RZ/Five SMARC EVK: - AX45MP CPU - CPG - PINCTRL - PLIC - SCIF0 - SYSC Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Reviewed-by: Conor Dooley --- v2->v3 * Fixed clock entry for CPU core * Fixed timebase frequency to 12MHz * Fixed sorting of the nodes * Included RB tags v1->v2 * Dropped including makefile change * Updated ndev count --- arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 120 +++++++++++++++++++++ 1 file changed, 120 insertions(+) create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043.dtsi diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi new file mode 100644 index 000000000000..fb6733f3cc2b --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi @@ -0,0 +1,120 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SoC + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include +#include + +/ { + compatible = "renesas,r9a07g043"; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + timebase-frequency = <12000000>; + + ax45mp: cpu@0 { + compatible = "andestech,ax45mp", "riscv"; + device_type = "cpu"; + reg = <0x0>; + status = "okay"; + riscv,isa = "rv64imafdc"; + mmu-type = "riscv,sv39"; + i-cache-size = <0x8000>; + i-cache-line-size = <0x40>; + d-cache-size = <0x8000>; + d-cache-line-size = <0x40>; + clocks = <&cpg CPG_CORE R9A07G043_CLK_I>; + + cpu0_intc: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + + /* clock can be either from exclk or crystal oscillator (XIN/XOUT) */ + extal_clk: extal-clk { + compatible = "fixed-clock"; + #clock-cells = <0>; + /* This value must be overridden by the board */ + clock-frequency = <0>; + }; + + soc: soc { + compatible = "simple-bus"; + interrupt-parent = <&plic>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + scif0: serial@1004b800 { + compatible = "renesas,scif-r9a07g043", + "renesas,scif-r9a07g044"; + reg = <0 0x1004b800 0 0x400>; + interrupts = <412 IRQ_TYPE_LEVEL_HIGH>, + <414 IRQ_TYPE_LEVEL_HIGH>, + <415 IRQ_TYPE_LEVEL_HIGH>, + <413 IRQ_TYPE_LEVEL_HIGH>, + <416 IRQ_TYPE_LEVEL_HIGH>, + <416 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "eri", "rxi", "txi", + "bri", "dri", "tei"; + clocks = <&cpg CPG_MOD R9A07G043_SCIF0_CLK_PCK>; + clock-names = "fck"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_SCIF0_RST_SYSTEM_N>; + status = "disabled"; + }; + + cpg: clock-controller@11010000 { + compatible = "renesas,r9a07g043-cpg"; + reg = <0 0x11010000 0 0x10000>; + clocks = <&extal_clk>; + clock-names = "extal"; + #clock-cells = <2>; + #reset-cells = <1>; + #power-domain-cells = <0>; + }; + + sysc: system-controller@11020000 { + compatible = "renesas,r9a07g043-sysc"; + reg = <0 0x11020000 0 0x10000>; + status = "disabled"; + }; + + pinctrl: pinctrl@11030000 { + compatible = "renesas,r9a07g043-pinctrl"; + reg = <0 0x11030000 0 0x10000>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + interrupt-controller; + gpio-ranges = <&pinctrl 0 0 152>; + clocks = <&cpg CPG_MOD R9A07G043_GPIO_HCLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_GPIO_RSTN>, + <&cpg R9A07G043_GPIO_PORT_RESETN>, + <&cpg R9A07G043_GPIO_SPARE_RESETN>; + }; + + plic: interrupt-controller@12c00000 { + compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; + #interrupt-cells = <2>; + #address-cells = <0>; + riscv,ndev = <512>; + interrupt-controller; + reg = <0x0 0x12c00000 0 0x400000>; + clocks = <&cpg CPG_MOD R9A07G043_NCEPLIC_ACLK>; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; + interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; + }; + }; +}; From patchwork Thu Sep 15 18:15:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 606332 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4D739C6FA86 for ; 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Thu, 15 Sep 2022 11:17:35 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 07/10] riscv: boot: dts: r9a07g043: Add placeholder nodes Date: Thu, 15 Sep 2022 19:15:55 +0100 Message-Id: <20220915181558.354737-8-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI. This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier board DTS/I. Signed-off-by: Lad Prabhakar --- v1->v3 * New patch --- arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 177 +++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi index fb6733f3cc2b..6d9db759a847 100644 --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi @@ -13,6 +13,14 @@ / { #address-cells = <2>; #size-cells = <2>; + audio_clk1: audio1-clk { + /* placeholder */ + }; + + audio_clk2: audio2-clk { + /* placeholder */ + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -54,6 +62,23 @@ soc: soc { #size-cells = <2>; ranges; + ssi1: ssi@1004a000 { + reg = <0 0x1004a000 0 0x400>; + #sound-dai-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + spi1: spi@1004b000 { + reg = <0 0x1004b000 0 0x400>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + scif0: serial@1004b800 { compatible = "renesas,scif-r9a07g043", "renesas,scif-r9a07g044"; @@ -73,6 +98,48 @@ scif0: serial@1004b800 { status = "disabled"; }; + canfd: can@10050000 { + reg = <0 0x10050000 0 0x8000>; + status = "disabled"; + + /* placeholder */ + }; + + i2c0: i2c@10058000 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058000 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + i2c1: i2c@10058400 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0 0x10058400 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + adc: adc@10059000 { + reg = <0 0x10059000 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + sbc: spi@10060000 { + reg = <0 0x10060000 0 0x10000>, + <0 0x20000000 0 0x10000000>, + <0 0x10070000 0 0x10000>; + reg-names = "regs", "dirmap", "wbuf"; + status = "disabled"; + + /* placeholder */ + }; + cpg: clock-controller@11010000 { compatible = "renesas,r9a07g043-cpg"; reg = <0 0x11010000 0 0x10000>; @@ -104,6 +171,95 @@ pinctrl: pinctrl@11030000 { <&cpg R9A07G043_GPIO_SPARE_RESETN>; }; + sdhi0: mmc@11c00000 { + reg = <0x0 0x11c00000 0 0x10000>; + status = "disabled"; + + /* placeholder */ + }; + + sdhi1: mmc@11c10000 { + reg = <0x0 0x11c10000 0 0x10000>; + status = "disabled"; + + /* placeholder */ + }; + + eth0: ethernet@11c20000 { + reg = <0 0x11c20000 0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + eth1: ethernet@11c30000 { + reg = <0 0x11c30000 0 0x10000>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + /* placeholder */ + }; + + phyrst: usbphy-ctrl@11c40000 { + reg = <0 0x11c40000 0 0x10000>; + #reset-cells = <1>; + status = "disabled"; + + /* placeholder */ + }; + + ohci0: usb@11c50000 { + reg = <0 0x11c50000 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ohci1: usb@11c70000 { + reg = <0 0x11c70000 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ehci0: usb@11c50100 { + reg = <0 0x11c50100 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + ehci1: usb@11c70100 { + reg = <0 0x11c70100 0 0x100>; + status = "disabled"; + + /* placeholder */ + }; + + usb2_phy0: usb-phy@11c50200 { + reg = <0 0x11c50200 0 0x700>; + status = "disabled"; + + /* placeholder */ + }; + + usb2_phy1: usb-phy@11c70200 { + reg = <0 0x11c70200 0 0x700>; + status = "disabled"; + + /* placeholder */ + }; + + hsusb: usb@11c60000 { + reg = <0 0x11c60000 0 0x10000>; + status = "disabled"; + + /* placeholder */ + }; + plic: interrupt-controller@12c00000 { compatible = "renesas,r9a07g043-plic", "andestech,nceplic100"; #interrupt-cells = <2>; @@ -116,5 +272,26 @@ plic: interrupt-controller@12c00000 { resets = <&cpg R9A07G043_NCEPLIC_ARESETN>; interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>; }; + + wdt0: watchdog@12800800 { + reg = <0 0x12800800 0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + ostm1: timer@12801400 { + reg = <0x0 0x12801400 0x0 0x400>; + status = "disabled"; + + /* placeholder */ + }; + + ostm2: timer@12801800 { + reg = <0x0 0x12801800 0x0 0x400>; + status = "disabled"; + + /* placeholder */ + }; }; }; From patchwork Thu Sep 15 18:15:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 606331 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3E68C6FA8D for ; Thu, 15 Sep 2022 18:18:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230148AbiIOSSM (ORCPT ); Thu, 15 Sep 2022 14:18:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39068 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230045AbiIOSRx (ORCPT ); Thu, 15 Sep 2022 14:17:53 -0400 Received: from mail-wm1-x32e.google.com (mail-wm1-x32e.google.com [IPv6:2a00:1450:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C30EC9F1AD; Thu, 15 Sep 2022 11:17:40 -0700 (PDT) Received: by mail-wm1-x32e.google.com with SMTP id c2-20020a1c3502000000b003b2973dafb7so18218071wma.2; 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Thu, 15 Sep 2022 11:17:38 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d411:a48b:4035:3d98]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b003b47e8a5d22sm4243151wmq.23.2022.09.15.11.17.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 11:17:37 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Date: Thu, 15 Sep 2022 19:15:56 +0100 Message-Id: <20220915181558.354737-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Enable the minimal blocks required for booting the Renesas RZ/Five SMARC EVK with initramfs. Below are the blocks enabled: - CPG - CPU0 - DDR (memory regions) - PINCTRL - PLIC - SCIF0 Note we have deleted the nodes from the DT for which support needs to be added for RZ/Five SoC and are enabled by RZ/G2UL SMARC EVK SoM/carrier board DTS/I. Signed-off-by: Lad Prabhakar --- v2->v3 * Dropped RB tags from Conor and Geert * Now re-using the SoM and carrier board DTS/I from RZ/G2UL v1->v2 * New patch --- arch/riscv/boot/dts/Makefile | 1 + arch/riscv/boot/dts/renesas/Makefile | 2 + .../boot/dts/renesas/r9a07g043f01-smarc.dts | 27 +++++++++ .../boot/dts/renesas/rzfive-smarc-som.dtsi | 42 ++++++++++++++ arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi | 56 +++++++++++++++++++ 5 files changed, 128 insertions(+) create mode 100644 arch/riscv/boot/dts/renesas/Makefile create mode 100644 arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi create mode 100644 arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile index ff174996cdfd..b0ff5fbabb0c 100644 --- a/arch/riscv/boot/dts/Makefile +++ b/arch/riscv/boot/dts/Makefile @@ -3,5 +3,6 @@ subdir-y += sifive subdir-y += starfive subdir-$(CONFIG_SOC_CANAAN_K210_DTB_BUILTIN) += canaan subdir-y += microchip +subdir-y += renesas obj-$(CONFIG_BUILTIN_DTB) := $(addsuffix /, $(subdir-y)) diff --git a/arch/riscv/boot/dts/renesas/Makefile b/arch/riscv/boot/dts/renesas/Makefile new file mode 100644 index 000000000000..2d3f5751a649 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0 +dtb-$(CONFIG_ARCH_R9A07G043) += r9a07g043f01-smarc.dtb diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts new file mode 100644 index 000000000000..9747f30c5db5 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/r9a07g043f01-smarc.dts @@ -0,0 +1,27 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +/dts-v1/; + +/* + * DIP-Switch SW1 setting + * 1 : High; 0: Low + * SW1-2 : SW_SD0_DEV_SEL (0: uSD; 1: eMMC) + * SW1-3 : SW_ET0_EN_N (0: ETHER0; 1: CAN0, CAN1, SSI1, RSPI1) + * Please change below macros according to SW1 setting on SoM + */ +#define SW_SW0_DEV_SEL 1 +#define SW_ET0_EN_N 1 + +#include "r9a07g043.dtsi" +#include "rzfive-smarc-som.dtsi" +#include "rzfive-smarc.dtsi" + +/ { + model = "Renesas SMARC EVK based on r9a07g043f01"; + compatible = "renesas,smarc-evk", "renesas,r9a07g043f01", "renesas,r9a07g043"; +}; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi new file mode 100644 index 000000000000..8547c273f140 --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK SOM + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include + +/ { + aliases { + /delete-property/ ethernet0; + /delete-property/ ethernet1; + }; + + chosen { + bootargs = "ignore_loglevel"; + }; +}; + +#if (SW_SW0_DEV_SEL) +/delete-node/ &adc; +#endif + +#if (!SW_ET0_EN_N) +/delete-node/ ð0; +#endif +/delete-node/ ð1; + +/delete-node/ &ostm1; +/delete-node/ &ostm2; + +/delete-node/ ®_1p8v; +/delete-node/ ®_3p3v; + +/delete-node/ &sdhi0; + +#if !(SW_SW0_DEV_SEL) +/delete-node/ &vccq_sdhi0; +#endif + +/delete-node/ &wdt0; diff --git a/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi new file mode 100644 index 000000000000..3fde7192241e --- /dev/null +++ b/arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/* + * Device Tree Source for the RZ/Five SMARC EVK carrier board + * + * Copyright (C) 2022 Renesas Electronics Corp. + */ + +#include + +/ { + aliases { + /delete-property/ i2c0; + /delete-property/ i2c1; + }; +}; + +/delete-node/ &audio_clk1; +/delete-node/ &audio_clk2; +/delete-node/ &audio_mclock; + +/delete-node/ &canfd; + +/delete-node/ &cpu_dai; + +/delete-node/ &ehci0; +/delete-node/ &ehci1; + +/delete-node/ &hsusb; + +/delete-node/ &i2c0; +/delete-node/ &i2c1; + +/delete-node/ &ohci0; +/delete-node/ &ohci1; + +&pinctrl { + /delete-property/ pinctrl-0; + /delete-property/ pinctrl-names; +}; + +/delete-node/ &phyrst; + +/delete-node/ &sdhi1; + +/delete-node/ &snd_rzg2l; + +/delete-node/ &spi1; + +/delete-node/ &ssi1; + +/delete-node/ &usb0_vbus_otg; + +/delete-node/ &usb2_phy0; +/delete-node/ &usb2_phy1; + +/delete-node/ &vccq_sdhi1; From patchwork Thu Sep 15 18:15:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 606633 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2A371C6FA89 for ; Thu, 15 Sep 2022 18:18:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230166AbiIOSSP (ORCPT ); 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Thu, 15 Sep 2022 11:17:38 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Date: Thu, 15 Sep 2022 19:15:57 +0100 Message-Id: <20220915181558.354737-10-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Add RISC-V architecture as part of ARM/Renesas architecture, as they have the same maintainers, use the same development collaboration infrastructure, and share many files. Signed-off-by: Lad Prabhakar --- v2->v3 * Merged as part of ARM v1->v2 * New patch --- MAINTAINERS | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index f5f17c50dac3..99483c13b91c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2665,7 +2665,7 @@ F: arch/arm/boot/dts/rtd* F: arch/arm/mach-realtek/ F: arch/arm64/boot/dts/realtek/ -ARM/RENESAS ARCHITECTURE +ARM/RISC-V/RENESAS ARCHITECTURE M: Geert Uytterhoeven M: Magnus Damm L: linux-renesas-soc@vger.kernel.org @@ -2686,6 +2686,7 @@ F: arch/arm/configs/shmobile_defconfig F: arch/arm/include/debug/renesas-scif.S F: arch/arm/mach-shmobile/ F: arch/arm64/boot/dts/renesas/ +F: arch/riscv/boot/dts/renesas/ F: drivers/soc/renesas/ F: include/linux/soc/renesas/ From patchwork Thu Sep 15 18:15:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prabhakar X-Patchwork-Id: 606634 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F9D3C6FA89 for ; Thu, 15 Sep 2022 18:18:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230054AbiIOSSM (ORCPT ); Thu, 15 Sep 2022 14:18:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38940 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230051AbiIOSRx (ORCPT ); Thu, 15 Sep 2022 14:17:53 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0F8B9F76F; Thu, 15 Sep 2022 11:17:41 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id n10so1523776wrw.12; Thu, 15 Sep 2022 11:17:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=xzoqzDtndDkISsSwTujowyDPoGXKL8jqH4hdlXLXrA0=; b=g5ulsbtE6DartTUDwK1K53pxs737iOAFvah1Hi8jK5pmVKn8KAVEf6OvssWURbZdFo dOSWToLwlaQwdJ18U4d1RedSFWSgxN+7k0AN5OqBda/cevb25gOLuTuI4LLibl9keWto N4Q825SAEdoOvDk6rXAoR/pJs7twaguzQCwGvopOeL3C4STOtA0O7SZgrNRYy1wyTxRZ 9jvDY4BZL8Srqk7Y+0B8Gc61zSI9T8yYmC2DmzFDp33WvqFBWINF5x4NaI7ujWuZuoTk DlNo+uDiS/xJUShEyQUfQ0UwDltURs02MR4sa1gaqN6zbcRSatsrYEFTxBqxt7dBSZ4p ay3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=xzoqzDtndDkISsSwTujowyDPoGXKL8jqH4hdlXLXrA0=; b=GKPuEmJ7jarW93RFlCuEp4Zld5Gey5ggZ7KxLAa6TIbtdhOiW/nlpBAkpPR3KXeuwa ikgLrjHTwdm6dWMqC28pkOpbKUkN6gTA5yMnTUK6wZeXtyK0TdKTGSYighwWwb4N6pgX p8dOWf3ku1j306Hw1X7GYI0LsigOSSEfad9+DjpUj4ffoJV0Y9Mz1QTtgXCtB2bsSppe M8LNRWJQFDCFe+GAyyZ/fHhNyMWhPFwHjabDCf6Uu/RGnRrTNUf0d9od5kPg5hVlW/l+ FZPitbH0WhUZo8p0KWT7j7ixUux38BeANgcE09UWKBOV7Oe4S799XDfcK3DRLyb7FeSN 75uw== X-Gm-Message-State: ACrzQf3wvL0zA8XdiWNBUpuxUSnKOyPQzB2qJlbEuPV9eM6u6PUTuySL 072nAEl3CP8mKQO0SaIbGToOyezcXG8YJQ== X-Google-Smtp-Source: AMsMyM7tjqwmJxX5D4dBi01RrRk+6JKiqTi1egw5XeegPGl6fRnFXsEXlXXpxAL3CklC75qxxfrBMg== X-Received: by 2002:a05:6000:384:b0:22a:5d05:c562 with SMTP id u4-20020a056000038400b0022a5d05c562mr579729wrf.701.1663265861500; Thu, 15 Sep 2022 11:17:41 -0700 (PDT) Received: from prasmi.home ([2a00:23c8:2501:c701:d411:a48b:4035:3d98]) by smtp.gmail.com with ESMTPSA id c11-20020a05600c0a4b00b003b47e8a5d22sm4243151wmq.23.2022.09.15.11.17.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 15 Sep 2022 11:17:40 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou Cc: Heiko Stuebner , Atish Patra , Conor Dooley , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-renesas-soc@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Lad Prabhakar Subject: [PATCH v3 10/10] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Date: Thu, 15 Sep 2022 19:15:58 +0100 Message-Id: <20220915181558.354737-11-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20220915181558.354737-1-prabhakar.mahadev-lad.rj@bp.renesas.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Lad Prabhakar Enable Renesas RZ/Five SoC config in defconfig. It allows the default upstream kernel to boot on RZ/Five SMARC EVK board. Alongside enable SERIAL_SH_SCI config so that the serial driver used by RZ/Five SoC is built-in. Signed-off-by: Lad Prabhakar Reviewed-by: Conor Dooley Reviewed-by: Geert Uytterhoeven --- v2->v3 * Included RB tags * Updated commit description v1->v2 * New patch --- arch/riscv/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 05fd5fcf24f9..3dd9aa4d707d 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -26,6 +26,7 @@ CONFIG_EXPERT=y # CONFIG_SYSFS_SYSCALL is not set CONFIG_PROFILING=y CONFIG_SOC_MICROCHIP_POLARFIRE=y +CONFIG_SOC_RENESAS_RZFIVE=y CONFIG_SOC_SIFIVE=y CONFIG_SOC_STARFIVE=y CONFIG_SOC_VIRT=y @@ -123,6 +124,7 @@ CONFIG_INPUT_MOUSEDEV=y CONFIG_SERIAL_8250=y CONFIG_SERIAL_8250_CONSOLE=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_SH_SCI=y CONFIG_VIRTIO_CONSOLE=y CONFIG_HW_RANDOM=y CONFIG_HW_RANDOM_VIRTIO=y