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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2022 09:56:48.0549 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf231c77-1de6-4266-a9d5-08da9637708e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR12MB5108 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org Create new SoC data structure for T23x platforms. StreamID programming is one of the additional feature added in Tegra234 and later chips Signed-off-by: Aniruddha Tvs Rao Signed-off-by: Prathamesh Shete --- drivers/mmc/host/sdhci-tegra.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 2d2d8260c681..a6c5bbae77b4 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1556,7 +1556,21 @@ static const struct sdhci_tegra_soc_data soc_data_tegra194 = { .max_tap_delay = 139, }; +static const struct sdhci_tegra_soc_data soc_data_tegra234 = { + .pdata = &sdhci_tegra186_pdata, + .dma_mask = DMA_BIT_MASK(39), + .nvquirks = NVQUIRK_NEEDS_PAD_CONTROL | + NVQUIRK_HAS_PADCALIB | + NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | + NVQUIRK_ENABLE_SDR50 | + NVQUIRK_ENABLE_SDR104 | + NVQUIRK_HAS_TMCLK, + .min_tap_delay = 95, + .max_tap_delay = 111, +}; + static const struct of_device_id sdhci_tegra_dt_match[] = { + { .compatible = "nvidia,tegra234-sdhci", .data = &soc_data_tegra234 }, { .compatible = "nvidia,tegra194-sdhci", .data = &soc_data_tegra194 }, { .compatible = "nvidia,tegra186-sdhci", .data = &soc_data_tegra186 }, { .compatible = "nvidia,tegra210-sdhci", .data = &soc_data_tegra210 }, From patchwork Wed Sep 14 09:56:26 2022 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2022 09:56:58.2112 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: edb13dc9-6eb1-4e80-c588-08da9637769e X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.161]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CO1NAM11FT107.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB6674 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org As per T23x MSS IAS SMMU clients are supposed to program streamid from their respective address spaces instead of MC override Define NVQUIRK_PROGRAM_MC_STREAMID and use it to program SMMU streamid from the SDMMC client address space Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete Reported-by: kernel test robot --- drivers/mmc/host/sdhci-tegra.c | 33 +++++++++++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index a6c5bbae77b4..b66b0cc51497 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -25,6 +25,7 @@ #include #include #include +#include #include @@ -94,6 +95,8 @@ #define SDHCI_TEGRA_AUTO_CAL_STATUS 0x1ec #define SDHCI_TEGRA_AUTO_CAL_ACTIVE BIT(31) +#define SDHCI_TEGRA_CIF2AXI_CTRL_0 0x1fc + #define NVQUIRK_FORCE_SDHCI_SPEC_200 BIT(0) #define NVQUIRK_ENABLE_BLOCK_GAP_DET BIT(1) #define NVQUIRK_ENABLE_SDHCI_SPEC_300 BIT(2) @@ -121,6 +124,7 @@ #define NVQUIRK_HAS_TMCLK BIT(10) #define NVQUIRK_HAS_ANDROID_GPT_SECTOR BIT(11) +#define NVQUIRK_PROGRAM_MC_STREAMID BIT(17) /* SDMMC CQE Base Address for Tegra Host Ver 4.1 and Higher */ #define SDHCI_TEGRA_CQE_BASE_ADDR 0xF000 @@ -177,6 +181,7 @@ struct sdhci_tegra { bool enable_hwcq; unsigned long curr_clk_rate; u8 tuned_tap_delay; + u32 streamid; }; static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) @@ -1564,6 +1569,7 @@ static const struct sdhci_tegra_soc_data soc_data_tegra234 = { NVQUIRK_DIS_CARD_CLK_CONFIG_TAP | NVQUIRK_ENABLE_SDR50 | NVQUIRK_ENABLE_SDR104 | + NVQUIRK_PROGRAM_MC_STREAMID | NVQUIRK_HAS_TMCLK, .min_tap_delay = 95, .max_tap_delay = 111, @@ -1637,6 +1643,7 @@ static int sdhci_tegra_probe(struct platform_device *pdev) struct sdhci_pltfm_host *pltfm_host; struct sdhci_tegra *tegra_host; struct clk *clk; + struct iommu_fwspec *fwspec; int rc; soc_data = of_device_get_match_data(&pdev->dev); @@ -1775,6 +1782,23 @@ static int sdhci_tegra_probe(struct platform_device *pdev) if (rc) goto err_add_host; + /* Program MC streamID for DMA transfers */ + if (soc_data->nvquirks & NVQUIRK_PROGRAM_MC_STREAMID) { + fwspec = dev_iommu_fwspec_get(&pdev->dev); + if (fwspec == NULL) { + rc = -ENODEV; + dev_err(mmc_dev(host->mmc), + "failed to get MC streamid: %d\n", + rc); + goto err_rst_get; + } else { + tegra_host->streamid = fwspec->ids[0] & 0xffff; + tegra_sdhci_writel(host, tegra_host->streamid | + (tegra_host->streamid << 8), + SDHCI_TEGRA_CIF2AXI_CTRL_0); + } + } + return 0; err_add_host: @@ -1861,6 +1885,8 @@ static int sdhci_tegra_suspend(struct device *dev) static int sdhci_tegra_resume(struct device *dev) { struct sdhci_host *host = dev_get_drvdata(dev); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); int ret; ret = mmc_gpio_set_cd_wake(host->mmc, false); @@ -1871,6 +1897,13 @@ static int sdhci_tegra_resume(struct device *dev) if (ret) return ret; + /* Re-program MC streamID for DMA transfers */ + if (tegra_host->soc_data->nvquirks & NVQUIRK_PROGRAM_MC_STREAMID) { + tegra_sdhci_writel(host, tegra_host->streamid | + (tegra_host->streamid << 8), + SDHCI_TEGRA_CIF2AXI_CTRL_0); + } + ret = sdhci_resume_host(host); if (ret) goto disable_clk; From patchwork Wed Sep 14 09:56:27 2022 Content-Type: text/plain; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2022 09:57:00.4610 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: a46eb5cb-645f-4b6d-d561-08da963777fa X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT079.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH2PR12MB4937 Precedence: bulk List-ID: X-Mailing-List: linux-mmc@vger.kernel.org In case of error condition to avoid system crash Tegra SDMMC controller requires CMD and DAT resets issued together. This is applicable to Tegra186 and later chips. Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete --- drivers/mmc/host/sdhci-tegra.c | 3 ++- drivers/mmc/host/sdhci.c | 11 ++++++++--- drivers/mmc/host/sdhci.h | 2 ++ 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index b66b0cc51497..7d16dc41fe91 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -1530,7 +1530,8 @@ static const struct sdhci_pltfm_data sdhci_tegra186_pdata = { SDHCI_QUIRK_NO_HISPD_BIT | SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN, - .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, + .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN | + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER, .ops = &tegra186_sdhci_ops, }; diff --git a/drivers/mmc/host/sdhci.c b/drivers/mmc/host/sdhci.c index 7689ffec5ad1..289fa8ae4866 100644 --- a/drivers/mmc/host/sdhci.c +++ b/drivers/mmc/host/sdhci.c @@ -3063,9 +3063,14 @@ static bool sdhci_request_done(struct sdhci_host *host) * Spec says we should do both at the same time, but Ricoh * controllers do not like that. */ - sdhci_do_reset(host, SDHCI_RESET_CMD); - sdhci_do_reset(host, SDHCI_RESET_DATA); - + if (host->quirks2 & + SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER) { + sdhci_do_reset(host, SDHCI_RESET_CMD | + SDHCI_RESET_DATA); + } else { + sdhci_do_reset(host, SDHCI_RESET_CMD); + sdhci_do_reset(host, SDHCI_RESET_DATA); + } host->pending_reset = false; } diff --git a/drivers/mmc/host/sdhci.h b/drivers/mmc/host/sdhci.h index 95a08f09df30..8045308f7859 100644 --- a/drivers/mmc/host/sdhci.h +++ b/drivers/mmc/host/sdhci.h @@ -480,6 +480,8 @@ struct sdhci_host { * block count. */ #define SDHCI_QUIRK2_USE_32BIT_BLK_CNT (1<<18) +/* Issue CMD and DATA reset together */ +#define SDHCI_QUIRK2_ISSUE_CMD_DAT_RESET_TOGETHER (1<<19) int irq; /* Device IRQ */ void __iomem *ioaddr; /* Mapped address */ From patchwork Wed Sep 14 09:56:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Prathamesh Shete X-Patchwork-Id: 606899 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93C0CECAAD8 for ; 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Wed, 14 Sep 2022 02:56:47 -0700 From: Prathamesh Shete To: , , , , , , , CC: , , , Subject: [PATCH v2 4/4] mmc: sdhci-tegra: Use actual clock rate for SW tuning correction Date: Wed, 14 Sep 2022 15:26:28 +0530 Message-ID: <20220914095628.26093-4-pshete@nvidia.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220914095628.26093-1-pshete@nvidia.com> References: <20220914095628.26093-1-pshete@nvidia.com> MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT036:EE_|DM6PR12MB4315:EE_ X-MS-Office365-Filtering-Correlation-Id: d82a5b9d-663a-4689-72b3-08da963779b6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: JOvDF4zpWm6YSXNHspdFiVCWu1P/m5XXbiGCurhX17OsXuDyfXMc6iKW7rIVH+jU5yoSG5cQj2awq30kXhfAvHQwxEJoMynEfhzeh5HhkYbHcz5a3huAQZ9yKmSdk1oS1m9PXtsHVVo2c1KC8gCBv042Eyezy+RDSg5yN8j3DluZjyFUSNrHiLSoqA13dNYlkVXFoPNvTmk4i3A+Za8hKL+vVHkiJUshPgi791gt3JxuYtRAjseYtEr8EW1zE8wxuPOaW0Mdy/IjErMzPzCbvKsfSd0c7UKy60idIX1hehjwz39x1uww1403FEYdHKaKPknntVOZRH0QvFTzySDVEY+JOGztzRNqrU8yJbETFd6EYiDk70X3ypFW1C3/PMDVAHdYBQn/XDEWcBq6RfK7sRaNWvzKZVhNjZg+x1++M+vzQ3HxXOtRxG696XVE1CZtHLNMso3JKKsa+/iRKH1Me3BQ+A24d1NziJOf6M0T14to9woHOxMDS2xdRMFC7NjeEH7tiRuCRNvBksQm2mAVmaKof4mEJh4EETiKDa3Wsn1p8TQvZcPntO9Ovwu6zQU2qRFLqEoIWdl/AQvtS/kqW8chkSSwS5eThf7+ie2PAFS8lvMKqwkdW2x1sYbu2jaRTIC8KUB9NY/2G+IAysUbTi8bqZKEuUtmjlgXVpWeyCZq1okfuhzENytYNOnRS0KRG3L6SKPCathtIjOlNSrhwCuUIt2TBMvPXuYFi3pLFWTv4uxQ22uZpaeAGpqFErSVUB9/nGj+yxmm1lln9/4vgg== X-Forefront-Antispam-Report: CIP:216.228.117.160; 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Fixes: ea8fc5953e8b ("mmc: tegra: update hw tuning process") Signed-off-by: Aniruddha TVS Rao Signed-off-by: Prathamesh Shete --- drivers/mmc/host/sdhci-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index 7d16dc41fe91..42b018d4ebc3 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -778,7 +778,7 @@ static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) dev_err(dev, "failed to set clk rate to %luHz: %d\n", host_clk, err); - tegra_host->curr_clk_rate = host_clk; + tegra_host->curr_clk_rate = clk_get_rate(pltfm_host->clk); if (tegra_host->ddr_signaling) host->max_clk = host_clk; else