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Wed, 14 Sep 2022 16:44:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT073.mail.protection.outlook.com (10.13.177.231) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5632.12 via Frontend Transport; Wed, 14 Sep 2022 16:44:56 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 14 Sep 2022 11:44:52 -0500 From: Arvind Yadav To: , , , , , , , , , , , , CC: Arvind Yadav , =?utf-8?q?Christian_K=C3=B6nig?= Subject: [PATCH v4 2/6] dma-buf: set signaling bit for the stub fence Date: Wed, 14 Sep 2022 22:13:17 +0530 Message-ID: <20220914164321.2156-3-Arvind.Yadav@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914164321.2156-1-Arvind.Yadav@amd.com> References: <20220914164321.2156-1-Arvind.Yadav@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT073:EE_|MW4PR12MB7013:EE_ X-MS-Office365-Filtering-Correlation-Id: 3c6c9833-ff8a-4ebe-57a3-08da967074ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(136003)(346002)(396003)(39860400002)(376002)(451199015)(40470700004)(36840700001)(46966006)(47076005)(82740400003)(81166007)(36756003)(356005)(426003)(921005)(336012)(316002)(2616005)(40480700001)(82310400005)(1076003)(6666004)(2906002)(8676002)(40460700003)(110136005)(66574015)(70206006)(186003)(7696005)(83380400001)(26005)(478600001)(86362001)(54906003)(41300700001)(70586007)(16526019)(5660300002)(4326008)(36860700001)(8936002)(83996005)(36900700001)(2101003); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2022 16:44:56.4438 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3c6c9833-ff8a-4ebe-57a3-08da967074ba X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT073.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW4PR12MB7013 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Here's setting software signaling bit for the stub fence which is always signaled. If this fence signaling bit is not set then the AMD GPU scheduler will cause a GPU reset due to a GPU scheduler cleanup activity timeout. Signed-off-by: Arvind Yadav Reviewed-by: Christian König --- Changes in v1 : 1- Addressing Christian's comment to remove unnecessary callback. 2- Replacing CONFIG_DEBUG_WW_MUTEX_SLOWPATH instead of CONFIG_DEBUG_FS. 3- The version of this patch is also changed and previously it was [PATCH 3/4] Changes in v2 : 1 - perviously using __dma_fence_enable_signaling() for enable signaling. 2 - #ifdef CONFIG_DEBUG_WW_MUTEX_SLOWPATH removed Changes in v3 : 1 - Enable Signaling bit for dma_fence_allocate_private_stub. --- drivers/dma-buf/dma-fence.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 64c99739ad23..645c158b7e01 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -136,6 +136,10 @@ struct dma_fence *dma_fence_get_stub(void) &dma_fence_stub_ops, &dma_fence_stub_lock, 0, 0); + + set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, + &dma_fence_stub.flags); + dma_fence_signal_locked(&dma_fence_stub); } spin_unlock(&dma_fence_stub_lock); @@ -161,6 +165,10 @@ struct dma_fence *dma_fence_allocate_private_stub(void) &dma_fence_stub_ops, &dma_fence_stub_lock, 0, 0); + + set_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, + &dma_fence_stub.flags); + dma_fence_signal(fence); return fence; From patchwork Wed Sep 14 16:43:19 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Arvind Yadav X-Patchwork-Id: 606026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19670ECAAD3 for ; Wed, 14 Sep 2022 16:45:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230107AbiINQp1 (ORCPT ); Wed, 14 Sep 2022 12:45:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229750AbiINQpU (ORCPT ); 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Wed, 14 Sep 2022 11:45:05 -0500 From: Arvind Yadav To: , , , , , , , , , , , , CC: Arvind Yadav Subject: [PATCH v4 4/6] dma-buf: dma_fence_wait must enable signaling Date: Wed, 14 Sep 2022 22:13:19 +0530 Message-ID: <20220914164321.2156-5-Arvind.Yadav@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914164321.2156-1-Arvind.Yadav@amd.com> References: <20220914164321.2156-1-Arvind.Yadav@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT110:EE_|CY8PR12MB7657:EE_ X-MS-Office365-Filtering-Correlation-Id: d893f585-94e8-4633-6294-08da96707c87 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: Px3CnwKFXlejpA705iuXXqHEEdF7Kb9tMBIdNiMfQDw3iWla62y60C7n2rtDQme5jOM5Fsw4ko5oVYTmnKEJ+KA9EvzxvFGS13DdwtVe3rwIVVh7i1eKPfZ5uDYDJ5/yCI3roeiiXVmnf5WD5ywXX3+3ilzM2WKqlB6tiKR94VoKIq96cCUjuVcFJY1hOXJEwE/hcvuc93Mm0FP2MhNtQRxkZhrLFxga3qrKpKWqXUCcHFxopYr9X9mNL3SvYAUKV3WzUDWMZMS2MMPXAy5THOvE4snFJg2RNkGX3EpK1j+NAqhYXM+T8gcnVVrcK66t07vtm972twCsrnIzZvvIWc5HATgd0Fxyctniwwsz0rWYUCnCfivIlKr1Jg8iWijFETVAw5/nxhImE0WTaJ9eFHoicrzFM7dbJZByCajSw0D0C2SJnP4rCSjd6RytH61D276sRho1OYklyBagjeEZwFa18aocKUZ391mH/25fjsJmNP3JLWX+cD5UODGXYp43T8+QvlMsy/eH9VTP5ZRl3voyqe+SmfhdFfgfl58IygHV6YpRUxxBXAwB8oHsgZEyaHQY+1iGKt8TvCp3S0RDc5kJ7rxiqR6Jyj9E52eCv2G0RTC/ayRYFgIlwMWWKWLHEUtQHjAV0B1gAKwvkwafbjPYRypU5wccvp6iKW5dM99Qo0o3xhKHbxht63/zPL7oENz8oEV2O/CnILqVmnxTajGdto0j8cC3W9hoLtsFg5yrOAFZC4ebuQABQ6AJWLvlM062fVEMb5FU1w6bFIFMC1GtDcNxrYEr/4qmqwKBF2uSaRmGIDwMnpGF//HBZhV8barTQtmySep5vo/sHfRPRKu85KV0JOAFymPdNaUG+zrwom/Zz8UCMNQcM+jQE47p X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(346002)(376002)(39860400002)(136003)(396003)(451199015)(40470700004)(36840700001)(46966006)(40460700003)(6666004)(356005)(8936002)(16526019)(316002)(110136005)(47076005)(70586007)(478600001)(336012)(1076003)(36756003)(70206006)(36860700001)(86362001)(2906002)(41300700001)(2616005)(83380400001)(426003)(7696005)(4326008)(81166007)(4744005)(82740400003)(26005)(5660300002)(186003)(82310400005)(40480700001)(921005)(8676002)(2101003)(36900700001)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2022 16:45:09.5472 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: d893f585-94e8-4633-6294-08da96707c87 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT110.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY8PR12MB7657 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org dma_fence_wait() should always enable signaling even when the fence is already signaled. Signed-off-by: Arvind Yadav --- Changes in v1..v3: This new patch was not part of previous series. --- drivers/dma-buf/dma-fence.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/drivers/dma-buf/dma-fence.c b/drivers/dma-buf/dma-fence.c index 645c158b7e01..a5fbf1c1e0ea 100644 --- a/drivers/dma-buf/dma-fence.c +++ b/drivers/dma-buf/dma-fence.c @@ -508,6 +508,8 @@ dma_fence_wait_timeout(struct dma_fence *fence, bool intr, signed long timeout) __dma_fence_might_wait(); + dma_fence_enable_sw_signaling(fence); + trace_dma_fence_wait_start(fence); if (fence->ops->wait) ret = fence->ops->wait(fence, intr, timeout); @@ -771,9 +773,6 @@ dma_fence_default_wait(struct dma_fence *fence, bool intr, signed long timeout) goto out; } - if (!__dma_fence_enable_signaling(fence)) - goto out; - if (!timeout) { ret = 0; goto out; From patchwork Wed Sep 14 16:43:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Arvind Yadav X-Patchwork-Id: 606025 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26D09ECAAD3 for ; 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Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BN8NAM11FT072.mail.protection.outlook.com (10.13.176.165) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.5632.12 via Frontend Transport; Wed, 14 Sep 2022 16:45:24 +0000 Received: from amd.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.28; Wed, 14 Sep 2022 11:45:19 -0500 From: Arvind Yadav To: , , , , , , , , , , , , CC: Arvind Yadav Subject: [PATCH v4 6/6] dma-buf: Check status of enable-signaling bit on debug Date: Wed, 14 Sep 2022 22:13:21 +0530 Message-ID: <20220914164321.2156-7-Arvind.Yadav@amd.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220914164321.2156-1-Arvind.Yadav@amd.com> References: <20220914164321.2156-1-Arvind.Yadav@amd.com> MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN8NAM11FT072:EE_|SA1PR12MB7341:EE_ X-MS-Office365-Filtering-Correlation-Id: 77829df5-388c-4f70-88aa-08da96708531 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230022)(4636009)(376002)(136003)(39860400002)(346002)(396003)(451199015)(40470700004)(36840700001)(46966006)(41300700001)(82310400005)(356005)(70206006)(86362001)(8676002)(81166007)(4326008)(7696005)(6666004)(47076005)(40460700003)(316002)(40480700001)(186003)(70586007)(426003)(110136005)(2906002)(16526019)(336012)(5660300002)(36860700001)(26005)(921005)(1076003)(82740400003)(8936002)(83380400001)(478600001)(2616005)(36756003)(2101003)(36900700001)(83996005); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Sep 2022 16:45:24.0841 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 77829df5-388c-4f70-88aa-08da96708531 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN8NAM11FT072.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB7341 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Fence signaling must be enabled to make sure that the dma_fence_is_signaled() function ever returns true. Since drivers and implementations sometimes mess this up, this ensures correct behaviour when DMABUF_DEBUG_ENABLE_SIGNALING is used during debugging. This should make any implementation bugs resulting in not signaled fences much more obvious. Signed-off-by: Arvind Yadav --- Changes in v1,v2 : 1- Addressing Christian's comment to replace CONFIG_DEBUG_WW_MUTEX_SLOWPATH instead of CONFIG_DEBUG_FS. 2- As per Christian's comment moving this patch at last so The version of this patch is also changed and previously it was [PATCH 1/4] Changes in v3: 1 - Adding new config DMABUF_DEBUG_ENABLE_SIGNALING. 2 - Replace CONFIG_DEBUG_WW_MUTEX_SLOWPATH to new CONFIG_DMABUF_DEBUG_ENABLE_SIGNALING. --- drivers/dma-buf/Kconfig | 7 +++++++ include/linux/dma-fence.h | 5 +++++ 2 files changed, 12 insertions(+) diff --git a/drivers/dma-buf/Kconfig b/drivers/dma-buf/Kconfig index e4dc53a36428..c991e6a51510 100644 --- a/drivers/dma-buf/Kconfig +++ b/drivers/dma-buf/Kconfig @@ -65,6 +65,13 @@ config DMABUF_SELFTESTS default n depends on DMA_SHARED_BUFFER +config DMABUF_DEBUG_ENABLE_SIGNALING + bool "DMA Fence enable signaling debug checks" + default n + depends on DMA_SHARED_BUFFER + help + This option enables additional checks for software signaling of fence. + menuconfig DMABUF_HEAPS bool "DMA-BUF Userland Memory Heaps" select DMA_SHARED_BUFFER diff --git a/include/linux/dma-fence.h b/include/linux/dma-fence.h index 775cdc0b4f24..01e1fa4d3cec 100644 --- a/include/linux/dma-fence.h +++ b/include/linux/dma-fence.h @@ -428,6 +428,11 @@ dma_fence_is_signaled_locked(struct dma_fence *fence) static inline bool dma_fence_is_signaled(struct dma_fence *fence) { +#ifdef CONFIG_DMABUF_DEBUG_ENABLE_SIGNALING + if (!test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, &fence->flags)) + return false; +#endif + if (test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &fence->flags)) return true;