From patchwork Tue Sep 13 14:21:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 605676 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5E1FC6FA8B for ; Tue, 13 Sep 2022 15:52:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235324AbiIMPwH (ORCPT ); Tue, 13 Sep 2022 11:52:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57724 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234356AbiIMPvu (ORCPT ); Tue, 13 Sep 2022 11:51:50 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 409D08E0E2; Tue, 13 Sep 2022 07:53:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663080830; x=1694616830; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=pLJ8priI7RmY67VypJNLPFkfcfxWAxaQ7nFJHrNbVhI=; b=neolalmZlbeg0Cd8OmeZQeOnG7uEwFZyCMvomSBD5w15HJAPJteumXOU +P/h8/TjVldCi8NOYeEkYmZ8KlbaIdTd33EhmwDfrBYYCJ2aUf8xXKdDC aMcXqXjBCuFx7ntVH94TqY0k3ryLCX6sursai79XeQYOXeWfATUVVLYo6 Km5auT4V1i9fB3gtyoFwrZOMc2gue0T0Qq1IUBXcxsp3ooV9oG927Rgog cyzBjpgRRJ4Uc+vKYDZ2IxWx4AhSU4X4Qz6o7rcQekwTQf5h1jHdlaXxD Nvspvsl03zKeLVsGm4rxzhv34QgbXbJuyg6LQio0SAt3Vbz0LMo4S46S4 w==; X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="190643859" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Sep 2022 07:24:55 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 13 Sep 2022 07:24:55 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 13 Sep 2022 07:24:50 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v3 02/14] ARM: dts: at91: sam9x60ek: Add DBGU compatibles to uart1 Date: Tue, 13 Sep 2022 17:21:54 +0300 Message-ID: <20220913142205.162399-3-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220913142205.162399-1-sergiu.moga@microchip.com> References: <20220913142205.162399-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Maintain consistency among the compatibles of the serial nodes of sam9x60ek and highlight the incremental characteristic of its serial IP's by making sure that all serial nodes contain both the sam9x60 and sam9260 usart/dbgu compatibles. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Nothing, previously this was [PATCH 4] arch/arm/boot/dts/at91-sam9x60ek.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/at91-sam9x60ek.dts b/arch/arm/boot/dts/at91-sam9x60ek.dts index 7ade9979e1c6..67bce8d60908 100644 --- a/arch/arm/boot/dts/at91-sam9x60ek.dts +++ b/arch/arm/boot/dts/at91-sam9x60ek.dts @@ -258,7 +258,7 @@ &flx5 { status = "okay"; uart1: serial@200 { - compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart"; + compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart"; reg = <0x200 0x200>; interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; dmas = <&dma0 From patchwork Tue Sep 13 14:21:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 605675 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0807C6FA8B for ; Tue, 13 Sep 2022 15:52:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235956AbiIMPwt (ORCPT ); Tue, 13 Sep 2022 11:52:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37288 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233076AbiIMPwV (ORCPT ); Tue, 13 Sep 2022 11:52:21 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3C3D08E0C6; Tue, 13 Sep 2022 07:54:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663080846; x=1694616846; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RciFByXsjP8F/vnPuZ08wV7/HdHLctza/kpMMpKQnxU=; b=PydzhTdh9nflu2xk0JKzUpIqxLK8B26LP3ziOQ0n4iQRwEiat/s/YIu8 6SBLSShDyi9q0T87O56CEdW1z6/CMZhSG9ARRjGdBQnMoNiBkMEhrEavf y5xGvVmFmqlYxWtDEYuVKzal8bVJyvhpZdvbc9kdL4wt1qMt1cFvM+Q63 YwOWT82HnZLdLTOq4ow1wOpGPcXz8eIOafnt5yfa9E+4Du/CVQfjdcZzl y5RrZcU6Lh8XQPmdAfJeOb7XF/sJlF3mOij3+mhY1gxFzNwia0+JdtfX1 IMps9iP2EHy0nXwwZU4sYc+t4NoivJuaj9mwG4s3U+gjTKw8urHXn3ZjZ g==; X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="190644030" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Sep 2022 07:25:16 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 13 Sep 2022 07:25:05 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 13 Sep 2022 07:25:00 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , , "Krzysztof Kozlowski" Subject: [PATCH v3 04/14] spi: dt-bindings: atmel,at91rm9200-spi: Add DMA related properties Date: Tue, 13 Sep 2022 17:21:56 +0300 Message-ID: <20220913142205.162399-5-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220913142205.162399-1-sergiu.moga@microchip.com> References: <20220913142205.162399-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org The DT nodes of the SPI IP's may contain DMA related properties so make sure that the binding is able to properly validate those as well by making it aware of these optional properties. Signed-off-by: Sergiu Moga Acked-by: Mark Brown Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - added Acked-by tags .../devicetree/bindings/spi/atmel,at91rm9200-spi.yaml | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml index d85d54024b2e..4dd973e341e6 100644 --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml @@ -34,6 +34,16 @@ properties: clocks: maxItems: 1 + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + atmel,fifo-size: $ref: /schemas/types.yaml#/definitions/uint32 description: | From patchwork Tue Sep 13 14:22:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 605674 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAA22C6FA86 for ; Tue, 13 Sep 2022 15:53:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233691AbiIMPxw (ORCPT ); Tue, 13 Sep 2022 11:53:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58198 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234688AbiIMPxE (ORCPT ); Tue, 13 Sep 2022 11:53:04 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ECB3DD5A; Tue, 13 Sep 2022 07:54:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663080870; x=1694616870; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HJ21i8WyvavSW1Rex/vM3PxZNjMJUVVOLwpNbp1oD2g=; b=D/TpzObeehMyiEvzn+m90SnhRQEgr496q2p1e0TlBA6lm6wrWmPW5Lsh Ou7IdAawt06H3ZoGY9wWiWBlmvr7tKi/bsvlAqk7RwYfu56fhPeBMTGiP XKhdJQNZQKvF4XehKqW02ICkvjM4qkWIXbmw3UgOSOSke8ESKoEU2o7Ia lVW5QRJUtLhnZ5WTEBgQ97xjXbrQh9xgRl4ejbDvaIW62IqqO16N0Vik8 mKJmhseEOjQcNjwGGsh5ouQ/eAW49cpyagqJkSVfi9FiuJ8RSp7LETNBu KBmlqn7cjSw06ai4xe+cq7+5+Yz08TQpoBppVmx8X++4zboJByLQq/IEP w==; X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="190644072" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Sep 2022 07:25:28 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 13 Sep 2022 07:25:27 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 13 Sep 2022 07:25:22 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v3 08/14] dt-bindings: mfd: atmel,sama5d2-flexcom: Add USART child node ref binding Date: Tue, 13 Sep 2022 17:22:00 +0300 Message-ID: <20220913142205.162399-9-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220913142205.162399-1-sergiu.moga@microchip.com> References: <20220913142205.162399-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org FLEXCOM, among other functionalities, has the ability to offer the USART serial communication protocol. To have the FLEXCOM binding properly validate its USART children nodes, we must reference the correct binding. To differentiate between the SPI of FLEXCOM and the SPI of USART in SPI mode, use the compatible string. Signed-off-by: Sergiu Moga Acked-by: Krzysztof Kozlowski --- v1 -> v2: - Nothing v2 -> v3: - Previously [PATCH 7] - Compare devices based on the compatible instead of the clock .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 0db0f2728b65..0467dfcf7db5 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -72,13 +72,21 @@ properties: patternProperties: "^serial@[0-9a-f]+$": - type: object + $ref: /schemas/serial/atmel,at91-usart.yaml description: - Child node describing USART. See atmel-usart.txt for details - of USART bindings. + Child node describing USART. "^spi@[0-9a-f]+$": - $ref: /schemas/spi/atmel,at91rm9200-spi.yaml + allOf: + - if: + properties: + compatible: + contains: + const: atmel,at91sam9260-usart + then: + $ref: /schemas/serial/atmel,at91-usart.yaml + else: + $ref: /schemas/spi/atmel,at91rm9200-spi.yaml description: Child node describing SPI. From patchwork Tue Sep 13 14:22:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 605673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42339C6FA86 for ; Tue, 13 Sep 2022 15:54:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232514AbiIMPyj (ORCPT ); Tue, 13 Sep 2022 11:54:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234208AbiIMPyD (ORCPT ); Tue, 13 Sep 2022 11:54:03 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF97F4DB0D; Tue, 13 Sep 2022 07:55:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663080904; x=1694616904; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=kN3hTzrmK/rsYNCiYsS5F3DbrNzaUjVvJ04I3YcEG8E=; b=mwbq0yCIvxF0LqIx9nFxCVc7FD+v+3jPOQ0jrtuF9CeD16XzxA/7u2Qv po7bgg1AuqZQGgfnma7HwvG1yu1OdsWhWDYWBd4c7YqRgvR4mrOxCF3Do A5JYef5swKhunAPW+VE3e4cbqQbGQmjzX5uO62BFtgklpYelYY2J0YC+A LYHXpf4tKFLhQlOO93jJSWYzxbfM0RnhkYPurwulvO109BYjUi/JREZnx ibiq+zoDD+kESRcjBDECU3zzZ0d+V5iky7LkIC5T9mFxUncnmdwcXAbpT 0rRHGLOveYyJAsiBS+Fsu0hmiKaiAj7OCxUhNL00HgwpWwwwPp3CkNm4F A==; X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="190644106" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Sep 2022 07:25:33 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 13 Sep 2022 07:25:32 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 13 Sep 2022 07:25:27 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v3 09/14] dt-bindings: serial: atmel, at91-usart: Add gclk as a possible USART clock Date: Tue, 13 Sep 2022 17:22:01 +0300 Message-ID: <20220913142205.162399-10-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220913142205.162399-1-sergiu.moga@microchip.com> References: <20220913142205.162399-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org The Devicetree nodes for FLEXCOM's USART can also have an alternative clock source for the baudrate generator (other than the peripheral clock), namely the Generick Clock. Thus make the binding aware of this clock that someone may place in the clock related properties of the USART node. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Previously this was [PATCH 13] .../devicetree/bindings/serial/atmel,at91-usart.yaml | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml index 4da642763bef..30b2131b5860 100644 --- a/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml +++ b/Documentation/devicetree/bindings/serial/atmel,at91-usart.yaml @@ -36,10 +36,16 @@ properties: maxItems: 1 clock-names: - const: usart + minItems: 1 + items: + - const: usart + - const: gclk clocks: - maxItems: 1 + minItems: 1 + items: + - description: USART Peripheral Clock + - description: USART Generic Clock dmas: items: From patchwork Tue Sep 13 14:22:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 605671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BA5F1ECAAD8 for ; Tue, 13 Sep 2022 16:55:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231684AbiIMQzD (ORCPT ); Tue, 13 Sep 2022 12:55:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45594 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231775AbiIMQyc (ORCPT ); Tue, 13 Sep 2022 12:54:32 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A1E02C0B68; Tue, 13 Sep 2022 08:47:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663084045; x=1694620045; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=z/YKByiaIlpU8pE5yj2eqLLdZWkiyu84ffoyl6Fiz44=; b=exGiSpZySfkoQtAtkzzY4CiEVQiBrKqCuFjT80ZR4ZHFit+nAKfZTSV2 IsI6MM/IWzzsP8mmE/SWNCu1atpAU7PENP/hM2lc1E7Gv7KXw0Jj9xEBC 5/1ToN5sxUtawyR4jEs3z34Th/TDkg95i+QzBxBKKwlEV2Ao3dITM12IH 9oGyZK2Kbs7AWeG5k1rC32ZKqfMrBqtwN8mnOpypLmNE63Aav8jyr2pwV wRYU5Zm01qpoTxGDEXcziLYcyz/tuSq4IFHdKhtWUUhTjby1Bguj3o3d9 BwJLnsEFhgIeuDQvJ5A6tKhEYqupeJmEYb44JnX+tFSn0yEw+5EbTON4d Q==; X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="176926450" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Sep 2022 07:25:47 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 13 Sep 2022 07:25:43 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 13 Sep 2022 07:25:38 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v3 11/14] tty: serial: atmel: Define BRSRCCK bitmask of UART IP's Mode Register Date: Tue, 13 Sep 2022 17:22:03 +0300 Message-ID: <20220913142205.162399-12-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220913142205.162399-1-sergiu.moga@microchip.com> References: <20220913142205.162399-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add definitions for the Baud Rate Source Clock bitmask of the Mode Register of UART IP's and its bitfields. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before v2 -> v3: - Previously this was [PATCH 11] drivers/tty/serial/atmel_serial.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 70d0611e56fd..ed64035ba6c3 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -68,6 +68,9 @@ #define ATMEL_US_NBSTOP_1 (0 << 12) #define ATMEL_US_NBSTOP_1_5 (1 << 12) #define ATMEL_US_NBSTOP_2 (2 << 12) +#define ATMEL_UA_BRSRCCK GENMASK(13, 12) /* Clock Selection for UART */ +#define ATMEL_UA_BRSRCCK_PERIPH_CLK (0 << 12) +#define ATMEL_UA_BRSRCCK_GCLK (1 << 12) #define ATMEL_US_CHMODE GENMASK(15, 14) /* Channel Mode */ #define ATMEL_US_CHMODE_NORMAL (0 << 14) #define ATMEL_US_CHMODE_ECHO (1 << 14) From patchwork Tue Sep 13 14:22:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 605678 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 893DBC6FA82 for ; Tue, 13 Sep 2022 14:59:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234756AbiIMO7v (ORCPT ); Tue, 13 Sep 2022 10:59:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235119AbiIMO7Q (ORCPT ); Tue, 13 Sep 2022 10:59:16 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 263457434D; Tue, 13 Sep 2022 07:28:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663079318; x=1694615318; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=IAvz+EPRVJUa2sWHwWF/4LgxqmMeTJl/Cd8xvZqLdzA=; b=DuTbcKJYCsBH6ALs5uDL8+qarqKM5HvWdZNN6iI/25wCqslpsH2tLj+E 6nKlsuqMLNus1lEWxuMR4n2eOyUEyz+tFookFS+x81/ihjSZnzhfwkfP8 J2Loona3UkR70WkyqrxcCgZ24G3W0Erm5ek5h3KdRri79GklhgsDy1MxA gUAVAIyT+YW16Y/pVU4aIvtR/1Ce/sIlemfReBsZMyvDvgzTunLFAiHt3 pYqZ5iCqckpHAUorNmkEvoYmogQtD23WycXwafSlWp+u7EDzDsCue+/JR O99jzO4Wti0ii61nRu7IxDIFzQa4Ab3bghg9fzT7ARm3z5GpzhipD/ilk A==; X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="180313680" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Sep 2022 07:25:57 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 13 Sep 2022 07:25:48 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 13 Sep 2022 07:25:43 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v3 12/14] tty: serial: atmel: Only divide Clock Divisor if the IP is USART Date: Tue, 13 Sep 2022 17:22:04 +0300 Message-ID: <20220913142205.162399-13-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220913142205.162399-1-sergiu.moga@microchip.com> References: <20220913142205.162399-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Make sure that the driver only divides the clock divisor if the IP handled at that point is USART, since UART IP's do not support implicit peripheral clock division. Instead, in the case of UART, go with the highest possible clock divisor. Signed-off-by: Sergiu Moga --- v1 -> v2: - Nothing, this patch was not here before and is mainly meant as both cleanup and as a way to introduce a new field into struct atmel_uart_port that will be used by the last patch to diferentiate between USART and UART regarding the location of the Baudrate Clock Source bitmask. v2 -> v3: - Use ATMEL_US_CD instead of 65535 - Previously [PATCH 10] drivers/tty/serial/atmel_serial.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index ab4a9dfae07d..ad7483230090 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -150,6 +150,7 @@ struct atmel_uart_port { u32 rts_low; bool ms_irq_enabled; u32 rtor; /* address of receiver timeout register if it exists */ + bool is_usart; bool has_frac_baudrate; bool has_hw_timer; struct timer_list uart_timer; @@ -1825,6 +1826,7 @@ static void atmel_get_ip_name(struct uart_port *port) */ atmel_port->has_frac_baudrate = false; atmel_port->has_hw_timer = false; + atmel_port->is_usart = false; if (name == new_uart) { dev_dbg(port->dev, "Uart with hw timer"); @@ -1834,6 +1836,7 @@ static void atmel_get_ip_name(struct uart_port *port) dev_dbg(port->dev, "Usart\n"); atmel_port->has_frac_baudrate = true; atmel_port->has_hw_timer = true; + atmel_port->is_usart = true; atmel_port->rtor = ATMEL_US_RTOR; version = atmel_uart_readl(port, ATMEL_US_VERSION); switch (version) { @@ -1863,6 +1866,7 @@ static void atmel_get_ip_name(struct uart_port *port) dev_dbg(port->dev, "This version is usart\n"); atmel_port->has_frac_baudrate = true; atmel_port->has_hw_timer = true; + atmel_port->is_usart = true; atmel_port->rtor = ATMEL_US_RTOR; break; case 0x203: @@ -2283,10 +2287,21 @@ static void atmel_set_termios(struct uart_port *port, cd = uart_get_divisor(port, baud); } - if (cd > 65535) { /* BRGR is 16-bit, so switch to slower clock */ + /* + * If the current value of the Clock Divisor surpasses the 16 bit + * ATMEL_US_CD mask and the IP is USART, switch to the Peripheral + * Clock implicitly divided by 8. + * If the IP is UART however, keep the highest possible value for + * the CD and avoid needless division of CD, since UART IP's do not + * support implicit division of the Peripheral Clock. + */ + if (atmel_port->is_usart && cd > ATMEL_US_CD) { cd /= 8; mode |= ATMEL_US_USCLKS_MCK_DIV8; + } else { + cd &= ATMEL_US_CD; } + quot = cd | fp << ATMEL_US_FP_OFFSET; if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) From patchwork Tue Sep 13 14:22:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 605677 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D255C6FA82 for ; Tue, 13 Sep 2022 15:01:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234755AbiIMPBV (ORCPT ); Tue, 13 Sep 2022 11:01:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234821AbiIMO7x (ORCPT ); Tue, 13 Sep 2022 10:59:53 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1764F12759; Tue, 13 Sep 2022 07:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1663079351; x=1694615351; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4JmDRlnwM3eagYZBbdfsG68lq5CHJB8sXvup6gdh2I4=; b=eKW1ijCESRTFAMIuBia6+WP+IjEUjFZZdrVo6eQ5F4wBpG9aGcomwKzS LfzQ+vRc9tOoJgTkXDD6Eeps4DZO2oOD/ntqpPa7gPAddc4sNx/l2jZE3 3LmVJ45Bf3BYM8zSfDDyMspcL7FpZv8JEZNURQQ7wu0xacKPkjIqMAl+I gMbsEH1nSfYByiezSq8cX4rbum9YtAppRF81QL4EbeYWgrAJgk8oIpuzU Z5frMqjb9U+eBHiDgmmWnxS/VHAKP0YF5Fa5ip39bFDlVg40vs5kw0HgI H1S1DUN7mvTS3jZCKDHgGKCbQAcuYL0cpqEeQZrH5ShcvA596hgkRg+GS w==; X-IronPort-AV: E=Sophos;i="5.93,313,1654585200"; d="scan'208";a="180313694" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 13 Sep 2022 07:25:59 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 13 Sep 2022 07:25:53 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 13 Sep 2022 07:25:48 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , , , , CC: , , , , , Subject: [PATCH v3 13/14] clk: at91: sama5d2: Add Generic Clocks for UART/USART Date: Tue, 13 Sep 2022 17:22:05 +0300 Message-ID: <20220913142205.162399-14-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220913142205.162399-1-sergiu.moga@microchip.com> References: <20220913142205.162399-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add the generic clocks for UART/USART in the sama5d2 driver to allow them to be registered in the Common Clock Framework. Signed-off-by: Sergiu Moga Reviewed-by: Claudiu Beznea --- v1 -> v2: - Added R-b tag v2 -> v3: - Nothing drivers/clk/at91/sama5d2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index cfd0f5e23b99..84156dc52bff 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -120,6 +120,16 @@ static const struct { struct clk_range r; int chg_pid; } sama5d2_gck[] = { + { .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart3_gclk", .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart4_gclk", .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, }, { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, }, { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, },