From patchwork Sat Sep 10 12:46:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 604577 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 74662C6FA86 for ; Sat, 10 Sep 2022 12:47:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229624AbiIJMrJ (ORCPT ); Sat, 10 Sep 2022 08:47:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229531AbiIJMrI (ORCPT ); Sat, 10 Sep 2022 08:47:08 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5BF7857574 for ; Sat, 10 Sep 2022 05:47:06 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id a8so7207307lff.13 for ; Sat, 10 Sep 2022 05:47:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=6R7WdKZZGEgnNPp4io9kbt+uAo7Q6dEP5JcdXxDYq1o=; b=OT851iS7+6MvGfXmA2BERCoBRLb9X0irEqAVYuN+RblIcXjlK23Gw0VOaVfxepUond bgTA8V0j/autRRsr9EKk/7oOLVBMMpDYnTrr/eFXMr62tkpGJpJGD1K/zZBrcVZz5iMi 9jzAdOF7uxxfOH+UAJDES2EX1j2SrGBEjCrajyhXSm7zLlXd0n+dthfL+1xjRuIQLFVL I1FE76xT3x8M11KULPPmKaTqZLpTtuc09FGyWQjMgEIl6v/FoSrT316RjYVttN9Laymp G7rnHE6YcrwDhveHTRGuOWBoO6n0WYwrWakcgcAPktdgo9F7nrtLZGhoyPS9dPr97z5o ZFvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=6R7WdKZZGEgnNPp4io9kbt+uAo7Q6dEP5JcdXxDYq1o=; b=RZ6zTVx2h1uuG07Jp7A5UNwmdfFG9zvXYqcqOzDikSyDqig6MiW005Y+AlPKN5ejPI Jxj4A5q/H24i1PjwBAE5s3LtGPxw3MHGUc8AlQGHLyWv5usy/pAPtmThw+zqRk2rV21X OhclBY+dKjMbCEPl+nnxroUAy813sAdp8xf0SJkWPJ6jHwIJMTtB8TEF6Fanp1FsW5Sf cFQf61nMD3vKJ3Ua+ETqiOOSM+CMzkCUOCLbfMzlLiBEg9kb/URFPNRX3uustrSayT3V BWuGKSUVbfn1PNd4Pexcwk8XpsQ5ym5saoSmL284JKARKq5Ys94zoo3rcSRn8JZTgH46 7o9w== X-Gm-Message-State: ACgBeo0iLbpGOQyUcdnwkx+5XEuMX/WXmoq92X92nTdEjxGO3rXn3z5S vrp0E6YTosNtqNZD5UmSvhhVgw== X-Google-Smtp-Source: AA6agR4IEC6lgocCONOR/A/J5VPjq6hV3cxawX43viUZIazPc0f+DLIAiqlnaC0HGGF0nJY74A1UZg== X-Received: by 2002:a05:6512:3d9f:b0:497:a108:544f with SMTP id k31-20020a0565123d9f00b00497a108544fmr5475867lfv.688.1662814024379; Sat, 10 Sep 2022 05:47:04 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id k14-20020a2e920e000000b002677a3ad1d9sm327463ljg.76.2022.09.10.05.47.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Sep 2022 05:47:03 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC PATCH 02/10] thermal/drivers/tsens: Support using nvmem cells for calibration data Date: Sat, 10 Sep 2022 15:46:53 +0300 Message-Id: <20220910124701.4060321-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> References: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add a unified function using nvmem cells for parsing the calibration data rather than parsing the calibration blob manually. Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v0_1.c | 15 ++++++++ drivers/thermal/qcom/tsens-v1.c | 6 ++- drivers/thermal/qcom/tsens.c | 62 +++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.h | 4 ++ 4 files changed, 86 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v0_1.c b/drivers/thermal/qcom/tsens-v0_1.c index f136cb350238..2974eea578f4 100644 --- a/drivers/thermal/qcom/tsens-v0_1.c +++ b/drivers/thermal/qcom/tsens-v0_1.c @@ -229,6 +229,11 @@ static int calibrate_8916(struct tsens_priv *priv) u32 p1[5], p2[5]; int mode = 0; u32 *qfprom_cdata, *qfprom_csel; + int ret; + + ret = tsens_calibrate_nvmem(priv, 3); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) @@ -286,6 +291,11 @@ static int calibrate_8939(struct tsens_priv *priv) int mode = 0; u32 *qfprom_cdata; u32 cdata[6]; + int ret; + + ret = tsens_calibrate_nvmem(priv, 2); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) @@ -491,6 +501,11 @@ static int calibrate_9607(struct tsens_priv *priv) u32 p1[5], p2[5]; int mode = 0; u32 *qfprom_cdata; + int ret; + + ret = tsens_calibrate_nvmem(priv, 2); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 573e261ccca7..868d7b4c9e36 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -172,7 +172,11 @@ static int calibrate_v1(struct tsens_priv *priv) u32 p1[10], p2[10]; u32 mode = 0, lsb = 0, msb = 0; u32 *qfprom_cdata; - int i; + int i, ret; + + ret = tsens_calibrate_nvmem(priv, 2); + if (!ret) + return 0; qfprom_cdata = (u32 *)qfprom_read(priv->dev, "calib"); if (IS_ERR(qfprom_cdata)) diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index e49f58e83513..8331b924325a 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -70,6 +70,68 @@ char *qfprom_read(struct device *dev, const char *cname) return ret; } +int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift) +{ + u32 mode; + u32 base1, base2; + u32 p1[MAX_SENSORS], p2[MAX_SENSORS]; + char name[] = "sX_pY"; + int i, ret; + + if (priv->num_sensors > MAX_SENSORS) + return -EINVAL; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "mode", &mode); + if (ret == -ENOENT) + dev_warn(priv->dev, "Please migrate to sepate nvmem cells for calibration data\n"); + if (ret < 0) + return ret; + + dev_dbg(priv->dev, "calibration mode is %d\n", mode); + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base1", &base1); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, "base2", &base2); + if (ret < 0) + return ret; + + for (i = 0; i < priv->num_sensors; i++) { + ret = snprintf(name, sizeof(name), "s%d_p1", i); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &p1[i]); + if (ret) + return ret; + + p1[i] = (base1 + p1[i]) << shift; + + ret = snprintf(name, sizeof(name), "s%d_p2", i); + if (ret < 0) + return ret; + + ret = nvmem_cell_read_variable_le_u32(priv->dev, name, &p2[i]); + if (ret) + return ret; + + p2[i] = (base2 + p2[i]) << shift; + } + + if (mode == NO_PT_CALIB) { + dev_dbg(priv->dev, "calibrationless mode\n"); + for (i = 0; i < priv->num_sensors; i++) { + p1[i] = 500; + p2[i] = 780; + } + } + + compute_intercept_slope(priv, p1, p2, mode); + + return 0; +} + /* * Use this function on devices where slope and offset calculations * depend on calibration data read from qfprom. On others the slope diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index ba05c8233356..504ed3394a79 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -6,6 +6,7 @@ #ifndef __QCOM_TSENS_H__ #define __QCOM_TSENS_H__ +#define NO_PT_CALIB 0x0 #define ONE_PT_CALIB 0x1 #define ONE_PT_CALIB2 0x2 #define TWO_PT_CALIB 0x3 @@ -17,6 +18,8 @@ #define THRESHOLD_MAX_ADC_CODE 0x3ff #define THRESHOLD_MIN_ADC_CODE 0x0 +#define MAX_SENSORS 16 + #include #include #include @@ -576,6 +579,7 @@ struct tsens_priv { }; char *qfprom_read(struct device *dev, const char *cname); +int tsens_calibrate_nvmem(struct tsens_priv *priv, int shift); void compute_intercept_slope(struct tsens_priv *priv, u32 *pt1, u32 *pt2, u32 mode); int init_common(struct tsens_priv *priv); int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp); From patchwork Sat Sep 10 12:46:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 604575 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 32379ECAAD3 for ; Sat, 10 Sep 2022 12:47:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229691AbiIJMrN (ORCPT ); Sat, 10 Sep 2022 08:47:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38466 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229661AbiIJMrK (ORCPT ); Sat, 10 Sep 2022 08:47:10 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 468AE578AB for ; Sat, 10 Sep 2022 05:47:08 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id f11so7247792lfa.6 for ; Sat, 10 Sep 2022 05:47:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=E42nL0SnLuu/advWVSA0exITSa9nePRzRLUKZ/sijPQ=; b=SJxt8lNR5AHZZUvEoZhMSYNUIElaFZyRNFubRnBVFbp+C/s57x29zwFeMdkT65bM0O R0gihKvGO1FoKu6u3OqISgtPtJz8LZaQly4mMwmG8Iw1nrRnOFUiKzwezcXyppKaJJUW rempBnSkgEULIXFnC6HXeN5q7k5yElGCZGfwgCWONi+jPLuyvbhdPi5ChFdc+E/Orp8Y rwHQDBr14qQ6eB5IrCWSdMGkiCSvHcc92gHEUx/xc4TTngz0HCHKfpN0WhNx0nfKk+ra f8R6D1uDLc87lelFS+NPJynk2YklUANxpeqHiOmtVeVcYVB2/2+TaV47RlPLP7+nkBUU d9Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=E42nL0SnLuu/advWVSA0exITSa9nePRzRLUKZ/sijPQ=; b=x7hIrb623q6bhnSQ5D2gic8EiuM01P225ZrL8GuGAuFhPlpccIDg5e3hk1Q5shtWs6 EOQCyf8xFQK9cs55umK5sO78VbtYfwiRpOsj6LumPcAQ9LouMOz8Xmz9yNPeXUcthiL7 Zo6oiQjynNK0Olbz1siNOPwDKOQA7zJyK5Xl/38aprjNF11uLc1YDhbYU2luRBt+ZLae 9pCplkcgoR8Sp2cF+LOZrrxyOwo9NHdJwpHxaFrWEAqnkHtjugeEsK6vunyrEPLMs74r hCtWcVEb44uSD+cRJ30EV3ahyLINIcPf9zS37gSWKdF6XxxXZpmjTnMy/9FyCcEA2fZS 3CPQ== X-Gm-Message-State: ACgBeo0qXIuq0h+/y/CQZy/MP8VeqbL3TMllv3hNEsJn4sITDEQs2bR+ pXaeNjUI3/z8GWJqVDGdFkXxQg== X-Google-Smtp-Source: AA6agR5eonv7R5b5BupEFDATrPIP336R2/jmJGZrzWiWVO3yhpxHO/1WNnkHTD3CLeycM+YZkShCtA== X-Received: by 2002:a19:505e:0:b0:497:abf6:1115 with SMTP id z30-20020a19505e000000b00497abf61115mr5632021lfj.36.1662814026639; Sat, 10 Sep 2022 05:47:06 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id k14-20020a2e920e000000b002677a3ad1d9sm327463ljg.76.2022.09.10.05.47.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Sep 2022 05:47:06 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [RFC PATCH 05/10] thermal/drivers/tsens: drop msm8976-specific defines Date: Sat, 10 Sep 2022 15:46:56 +0300 Message-Id: <20220910124701.4060321-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> References: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop msm8976-specific defines, which duplicate generic ones. Cc: Konrad Dybcio Cc: AngeloGioacchino Del Regno Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index 868d7b4c9e36..e6ef3bacfc39 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -78,11 +78,6 @@ #define MSM8976_CAL_SEL_MASK 0x3 -#define MSM8976_CAL_DEGC_PT1 30 -#define MSM8976_CAL_DEGC_PT2 120 -#define MSM8976_SLOPE_FACTOR 1000 -#define MSM8976_SLOPE_DEFAULT 3200 - /* eeprom layout data for qcs404/405 (v1) */ #define BASE0_MASK 0x000007f8 #define BASE1_MASK 0x0007f800 @@ -160,8 +155,8 @@ static void compute_intercept_slope_8976(struct tsens_priv *priv, priv->sensor[10].slope = 3286; for (i = 0; i < priv->num_sensors; i++) { - priv->sensor[i].offset = (p1[i] * MSM8976_SLOPE_FACTOR) - - (MSM8976_CAL_DEGC_PT1 * + priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - + (CAL_DEGC_PT1 * priv->sensor[i].slope); } } From patchwork Sat Sep 10 12:46:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 604576 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9A8B3C6FA96 for ; Sat, 10 Sep 2022 12:47:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229582AbiIJMrL (ORCPT ); Sat, 10 Sep 2022 08:47:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38444 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229635AbiIJMrJ (ORCPT ); Sat, 10 Sep 2022 08:47:09 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4634B57895 for ; Sat, 10 Sep 2022 05:47:08 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id k10so7262852lfm.4 for ; Sat, 10 Sep 2022 05:47:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=iQQMZWiQo60j4E8YQUdNFlg6xHQjLMTSCPZx/5k4hto=; b=MGW6RT+7ZRjAWILA/5uFm4gR97jAJj0QfVSM8Zo/X0c9zGgFZCTx/Zsv19yB8Q8BLz /xNboDe78nfP2PZnKz3o5QBwopctGDbppuXNNK4qXqmPrhYUgMXcgcnMb3CplkpTw5H3 dxgXhw3i82MJOdpsRpoMJQPP9godsawwJUborzILUCsjvjLRYF4K3mSmaJykvSmP1/jx X4W6BLp74fl1Ql1bz4g9T2dmtmuVI8SE5Am9Yz/iKpsNZPL4NYakGoVbdH/ILSuBmYhB U5vAdxI5Eotb3HZb43AUnkXcvFtMEMuoit/viVxgZZFpJCFEt1xrY46dsA/g4V5Hbmn0 C0rA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=iQQMZWiQo60j4E8YQUdNFlg6xHQjLMTSCPZx/5k4hto=; b=nuPfs9dbRmxqE0g/fpysw73AB1LRZxDmrQ8H+D+Kzs3/shaLADk8P7/jBjzbZTYdIl /ynHDnnif3qgSJahiy+PEoVNQx6klgo+gtJ61SSq5p2/AOFWgdn3ou573CngW3qDlQTI 8VwzC/pVK9h1PtebWWiKO6iYYLv8+/jIWTk0cWN6DTW+WrrMd1YMC7vEHQgtNzXpH/OG cYz+XZAuNS1Me0hCLMlQ03DG7oq38Dwoy3qZ5r0wipxs7MDgzAGKz68Sm5SvaITwKrgN ZrcWE9FyTzxvjk7uwWNpFY/eopR77ser1y5jM80782n5yl8wqoVQt8BWSTknZkCQ2+Wf fvfw== X-Gm-Message-State: ACgBeo1PuW9xIkt56qPTKmkl1H5QqmaQPFP6LYPCt1VUkxJtHuDRnIre qYuNQpotFeVhO0cBANvJQKYElg== X-Google-Smtp-Source: AA6agR4BnPZ6R3AXFRgr/POumn5pPb4h25fzYSApp5BkcRMA+nkRVqSRAdRsKR0Ddr5um+h5VLeR4g== X-Received: by 2002:a05:6512:114e:b0:498:76c2:658a with SMTP id m14-20020a056512114e00b0049876c2658amr4424699lfg.672.1662814027719; Sat, 10 Sep 2022 05:47:07 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id k14-20020a2e920e000000b002677a3ad1d9sm327463ljg.76.2022.09.10.05.47.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Sep 2022 05:47:07 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org, AngeloGioacchino Del Regno Subject: [RFC PATCH 06/10] thermal/drivers/tsens: use generic calibration routine for msm8976 Date: Sat, 10 Sep 2022 15:46:57 +0300 Message-Id: <20220910124701.4060321-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> References: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org According to msm-3.10, msm8976 uses the same routine for processing calibration data as other platforms. Drop the msm8976-specific compute_intercept_slope_8976() and use compute_intercept_slope(). Cc: Konrad Dybcio Cc: AngeloGioacchino Del Regno Signed-off-by: Dmitry Baryshkov --- drivers/thermal/qcom/tsens-v1.c | 26 +------------------------- 1 file changed, 1 insertion(+), 25 deletions(-) diff --git a/drivers/thermal/qcom/tsens-v1.c b/drivers/thermal/qcom/tsens-v1.c index e6ef3bacfc39..11363a318ae8 100644 --- a/drivers/thermal/qcom/tsens-v1.c +++ b/drivers/thermal/qcom/tsens-v1.c @@ -137,30 +137,6 @@ #define CAL_SEL_MASK 7 #define CAL_SEL_SHIFT 0 -static void compute_intercept_slope_8976(struct tsens_priv *priv, - u32 *p1, u32 *p2, u32 mode) -{ - int i; - - priv->sensor[0].slope = 3313; - priv->sensor[1].slope = 3275; - priv->sensor[2].slope = 3320; - priv->sensor[3].slope = 3246; - priv->sensor[4].slope = 3279; - priv->sensor[5].slope = 3257; - priv->sensor[6].slope = 3234; - priv->sensor[7].slope = 3269; - priv->sensor[8].slope = 3255; - priv->sensor[9].slope = 3239; - priv->sensor[10].slope = 3286; - - for (i = 0; i < priv->num_sensors; i++) { - priv->sensor[i].offset = (p1[i] * SLOPE_FACTOR) - - (CAL_DEGC_PT1 * - priv->sensor[i].slope); - } -} - static int calibrate_v1(struct tsens_priv *priv) { u32 base0 = 0, base1 = 0; @@ -290,7 +266,7 @@ static int calibrate_8976(struct tsens_priv *priv) break; } - compute_intercept_slope_8976(priv, p1, p2, mode); + compute_intercept_slope(priv, p1, p2, mode); kfree(qfprom_cdata); return 0; From patchwork Sat Sep 10 12:47:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 604574 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB763C6FA92 for ; Sat, 10 Sep 2022 12:47:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229696AbiIJMrP (ORCPT ); Sat, 10 Sep 2022 08:47:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38526 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229655AbiIJMrM (ORCPT ); Sat, 10 Sep 2022 08:47:12 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6F93C57885 for ; Sat, 10 Sep 2022 05:47:10 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id i26so7225913lfp.11 for ; Sat, 10 Sep 2022 05:47:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=Xnrwle//1aq5NGhF/qMEZvbwwoMwpjLog3bunzgx6rM=; b=BVd/bJ7kuaUOUaXMcU3dQZTD6lIj6NGmKFCMIH5ED55WCea78YSjfASq9DfQcf6d1q /6JbDNWgopU84NuCLP0JLoEhzqTc9IMaD6z8XeVB2FxNvh27Djbo3U8/ymNglT8fV+44 OQ+u9ZXS4ojSAuB0FuBdDY3HW6yodwsxcCuA6E2iaIZBgxO9cIuE7urMT8JD5pTB8vsj ZOFJtDQNTfWJBTpdNu9X607Xn8DaNfASia4uRZIz5Tlk8VgN19TWQFL6dgUfVGiNjFhi yUEOmGPLsFNGLPN2m9MPMwLrsMvJcMTKZ4JkxuAxLCwxXiX9myaZf8WozF3qFApWIKY1 iIdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=Xnrwle//1aq5NGhF/qMEZvbwwoMwpjLog3bunzgx6rM=; b=k1RsfhVj9t/IGtSlKeVPz2tn5BZj8QyCklK3ryVd7zb+iHN+ksit/OXZ7I6Sf1QRAI fBQ/6sfQMXEkQX/BnoxydihsfjmDor2gdDCfUfqi9kPoNJ6ALO2ZmHmUmaTy135hKkm7 vyWuNbM9xH5DiG0zLmbMZjn8hky44FEtwtNUwCxAJC3aEqea0XpwAhTmIFvGLqkcZjnC sfNgGLqcrqy5A3KyfpmjFz1HktJYMFEjZYrZIMIBLQoQAs5htwEvqWWnorrRGZyNwZud fBBSt98A8VrauH43xmHL1VrpannQf0YD37VUvukEeQCrpHQw0skZYwUUsSoppxjxRsNP 1X6g== X-Gm-Message-State: ACgBeo22iVgHmcPb15SqslUbUs3yBzos/gq+V/8Lfbp/Ra4E7q8/fTtl GOKPAooYlfF9NFSmdIdCwxXozA== X-Google-Smtp-Source: AA6agR6s148d4YerVeBrqBSEgZ0fxuXqADDlmf/69Y+9zvQwmWUbnDleLVGwNxVrSGTTZpEEJ4sVrw== X-Received: by 2002:a05:6512:31cc:b0:494:6815:a81b with SMTP id j12-20020a05651231cc00b004946815a81bmr6365824lfe.511.1662814029971; Sat, 10 Sep 2022 05:47:09 -0700 (PDT) Received: from eriador.lan ([37.153.55.125]) by smtp.gmail.com with ESMTPSA id k14-20020a2e920e000000b002677a3ad1d9sm327463ljg.76.2022.09.10.05.47.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 10 Sep 2022 05:47:09 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Amit Kucheria , Thara Gopinath , "Rafael J. Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC PATCH 09/10] arm64: dts: qcom: msm8916: specify per-sensor calibration cells Date: Sat, 10 Sep 2022 15:47:00 +0300 Message-Id: <20220910124701.4060321-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> References: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/msm8916.dtsi | 70 ++++++++++++++++++++++++--- 1 file changed, 64 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/msm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8916.dtsi index 48bc2e09128d..d2cce8f75fb6 100644 --- a/arch/arm64/boot/dts/qcom/msm8916.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8916.dtsi @@ -442,11 +442,57 @@ qfprom: qfprom@5c000 { reg = <0x0005c000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { - reg = <0xd0 0x8>; + tsens_base1: base1@d0 { + reg = <0xd0 0x1>; + bits = <0 7>; }; - tsens_calsel: calsel@ec { - reg = <0xec 0x4>; + tsens_s0_p1: s0_p1@d0 { + reg = <0xd0 0x2>; + bits = <7 5>; + }; + tsens_s0_p2: s0_p2@d1 { + reg = <0xd1 0x2>; + bits = <4 5>; + }; + tsens_s1_p1: s1_p1@d2 { + reg = <0xd2 0x1>; + bits = <1 5>; + }; + tsens_s1_p2: s1_p2@d2 { + reg = <0xd2 0x2>; + bits = <6 5>; + }; + tsens_s2_p1: s2_p1@d3 { + reg = <0xd3 0x1>; + bits = <3 5>; + }; + tsens_s2_p2: s2_p2@d4 { + reg = <0xd4 0x1>; + bits = <0 5>; + }; + tsens_s3_p1: s3_p1@d4 { + reg = <0xd4 0x2>; + bits = <5 5>; + }; + tsens_s3_p2: s3_p2@d5 { + reg = <0xd5 0x1>; + bits = <2 5>; + }; + tsens_s4_p1: s4_p1@d5 { + reg = <0xd5 0x2>; + bits = <7 5>; + }; + tsens_s4_p2: s4_p2@d6 { + reg = <0xd6 0x2>; + bits = <4 5>; + }; + tsens_base2: base2@d7 { + reg = <0xd7 0x1>; + bits = <1 7>; + }; + tsens_mode: mode@ec { + reg = <0xef 0x1>; + bits = <5 3>; }; }; @@ -473,8 +519,20 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,msm8916-tsens", "qcom,tsens-v0_1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>, <&tsens_calsel>; - nvmem-cell-names = "calib", "calib_sel"; + nvmem-cells = <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>; + nvmem-cell-names = "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2"; 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Wysocki" , Daniel Lezcano , Zhang Rui Cc: linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, devicetree@vger.kernel.org Subject: [RFC PATCH 10/10] arm64: dts: qcom: qcs404: specify per-sensor calibration cells Date: Sat, 10 Sep 2022 15:47:01 +0300 Message-Id: <20220910124701.4060321-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> References: <20220910124701.4060321-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Specify pre-parsed per-sensor calibration nvmem cells in the tsens device node rather than parsing the whole data blob in the driver. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/qcs404.dtsi | 120 ++++++++++++++++++++++++++- 1 file changed, 117 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/qcs404.dtsi b/arch/arm64/boot/dts/qcom/qcs404.dtsi index 9ab990061522..bcbbd5ede2a1 100644 --- a/arch/arm64/boot/dts/qcom/qcs404.dtsi +++ b/arch/arm64/boot/dts/qcom/qcs404.dtsi @@ -370,13 +370,105 @@ qfprom: qfprom@a4000 { reg = <0x000a4000 0x1000>; #address-cells = <1>; #size-cells = <1>; - tsens_caldata: caldata@d0 { + tsens_caldata: caldata@1f8 { reg = <0x1f8 0x14>; }; cpr_efuse_speedbin: speedbin@13c { reg = <0x13c 0x4>; bits = <2 3>; }; + tsens_s0_p1: s0_p1@1f8 { + reg = <0x1f8 0x1>; + bits = <0 6>; + }; + tsens_s0_p2: s0_p2@1f8 { + reg = <0x1f8 0x2>; + bits = <6 6>; + }; + tsens_s1_p1: s1_p1@1f9 { + reg = <0x1f9 0x2>; + bits = <4 6>; + }; + tsens_s1_p2: s1_p2@1fa { + reg = <0x1fa 0x1>; + bits = <2 6>; + }; + tsens_s2_p1: s2_p1@1fb { + reg = <0x1fb 0x1>; + bits = <0 6>; + }; + tsens_s2_p2: s2_p2@1fb { + reg = <0x1fb 0x2>; + bits = <6 6>; + }; + tsens_s3_p1: s3_p1@1fc { + reg = <0x1fc 0x2>; + bits = <4 6>; + }; + tsens_s3_p2: s3_p2@1fd { + reg = <0x1fd 0x1>; + bits = <2 6>; + }; + tsens_s4_p1: s4_p1@1fe { + reg = <0x1fe 0x1>; + bits = <0 6>; + }; + tsens_s4_p2: s4_p2@1fe { + reg = <0x1fe 0x2>; + bits = <6 6>; + }; + tsens_s5_p1: s5_p1@200 { + reg = <0x200 0x1>; + bits = <0 6>; + }; + tsens_s5_p2: s5_p2@200 { + reg = <0x200 0x2>; + bits = <6 6>; + }; + tsens_s6_p1: s6_p1@201 { + reg = <0x201 0x2>; + bits = <4 6>; + }; + tsens_s6_p2: s6_p2@202 { + reg = <0x202 0x1>; + bits = <2 6>; + }; + tsens_s7_p1: s7_p1@203 { + reg = <0x203 0x1>; + bits = <0 6>; + }; + tsens_s7_p2: s7_p2@203 { + reg = <0x203 0x2>; + bits = <6 6>; + }; + tsens_s8_p1: s8_p1@204 { + reg = <0x204 0x2>; + bits = <4 6>; + }; + tsens_s8_p2: s8_p2@205 { + reg = <0x205 0x1>; + bits = <2 6>; + }; + tsens_s9_p1: s9_p1@206 { + reg = <0x206 0x1>; + bits = <0 6>; + }; + tsens_s9_p2: s9_p2@206 { + reg = <0x206 0x2>; + bits = <6 6>; + }; + tsens_mode: mode@208 { + reg = <0x208 1>; + bits = <0 3>; + }; + tsens_base1: base1@208 { + reg = <0x208 2>; + bits = <3 8>; + }; + tsens_base2: base2@208 { + reg = <0x209 2>; + bits = <3 8>; + }; cpr_efuse_quot_offset1: qoffset1@231 { reg = <0x231 0x4>; bits = <4 7>; @@ -451,8 +543,30 @@ tsens: thermal-sensor@4a9000 { compatible = "qcom,qcs404-tsens", "qcom,tsens-v1"; reg = <0x004a9000 0x1000>, /* TM */ <0x004a8000 0x1000>; /* SROT */ - nvmem-cells = <&tsens_caldata>; - nvmem-cell-names = "calib"; + nvmem-cells = <&tsens_caldata>, <&tsens_mode>, + <&tsens_base1>, <&tsens_base2>, + <&tsens_s0_p1>, <&tsens_s0_p2>, + <&tsens_s1_p1>, <&tsens_s1_p2>, + <&tsens_s2_p1>, <&tsens_s2_p2>, + <&tsens_s3_p1>, <&tsens_s3_p2>, + <&tsens_s4_p1>, <&tsens_s4_p2>, + <&tsens_s5_p1>, <&tsens_s5_p2>, + <&tsens_s6_p1>, <&tsens_s6_p2>, + <&tsens_s7_p1>, <&tsens_s7_p2>, + <&tsens_s8_p1>, <&tsens_s8_p2>, + <&tsens_s9_p1>, <&tsens_s9_p2>; + nvmem-cell-names = "calib", "mode", + "base1", "base2", + "s0_p1", "s0_p2", + "s1_p1", "s1_p2", + "s2_p1", "s2_p2", + "s3_p1", "s3_p2", + "s4_p1", "s4_p2", + "s5_p1", "s5_p2", + "s6_p1", "s6_p2", + "s7_p1", "s7_p2", + "s8_p1", "s8_p2", + "s9_p1", "s9_p2"; #qcom,sensors = <10>; interrupts = ; interrupt-names = "uplow";