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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id b25sm1119581pfi.72.2019.02.13.20.06.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Feb 2019 20:06:54 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 13 Feb 2019 20:06:49 -0800 Message-Id: <20190214040652.4811-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214040652.4811-1-richard.henderson@linaro.org> References: <20190214040652.4811-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62f Subject: [Qemu-devel] [PATCH 1/4] target/arm: Split out recompute_hflags et al X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We will use these to minimize the computation for every call to cpu_get_tb_cpu_state. For now, the env->hflags variable is not used. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 22 +++- target/arm/helper.h | 3 + target/arm/internals.h | 3 + target/arm/helper.c | 268 ++++++++++++++++++++++++----------------- 4 files changed, 180 insertions(+), 116 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47238e4245..8b0dea947b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -240,6 +240,9 @@ typedef struct CPUARMState { uint32_t pstate; uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.nRW */ + /* Cached TBFLAGS state. See below for which bits are included. */ + uint32_t hflags; + /* Frequently accessed CPSR bits are stored separately for efficiency. This contains all the other bits. Use cpsr_{read,write} to access the whole CPSR. */ @@ -3019,25 +3022,28 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env) #include "exec/cpu-all.h" -/* Bit usage in the TB flags field: bit 31 indicates whether we are +/* + * Bit usage in the TB flags field: bit 31 indicates whether we are * in 32 or 64 bit mode. The meaning of the other bits depends on that. * We put flags which are shared between 32 and 64 bit mode at the top * of the word, and flags which apply to only one mode at the bottom. + * + * Unless otherwise noted, these bits are cached in env->hflags. */ FIELD(TBFLAG_ANY, AARCH64_STATE, 31, 1) FIELD(TBFLAG_ANY, MMUIDX, 28, 3) FIELD(TBFLAG_ANY, SS_ACTIVE, 27, 1) -FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) +FIELD(TBFLAG_ANY, PSTATE_SS, 26, 1) /* Not cached. */ /* Target EL if we take a floating-point-disabled exception */ FIELD(TBFLAG_ANY, FPEXC_EL, 24, 2) FIELD(TBFLAG_ANY, BE_DATA, 23, 1) /* Bit usage when in AArch32 state: */ -FIELD(TBFLAG_A32, THUMB, 0, 1) +FIELD(TBFLAG_A32, THUMB, 0, 1) /* Not cached. */ FIELD(TBFLAG_A32, VECLEN, 1, 3) FIELD(TBFLAG_A32, VECSTRIDE, 4, 2) FIELD(TBFLAG_A32, VFPEN, 7, 1) -FIELD(TBFLAG_A32, CONDEXEC, 8, 8) +FIELD(TBFLAG_A32, CONDEXEC, 8, 8) /* Not cached. */ FIELD(TBFLAG_A32, SCTLR_B, 16, 1) /* We store the bottom two bits of the CPAR as TB flags and handle * checks on the other bits at runtime @@ -3059,7 +3065,7 @@ FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2) FIELD(TBFLAG_A64, ZCR_LEN, 4, 4) FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1) FIELD(TBFLAG_A64, BT, 9, 1) -FIELD(TBFLAG_A64, BTYPE, 10, 2) +FIELD(TBFLAG_A64, BTYPE, 10, 2) /* Not cached. */ FIELD(TBFLAG_A64, TBID, 12, 2) static inline bool bswap_code(bool sctlr_b) @@ -3144,6 +3150,12 @@ void arm_register_pre_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void arm_register_el_change_hook(ARMCPU *cpu, ARMELChangeHookFn *hook, void *opaque); +/** + * arm_rebuild_hflags: + * Rebuild the cached TBFLAGS for arbitrary changed processor state. + */ +void arm_rebuild_hflags(CPUARMState *env); + /** * aa32_vfp_dreg: * Return a pointer to the Dn register within env in 32-bit mode. diff --git a/target/arm/helper.h b/target/arm/helper.h index 53a38188c6..e3c98913e6 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -653,6 +653,9 @@ DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_2(rebuild_hflags_a32, TCG_CALL_NO_RWG, void, env, i32) +DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/internals.h b/target/arm/internals.h index a4bd1becb7..8c1b813364 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -968,4 +968,7 @@ ARMVAParameters aa64_va_parameters_both(CPUARMState *env, uint64_t va, ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, ARMMMUIdx mmu_idx, bool data); +uint32_t rebuild_hflags_a32(CPUARMState *env, int el); +uint32_t rebuild_hflags_a64(CPUARMState *env, int el); + #endif diff --git a/target/arm/helper.c b/target/arm/helper.c index 520ceea7a4..7a77f53ba8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13745,122 +13745,15 @@ ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env) } #endif -void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *pflags) +static uint32_t common_hflags(CPUARMState *env, int el, ARMMMUIdx mmu_idx, + int fp_el, uint32_t flags) { - ARMMMUIdx mmu_idx = arm_mmu_idx(env); - int current_el = arm_current_el(env); - int fp_el = fp_exception_el(env, current_el); - uint32_t flags = 0; - - if (is_a64(env)) { - ARMCPU *cpu = arm_env_get_cpu(env); - uint64_t sctlr; - - *pc = env->pc; - flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); - - /* Get control bits for tagged addresses. */ - { - ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); - ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); - int tbii, tbid; - - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - if (regime_el(env, stage1) < 2) { - ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); - tbid = (p1.tbi << 1) | p0.tbi; - tbii = tbid & ~((p1.tbid << 1) | p0.tbid); - } else { - tbid = p0.tbi; - tbii = tbid & !p0.tbid; - } - - flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); - flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); - } - - if (cpu_isar_feature(aa64_sve, cpu)) { - int sve_el = sve_exception_el(env, current_el); - uint32_t zcr_len; - - /* If SVE is disabled, but FP is enabled, - * then the effective len is 0. - */ - if (sve_el != 0 && fp_el == 0) { - zcr_len = 0; - } else { - zcr_len = sve_zcr_len_for_el(env, current_el); - } - flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); - flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); - } - - if (current_el == 0) { - /* FIXME: ARMv8.1-VHE S2 translation regime. */ - sctlr = env->cp15.sctlr_el[1]; - } else { - sctlr = env->cp15.sctlr_el[current_el]; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - /* - * In order to save space in flags, we record only whether - * pauth is "inactive", meaning all insns are implemented as - * a nop, or "active" when some action must be performed. - * The decision of which action to take is left to a helper. - */ - if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { - flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); - } - } - - if (cpu_isar_feature(aa64_bti, cpu)) { - /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ - if (sctlr & (current_el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { - flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); - } - flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); - } - } else { - *pc = env->regs[15]; - flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); - flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); - flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); - flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); - flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); - flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1)) { - flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); - } - flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); - } - flags = FIELD_DP32(flags, TBFLAG_ANY, MMUIDX, arm_to_core_mmu_idx(mmu_idx)); + flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine - * states defined in the ARM ARM for software singlestep: - * SS_ACTIVE PSTATE.SS State - * 0 x Inactive (the TB flag for SS is always 0) - * 1 0 Active-pending - * 1 1 Active-not-pending - */ - if (arm_singlestep_active(env)) { - flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } else { - if (env->uncached_cpsr & PSTATE_SS) { - flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); - } - } - } if (arm_cpu_data_is_big_endian(env)) { flags = FIELD_DP32(flags, TBFLAG_ANY, BE_DATA, 1); } - flags = FIELD_DP32(flags, TBFLAG_ANY, FPEXC_EL, fp_el); if (arm_v7m_is_handler_mode(env)) { flags = FIELD_DP32(flags, TBFLAG_A32, HANDLER, 1); @@ -13876,8 +13769,161 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, flags = FIELD_DP32(flags, TBFLAG_A32, STACKCHECK, 1); } - *pflags = flags; + if (arm_singlestep_active(env)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, SS_ACTIVE, 1); + } + + return flags; +} + +uint32_t rebuild_hflags_a32(CPUARMState *env, int el) +{ + uint32_t flags = 0; + ARMMMUIdx mmu_idx; + int fp_el; + + flags = FIELD_DP32(flags, TBFLAG_A32, VECLEN, env->vfp.vec_len); + flags = FIELD_DP32(flags, TBFLAG_A32, VECSTRIDE, env->vfp.vec_stride); + flags = FIELD_DP32(flags, TBFLAG_A32, SCTLR_B, arm_sctlr_b(env)); + flags = FIELD_DP32(flags, TBFLAG_A32, NS, !access_secure_reg(env)); + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) + || arm_el_is_aa64(env, 1)) { + flags = FIELD_DP32(flags, TBFLAG_A32, VFPEN, 1); + } + flags = FIELD_DP32(flags, TBFLAG_A32, XSCALE_CPAR, env->cp15.c15_cpar); + + mmu_idx = arm_mmu_idx(env); + fp_el = fp_exception_el(env, el); + return common_hflags(env, el, mmu_idx, fp_el, flags); +} + +uint32_t rebuild_hflags_a64(CPUARMState *env, int el) +{ + ARMCPU *cpu = arm_env_get_cpu(env); + ARMMMUIdx mmu_idx = arm_mmu_idx(env); + ARMMMUIdx stage1 = stage_1_mmu_idx(mmu_idx); + ARMVAParameters p0 = aa64_va_parameters_both(env, 0, stage1); + int fp_el = fp_exception_el(env, el); + uint32_t flags = 0; + uint64_t sctlr; + int tbii, tbid; + + flags = FIELD_DP32(flags, TBFLAG_ANY, AARCH64_STATE, 1); + + /* Get control bits for tagged addresses. */ + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + if (regime_el(env, stage1) < 2) { + ARMVAParameters p1 = aa64_va_parameters_both(env, -1, stage1); + tbid = (p1.tbi << 1) | p0.tbi; + tbii = tbid & ~((p1.tbid << 1) | p0.tbid); + } else { + tbid = p0.tbi; + tbii = tbid & !p0.tbid; + } + + flags = FIELD_DP32(flags, TBFLAG_A64, TBII, tbii); + flags = FIELD_DP32(flags, TBFLAG_A64, TBID, tbid); + + if (cpu_isar_feature(aa64_sve, cpu)) { + int sve_el = sve_exception_el(env, el); + uint32_t zcr_len; + + /* If SVE is disabled, but FP is enabled, + * then the effective len is 0. + */ + if (sve_el != 0 && fp_el == 0) { + zcr_len = 0; + } else { + zcr_len = sve_zcr_len_for_el(env, el); + } + flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); + flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); + } + + if (el == 0) { + /* FIXME: ARMv8.1-VHE S2 translation regime. */ + sctlr = env->cp15.sctlr_el[1]; + } else { + sctlr = env->cp15.sctlr_el[el]; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + /* + * In order to save space in flags, we record only whether + * pauth is "inactive", meaning all insns are implemented as + * a nop, or "active" when some action must be performed. + * The decision of which action to take is left to a helper. + */ + if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) { + flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1); + } + } + + if (cpu_isar_feature(aa64_bti, cpu)) { + /* Note that SCTLR_EL[23].BT == SCTLR_BT1. */ + if (sctlr & (el == 0 ? SCTLR_BT0 : SCTLR_BT1)) { + flags = FIELD_DP32(flags, TBFLAG_A64, BT, 1); + } + flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + } + + return common_hflags(env, el, mmu_idx, fp_el, flags); +} + +void arm_rebuild_hflags(CPUARMState *env) +{ + int el = arm_current_el(env); + env->hflags = (is_a64(env) + ? rebuild_hflags_a64(env, el) + : rebuild_hflags_a32(env, el)); +} + +void HELPER(rebuild_hflags_a32)(CPUARMState *env, uint32_t el) +{ + tcg_debug_assert(!is_a64(env)); + env->hflags = rebuild_hflags_a32(env, el); +} + +void HELPER(rebuild_hflags_a64)(CPUARMState *env, uint32_t el) +{ + tcg_debug_assert(is_a64(env)); + env->hflags = rebuild_hflags_a64(env, el); +} + +void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + int current_el = arm_current_el(env); + uint32_t flags; + uint32_t pstate_for_ss; + *cs_base = 0; + if (is_a64(env)) { + *pc = env->pc; + flags = rebuild_hflags_a64(env, current_el); + flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); + pstate_for_ss = env->pstate; + } else { + *pc = env->regs[15]; + flags = rebuild_hflags_a32(env, current_el); + flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); + flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); + pstate_for_ss = env->uncached_cpsr; + } + + /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + * states defined in the ARM ARM for software singlestep: + * SS_ACTIVE PSTATE.SS State + * 0 x Inactive (the TB flag for SS is always 0) + * 1 0 Active-pending + * 1 1 Active-not-pending + * SS_ACTIVE is set in hflags; PSTATE_SS is computed every TB. + */ + if (FIELD_EX32(flags, TBFLAG_ANY, SS_ACTIVE) + && (pstate_for_ss & PSTATE_SS)) { + flags = FIELD_DP32(flags, TBFLAG_ANY, PSTATE_SS, 1); + } + + *pflags = flags; } #ifdef TARGET_AARCH64 From patchwork Thu Feb 14 04:06:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158312 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp879540jaa; Wed, 13 Feb 2019 20:07:25 -0800 (PST) X-Google-Smtp-Source: AHgI3IZwa/n9i8M3FbcYX/1U1Ew4D0wWYa38DLfsQN76F/7FsYe2VWfgo5e+Qu8joBP8LP/Mu4Wc X-Received: by 2002:a5b:88b:: with SMTP id e11mr1357566ybq.270.1550117245372; Wed, 13 Feb 2019 20:07:25 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550117245; cv=none; d=google.com; s=arc-20160816; b=mJcHVBDETSt+f1Nayw7e7CwRlTTKW67TnLm1ayGeiEmW4wKXryVDNM4G958UltJ7cG rArZr5Z2LbY6FTs3zOjAstHbXHFhyf8UVKDH+ugrg3yTMUX0T4Jo3KdVSLwSNRQUEKpf /XpQ6YxaDv9zvj8dZWFYyMwrCxpIxDXA6k/92pVnafnS+LgYnJRy0chy5zVcqjvGhHym 8bHlTjrWndE37gN0Lps7fkMjHGBBntX5GOcYBxgC0wylZl7AEAy/8/lS8D+b8MpR6qAg et8WRcmenAkJ9MVDxPcPGoHpYqD8QvsiP3tFWS0yCTrRPL+R+NqPbfDOUO7TDfYyEGQ9 c8dA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=N9GNITbyk8UnqG/xwPtE4ILmUjJYlPYwEitGU97FK/8=; b=R0VpVpUfd0S9nBAc4Z8uV8Y+ix7omM/XFLL9G6iWWebOeeoay254hS3UfC+Uq0JqGa E50d6NYvCM6AUYJ0E9m2ozzPYRPAQExPh6aqLbuN7QV4a//o4qvQKjDW3FIzz8CO9cpX iBabZzesDo9hqirFb5IUweIwI0PJ4Ggs1+gurLiANv/qDUnnbQOVOwuBvrQSP/0cFNww Kb6AspD6kYgzG20oMvKbobY50aWSLuys3cVG9GX3e6fweOnADKB8umWJT8w15hGbVBAw MBC76ZbiibfYI8ybO29ElD2UsYD+b/PGPASt3S9XbrRRcCtxwTWmB5LokrUJ9HHTqw8k U3Bw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BL2jZugy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id b25sm1119581pfi.72.2019.02.13.20.06.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Feb 2019 20:06:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 13 Feb 2019 20:06:50 -0800 Message-Id: <20190214040652.4811-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214040652.4811-1-richard.henderson@linaro.org> References: <20190214040652.4811-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 Subject: [Qemu-devel] [PATCH 2/4] target/arm: Rebuild hflags at el changes and MSR writes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Now setting, but not relying upon, env->hflags. Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + linux-user/syscall.c | 1 + target/arm/cpu.c | 1 + target/arm/helper-a64.c | 3 +++ target/arm/helper.c | 2 ++ target/arm/machine.c | 1 + target/arm/op_helper.c | 1 + target/arm/translate-a64.c | 6 +++++- target/arm/translate.c | 14 ++++++++++++-- 9 files changed, 27 insertions(+), 3 deletions(-) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/internals.h b/target/arm/internals.h index 8c1b813364..235f4fafec 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -970,5 +970,6 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, uint64_t va, uint32_t rebuild_hflags_a32(CPUARMState *env, int el); uint32_t rebuild_hflags_a64(CPUARMState *env, int el); +void rebuild_hflags_any(CPUARMState *env); #endif diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 5bbb72f3d5..123f342bdc 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9691,6 +9691,7 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, aarch64_sve_narrow_vq(env, vq); } env->vfp.zcr_el[1] = vq - 1; + arm_rebuild_hflags(env); ret = vq * 16; } return ret; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1..e4da513eb3 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -390,6 +390,7 @@ static void arm_cpu_reset(CPUState *s) hw_breakpoint_update_all(cpu); hw_watchpoint_update_all(cpu); + arm_rebuild_hflags(env); } bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 101fa6d3ea..f51cb75444 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -995,6 +995,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } else { env->regs[15] = new_pc & ~0x3; } + rebuild_hflags_a32(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch32 EL%d PC 0x%" PRIx32 "\n", cur_el, new_el, env->regs[15]); @@ -1006,10 +1007,12 @@ void HELPER(exception_return)(CPUARMState *env, uint64_t new_pc) } aarch64_restore_sp(env, new_el); env->pc = new_pc; + rebuild_hflags_a64(env, new_el); qemu_log_mask(CPU_LOG_INT, "Exception return from AArch64 EL%d to " "AArch64 EL%d PC 0x%" PRIx64 "\n", cur_el, new_el, env->pc); } + /* * Note that cur_el can never be 0. If new_el is 0, then * el0_a64 is return_to_aa64, else el0_a64 is ignored. diff --git a/target/arm/helper.c b/target/arm/helper.c index 7a77f53ba8..d8249f0eae 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9081,6 +9081,7 @@ static void take_aarch32_exception(CPUARMState *env, int new_mode, env->regs[14] = env->regs[15] + offset; } env->regs[15] = newpc; + env->hflags = rebuild_hflags_a32(env, arm_current_el(env)); } static void arm_cpu_do_interrupt_aarch32_hyp(CPUState *cs) @@ -9426,6 +9427,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) pstate_write(env, PSTATE_DAIF | new_mode); env->aarch64 = 1; + env->hflags = rebuild_hflags_a64(env, new_el); aarch64_restore_sp(env, new_el); env->pc = addr; diff --git a/target/arm/machine.c b/target/arm/machine.c index b292549614..61889801dd 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -743,6 +743,7 @@ static int cpu_post_load(void *opaque, int version_id) if (!kvm_enabled()) { pmu_op_finish(&cpu->env); } + arm_rebuild_hflags(&cpu->env); return 0; } diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index c998eadfaa..8d459d9a84 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -571,6 +571,7 @@ void HELPER(cpsr_write_eret)(CPUARMState *env, uint32_t val) */ env->regs[15] &= (env->thumb ? ~1 : ~3); + rebuild_hflags_a32(env, arm_current_el(env)); qemu_mutex_lock_iothread(); arm_call_el_change_hook(arm_env_get_cpu(env)); qemu_mutex_unlock_iothread(); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e002251ac6..ad665c1609 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1841,11 +1841,15 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); s->base.is_jmp = DISAS_UPDATE; - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); s->base.is_jmp = DISAS_UPDATE; } } diff --git a/target/arm/translate.c b/target/arm/translate.c index 66cf28c8cb..36842a27b3 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8432,6 +8432,8 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) ri = get_arm_cp_reginfo(s->cp_regs, ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2)); if (ri) { + bool need_exit_tb; + /* Check access permissions */ if (!cp_access_ok(s->current_el, ri, isread)) { return 1; @@ -8604,15 +8606,23 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) } } + need_exit_tb = false; if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { /* I/O operations must end the TB here (whether read or write) */ gen_io_end(); - gen_lookup_tb(s); - } else if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { + need_exit_tb = true; + } + if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + TCGv_i32 tcg_el = tcg_const_i32(s->current_el); + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + tcg_temp_free_i32(tcg_el); + need_exit_tb = true; + } + if (need_exit_tb) { gen_lookup_tb(s); } From patchwork Thu Feb 14 04:06:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158311 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp879503jaa; Wed, 13 Feb 2019 20:07:23 -0800 (PST) X-Google-Smtp-Source: AHgI3IaC/u5KZn3qwlyCU+Sctk2Qs32/DW5GlLhh2Tpi8MUE70nvexLAp8mzkgznSUem9Qi5NYox X-Received: by 2002:a25:774d:: with SMTP id s74mr1365588ybc.204.1550117243770; Wed, 13 Feb 2019 20:07:23 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550117243; cv=none; d=google.com; s=arc-20160816; b=QNf/GDKVPc1+8tzhjl9MMUKYwcLNwXa86hDCCCzjBFfDWyHkzQ/Tz5F4BovYGft2Px 5r6R4K1W7akrmz1n3eF59xv/aLk8rnCBW9q7T58AAMxjyNUtf8teYuRZ9EfFzcGE3u2Y 44AmxWTCuylqfDCPS/CUcLTz2tRyU2uFkTv6UPTHAn8V5+4iZngIm3z9dVmyRNLe3mdD HZQu2OU8IoClSwiGGXdeEnI8eGTiEXpjFUL3vlf1NUe3mkq5OhTW7KzxLMZAO83o1tGR NltJ7nhJ+ynQGu+ih718UV3+izAMmTIFyL6AdoTR8zc7xbCoqxdP5G0O8I0BJWwnE0c8 xpQw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=nodb+pXuGEzhw6weVrwdkSF8Vf1+sp5VvNRk+R4jG1I=; b=aCaXcqiGE24WqTUV84iq0Lt4CUlbSjnMZYqfaBP9NIIZx8TQKtXQeALvmgbROcxAwZ 2LoXZPaot3fu0xlMeILII+EHJc7nIJOjjojpQzev0UsG0qhGiIPBKKn064nDhj3E6U2C C+imhxQATAq0PEl6KIFUjh/lLsLyEVkTSbiLQCsYgviJMOxLuhq1dmig2Infki8OWAAn DwAErVpxKwZcJauGagkW2SrBtX3zNuW3COhIA+OCsHUopZSNr9oUmHiVFm5vY+kLAxpx /MDqZWbMyJ8CWJkAhd5px2vSiDAgQTGgeg6vqS8deAdiKPcwy6mRwHRaI40wOHiZM/EU W9+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BatPyJqj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::442 Subject: [Qemu-devel] [PATCH 3/4] target/arm: Assert hflags is correct in cpu_get_tb_cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Make sure that we are updating env->hflags everywhere required. Signed-off-by: Richard Henderson --- target/arm/helper.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 Reviewed-by: Alex Bennée diff --git a/target/arm/helper.c b/target/arm/helper.c index d8249f0eae..3c8724883d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13902,11 +13902,13 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, if (is_a64(env)) { *pc = env->pc; flags = rebuild_hflags_a64(env, current_el); + assert(flags == env->hflags); flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); pstate_for_ss = env->pstate; } else { *pc = env->regs[15]; flags = rebuild_hflags_a32(env, current_el); + assert(flags == env->hflags); flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); pstate_for_ss = env->uncached_cpsr; From patchwork Thu Feb 14 04:06:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158313 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp881259jaa; Wed, 13 Feb 2019 20:09:42 -0800 (PST) X-Google-Smtp-Source: AHgI3IZIa4m/eVrPEVE0GHUPNzmVvgP8apcR3p+UHkijyKGmzFuPIBpa9FYWKcqNOx3KJZula2eO X-Received: by 2002:a81:7084:: with SMTP id l126mr1235753ywc.203.1550117382672; Wed, 13 Feb 2019 20:09:42 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550117382; cv=none; d=google.com; s=arc-20160816; b=nuZjz8CwW2tzUhm11t5zNQogACbb/m0pTPOnaZ8Ub+6JbWBs9a2lDtc1TbmgIzL+GY EUY+PbK4uSqrjXkqQRMWEhksiqQWLKFocQJwXkos522E1BSvEEznskpiop5dNaFFdq42 HVjmmSA2vLmUBeOf/X1ZggbMalAcMrvbp79E2MuCML+asxyQqqFzjvWjbGIQ/b+2iTPL je0LjEwjbaFVJgB6LoMJdgcKPTj1n4faJbRrUUgnfkBlzOQPjg/+BW/U51kON95FzclE kicIIKz6zzdUacMEUV/TJErWDFifdWAXgtQScO2GotdgvNQVFQI4CAUOksrsGv/JcJST yKCA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=qiwGK9NKR9zng2waAo5zTZuYYKgXgK/hMyrBttacMdQ=; b=S44qvsl/Y2t4fNA1p6MhF2yHZ1Yh0PK9WCQB88+xSxVboLHHNa3f22SoRLYSE8lyK5 h7/Uwf+aTDDBxWKEED6NibHogISr77M+94gosm1i7urh8UT9BU9uOGWMU8+hd2kQ68RZ 3eW9oxgth5cO+LeZkLJ4JGMWIGlxzUbvhvRg5Gwz1smOeUMyFutSGZjN5LMqEhDvsb0w 8o0DdWx1EUYO4Cx9ppGW+ndU3hV9YwKiUQ9pKDPzlxBEedpiy3NqflN1Jc1I3n+zA8of rEoXVPGTOuxjhtAGjS9UL8bTWVlq2BkULJN2MODovzcPymi71A7Q/n7jUp5JXm2j5r9F TB/g== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=fkopXoAT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id b25sm1119581pfi.72.2019.02.13.20.06.58 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 13 Feb 2019 20:06:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 13 Feb 2019 20:06:52 -0800 Message-Id: <20190214040652.4811-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190214040652.4811-1-richard.henderson@linaro.org> References: <20190214040652.4811-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 4/4] target/arm: Rely on hflags correct in cpu_get_tb_cpu_state X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, cota@braap.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is the payoff. >From perf record -g data of ubuntu 18 boot and shutdown: BEFORE: - 23.02% 2.82% qemu-system-aar [.] helper_lookup_tb_ptr - 20.22% helper_lookup_tb_ptr + 10.05% tb_htable_lookup - 9.13% cpu_get_tb_cpu_state 3.20% aa64_va_parameters_both 0.55% fp_exception_el - 11.66% 4.74% qemu-system-aar [.] cpu_get_tb_cpu_state - 6.96% cpu_get_tb_cpu_state 3.63% aa64_va_parameters_both 0.60% fp_exception_el 0.53% sve_exception_el AFTER: - 16.40% 3.40% qemu-system-aar [.] helper_lookup_tb_ptr - 13.03% helper_lookup_tb_ptr + 11.19% tb_htable_lookup 0.55% cpu_get_tb_cpu_state 0.98% 0.71% qemu-system-aar [.] cpu_get_tb_cpu_state 0.87% 0.24% qemu-system-aar [.] rebuild_hflags_a64 Before, helper_lookup_tb_ptr is the second hottest function in the application, consuming almost a quarter of the runtime. Within the entire execution, cpu_get_tb_cpu_state consumes about 12%. After, helper_lookup_tb_ptr has dropped to the fourth hottest function, with consumption dropping to a sixth of the runtime. Within the entire execution, cpu_get_tb_cpu_state has dropped below 1%, and the supporting function to rebuild hflags also consumes about 1%. Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) -- 2.17.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index 3c8724883d..1bdb87267e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -13894,21 +13894,16 @@ void HELPER(rebuild_hflags_a64)(CPUARMState *env, uint32_t el) void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *pflags) { - int current_el = arm_current_el(env); - uint32_t flags; + uint32_t flags = env->hflags; uint32_t pstate_for_ss; *cs_base = 0; - if (is_a64(env)) { + if (FIELD_EX32(flags, TBFLAG_ANY, AARCH64_STATE)) { *pc = env->pc; - flags = rebuild_hflags_a64(env, current_el); - assert(flags == env->hflags); flags = FIELD_DP32(flags, TBFLAG_A64, BTYPE, env->btype); pstate_for_ss = env->pstate; } else { *pc = env->regs[15]; - flags = rebuild_hflags_a32(env, current_el); - assert(flags == env->hflags); flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb); flags = FIELD_DP32(flags, TBFLAG_A32, CONDEXEC, env->condexec_bits); pstate_for_ss = env->uncached_cpsr;