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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id o2sm972713pgq.90.2019.02.13.19.43.48 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Feb 2019 19:43:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 13 Feb 2019 19:43:42 -0800 Message-Id: <20190214034345.24722-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190214034345.24722-1-richard.henderson@linaro.org> References: <20190214034345.24722-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH 1/4] target/arm: Add helpers for FMLAL and FMLSL X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Note that float16_to_float32 rightly squashes SNaN to QNaN. But of course pickNaNMulAdd, for ARM, selects SNaNs first. So we have to preserve SNaN long enough for the correct NaN to be selected. Thus float16_to_float32_by_bits. Signed-off-by: Richard Henderson --- target/arm/helper.h | 9 +++ target/arm/vec_helper.c | 154 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 163 insertions(+) -- 2.17.2 diff --git a/target/arm/helper.h b/target/arm/helper.h index 53a38188c6..0302e13604 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -653,6 +653,15 @@ DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmlsl_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmlal_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_fmlsl_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 37f338732e..0c3b3de961 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -766,3 +766,157 @@ DO_FMLA_IDX(gvec_fmla_idx_s, float32, H4) DO_FMLA_IDX(gvec_fmla_idx_d, float64, ) #undef DO_FMLA_IDX + +/* + * Convert float16 to float32, raising no exceptions and + * preserving exceptional values, including SNaN. + * This is effectively an unpack+repack operation. + */ +static float32 float16_to_float32_by_bits(uint32_t f16) +{ + const int f16_bias = 15; + const int f32_bias = 127; + uint32_t sign = extract32(f16, 15, 1); + uint32_t exp = extract32(f16, 10, 5); + uint32_t frac = extract32(f16, 0, 10); + + if (exp == 0x1f) { + /* Inf or NaN */ + exp = 0xff; + } else if (exp == 0) { + /* Zero or denormal. */ + if (frac != 0) { + /* + * Denormal; these are all normal float32. + * Shift the fraction so that the msb is at bit 11, + * then remove bit 11 as the implicit bit of the + * normalized float32. Note that we still go through + * the shift for normal numbers below, to put the + * float32 fraction at the right place. + */ + int shift = clz32(frac) - 21; + frac = (frac << shift) & 0x3ff; + exp = f32_bias - f16_bias - shift + 1; + } + } else { + /* Normal number; adjust the bias. */ + exp += f32_bias - f16_bias; + } + sign <<= 31; + exp <<= 23; + frac <<= 23 - 10; + + return sign | exp | frac; +} + +static float32 fmlal(float32 a, float16 n16, float16 m16, float_status *fpst) +{ + float32 n = float16_to_float32_by_bits(n16); + float32 m = float16_to_float32_by_bits(m16); + return float32_muladd(n, m, a, 0, fpst); +} + +static float32 fmlsl(float32 a, float16 n16, float16 m16, float_status *fpst) +{ + float32 n = float16_to_float32_by_bits(n16); + float32 m = float16_to_float32_by_bits(m16); + return float32_muladd(float32_chs(n), m, a, 0, fpst); +} + +static inline uint64_t load4_f16(uint64_t *ptr, int is_q, int is_2) +{ + /* + * Branchless load of u32[0], u64[0], u32[1], or u64[1]. + * Load the 2nd qword iff is_q & is_2. + * Shift to the 2nd dword iff !is_q & is_2. + * For !is_q & !is_2, the upper bits of the result are garbage. + */ + return ptr[is_q & is_2] >> ((is_2 & ~is_q) << 5); +} + +/* + * Note that FMLAL and FMLSL require oprsz == 8 or oprsz == 16, + * as there is not yet SVE versions that might use blocking. + */ + +void HELPER(gvec_fmlal_h)(void *vd, void *vn, void *vm, + void *fpst, uint32_t desc) +{ + intptr_t i, oprsz = simd_oprsz(desc); + int is_2 = extract32(desc, SIMD_DATA_SHIFT, 1); + int is_q = oprsz == 16; + float32 *d = vd; + uint64_t n_4, m_4; + + /* Pre-load all of the f16 data, avoiding overlap issues. */ + n_4 = load4_f16(vn, is_q, is_2); + m_4 = load4_f16(vm, is_q, is_2); + + for (i = 0; i < oprsz / 4; i++) { + d[H4(i)] = fmlal(d[H4(i)], extract64(n_4, i*16, 16), + extract64(m_4, i*16, 16), fpst); + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_fmlsl_h)(void *vd, void *vn, void *vm, + void *fpst, uint32_t desc) +{ + intptr_t i, oprsz = simd_oprsz(desc); + int is_2 = extract32(desc, SIMD_DATA_SHIFT, 1); + int is_q = oprsz == 16; + float32 *d = vd; + uint64_t n_4, m_4; + + /* Pre-load all of the f16 data, avoiding overlap issues. */ + n_4 = load4_f16(vn, is_q, is_2); + m_4 = load4_f16(vm, is_q, is_2); + + for (i = 0; i < oprsz / 4; i++) { + d[H4(i)] = fmlsl(d[H4(i)], extract64(n_4, i*16, 16), + extract64(m_4, i*16, 16), fpst); + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_fmlal_idx_h)(void *vd, void *vn, void *vm, + void *fpst, uint32_t desc) +{ + intptr_t i, oprsz = simd_oprsz(desc); + int is_2 = extract32(desc, SIMD_DATA_SHIFT, 1); + int index = extract32(desc, SIMD_DATA_SHIFT + 1, 3); + int is_q = oprsz == 16; + float32 *d = vd; + uint64_t n_4; + float16 m_1; + + /* Pre-load all of the f16 data, avoiding overlap issues. */ + n_4 = load4_f16(vn, is_q, is_2); + m_1 = ((float16 *)vm)[H2(index)]; + + for (i = 0; i < oprsz / 4; i++) { + d[H4(i)] = fmlal(d[H4(i)], extract64(n_4, i * 16, 16), m_1, fpst); + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_fmlsl_idx_h)(void *vd, void *vn, void *vm, + void *fpst, uint32_t desc) +{ + intptr_t i, oprsz = simd_oprsz(desc); + int is_2 = extract32(desc, SIMD_DATA_SHIFT, 1); + int index = extract32(desc, SIMD_DATA_SHIFT + 1, 3); + int is_q = oprsz == 16; + float32 *d = vd; + uint64_t n_4; + float16 m_1; + + /* Pre-load all of the f16 data, avoiding overlap issues. */ + n_4 = load4_f16(vn, is_q, is_2); + m_1 = ((float16 *)vm)[H2(index)]; + + for (i = 0; i < oprsz / 4; i++) { + d[H4(i)] = fmlsl(d[H4(i)], extract64(n_4, i*16, 16), m_1, fpst); + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} From patchwork Thu Feb 14 03:43:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158306 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp872967jaa; Wed, 13 Feb 2019 19:58:50 -0800 (PST) X-Google-Smtp-Source: AHgI3IaF29U6ZBXorxRpKzvzgLeu5fsGd9nqg0nNNXreK1QN2jOZru5MZPXI5R0FbKOF0X0HhqW1 X-Received: by 2002:a25:2102:: with SMTP id h2mr1314710ybh.363.1550116730105; Wed, 13 Feb 2019 19:58:50 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550116730; 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id o2sm972713pgq.90.2019.02.13.19.43.49 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Feb 2019 19:43:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 13 Feb 2019 19:43:43 -0800 Message-Id: <20190214034345.24722-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190214034345.24722-1-richard.henderson@linaro.org> References: <20190214034345.24722-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH 2/4] target/arm: Implement FMLAL and FMLSL for aarch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++++ target/arm/translate-a64.c | 49 +++++++++++++++++++++++++++++++++++++- 2 files changed, 53 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47238e4245..15085a94ff 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3305,6 +3305,11 @@ static inline bool isar_feature_aa64_dp(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, DP) != 0; } +static inline bool isar_feature_aa64_fhm(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, FHM) != 0; +} + static inline bool isar_feature_aa64_fcma(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, FCMA) != 0; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e002251ac6..d2ee811489 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10891,9 +10891,26 @@ static void disas_simd_3same_float(DisasContext *s, uint32_t insn) if (!fp_access_check(s)) { return; } - handle_3same_float(s, size, elements, fpopcode, rd, rn, rm); return; + + case 0x1d: /* FMLAL */ + case 0x3d: /* FMLSL */ + case 0x59: /* FMLAL2 */ + case 0x79: /* FMLSL2 */ + if (size & 1 || !dc_isar_feature(aa64_fhm, s)) { + unallocated_encoding(s); + return; + } + if (fp_access_check(s)) { + gen_gvec_op3_fpst(s, is_q, rd, rn, rm, false, + extract32(insn, 29, 1), + extract32(insn, 23, 1) + ? gen_helper_gvec_fmlsl_h + : gen_helper_gvec_fmlal_h); + } + return; + default: unallocated_encoding(s); return; @@ -12724,6 +12741,17 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } is_fp = 2; break; + case 0x00: /* FMLAL */ + case 0x04: /* FMLSL */ + case 0x18: /* FMLAL2 */ + case 0x1c: /* FMLSL2 */ + if (is_scalar || size != MO_32 || !dc_isar_feature(aa64_fhm, s)) { + unallocated_encoding(s); + return; + } + size = MO_16; + is_fp = 3; + break; default: unallocated_encoding(s); return; @@ -12765,6 +12793,9 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } break; + case 3: /* other fp, size already set and verified. */ + break; + default: /* integer */ switch (size) { case MO_8: @@ -12834,6 +12865,22 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) tcg_temp_free_ptr(fpst); } return; + + case 0x00: /* FMLAL */ + case 0x04: /* FMLSL */ + case 0x18: /* FMLAL2 */ + case 0x1c: /* FMLSL2 */ + { + int data = (index << 1) | u; + tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), fpst, + is_q ? 16 : 8, vec_full_reg_size(s), data, + opcode & 4 ? gen_helper_gvec_fmlsl_idx_h + : gen_helper_gvec_fmlal_idx_h); + tcg_temp_free_ptr(fpst); + } + return; } if (size == 3) { From patchwork Thu Feb 14 03:43:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158309 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp876535jaa; Wed, 13 Feb 2019 20:03:17 -0800 (PST) X-Google-Smtp-Source: AHgI3IZO2kPKL5SnFK3EpPaor7JEc6Q/afVH0FD/sI350Bdxpz8Nu4UR8KCdgmJOZMkJ3ba8J2sw X-Received: by 2002:a25:ab52:: with SMTP id u76mr1395167ybi.143.1550116997925; Wed, 13 Feb 2019 20:03:17 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550116997; cv=none; d=google.com; s=arc-20160816; b=r3dJHkrn0iGH3Ilj8LsWjbGcOg1xlf8p59Grnpqk09r1gSY0zr4/8ntaCsNeyV8eYK XaQnuTRDqs/QxIjQVtqalzPJDs2YJWyCW/3NyYmoOI8v3GKi2QS1n4fCAcIcFPUvs3Xt 9Fozq5UZqnuoLso/VytFDJ94f3FBKX0x4dm2M+Owd99wBrnACtqOXV34P0QtR0//R+Rq 2V++hnjbHtnL+2ohU17kNnJEYu4w4Z87MtJLLFriHshffjrLnsuss9hyOpo6wMyCIKvn cDb43FUdCQ+7I2RyTlpxvOchh2ygbIgfWh/wOKq6gxHPTjbjfxn2e+SkepJXUYMIAIFG HfoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=+3uqZJoPHf7H0MV6qZLBPTy2QZidE62Ds6I3+3j8avw=; b=LYawSfHjnDga2HVUJw5rvlORqFS+GxTvW48EWcPA5/hdZhjjZtnaZqhGZXqAA+LQ6L RfWf5ETCCW9pUxldyOFdJnf9RUOMm7AK2W+CzwlN6iz13AX8SjkW8VcZfkB09Mb7zbOk ofwmIRBvwiRnUjaaHOZTK++vxZHg3UTqVOmaciNPkCbtnSRTW7bxt+mYD9IeTnW1KTn/ 7qYIyiyb6GIWyJqimuBGttU9JP7vSvnCNifohjFvK5U+rvE9ELQc9xLr6q58YcxhUnDH ojm6zirl18YczJZwTeF8LsijlRXYdV6GPmrzh640ILhCLJFaMdcv5PoFmZQvH/7VLPdL E5PQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=ApmbJmSv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id o2sm972713pgq.90.2019.02.13.19.43.50 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Feb 2019 19:43:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 13 Feb 2019 19:43:44 -0800 Message-Id: <20190214034345.24722-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190214034345.24722-1-richard.henderson@linaro.org> References: <20190214034345.24722-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH 3/4] target/arm: Implement VFMAL and VFMSL for aarch32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++ target/arm/translate.c | 104 +++++++++++++++++++++++++++++------------ 2 files changed, 80 insertions(+), 29 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 15085a94ff..84d24044fe 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3232,6 +3232,11 @@ static inline bool isar_feature_aa32_dp(const ARMISARegisters *id) return FIELD_EX32(id->id_isar6, ID_ISAR6, DP) != 0; } +static inline bool isar_feature_aa32_fhm(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_isar6, ID_ISAR6, FHM) != 0; +} + static inline bool isar_feature_aa32_fp16_arith(const ARMISARegisters *id) { /* diff --git a/target/arm/translate.c b/target/arm/translate.c index 66cf28c8cb..0ed4768080 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -8236,15 +8236,8 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL; int rd, rn, rm, opr_sz; int data = 0; - bool q; - - q = extract32(insn, 6, 1); - VFP_DREG_D(rd, insn); - VFP_DREG_N(rn, insn); - VFP_DREG_M(rm, insn); - if ((rd | rn | rm) & q) { - return 1; - } + int off_rn, off_rm; + bool is_long = false, q = extract32(insn, 6, 1); if ((insn & 0xfe200f10) == 0xfc200800) { /* VCMLA -- 1111 110R R.1S .... .... 1000 ...0 .... */ @@ -8271,10 +8264,38 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) return 1; } fn_gvec = u ? gen_helper_gvec_udot_b : gen_helper_gvec_sdot_b; + } else if ((insn & 0xff300f10) == 0xfc200810) { + /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */ + int sub = extract32(insn, 23, 1); + if (!dc_isar_feature(aa32_fhm, s)) { + return 1; + } + is_long = true; + fn_gvec_ptr = sub ? gen_helper_gvec_fmlsl_h : gen_helper_gvec_fmlal_h; + data = 0; /* is_2 == 0 */ } else { return 1; } + VFP_DREG_D(rd, insn); + if (rd & q) { + return 1; + } + if (q || !is_long) { + VFP_DREG_N(rn, insn); + VFP_DREG_M(rm, insn); + if ((rn | rm) & q & !is_long) { + return 1; + } + off_rn = vfp_reg_offset(1, rn); + off_rm = vfp_reg_offset(1, rm); + } else { + rn = VFP_SREG_N(insn); + rm = VFP_SREG_M(insn); + off_rn = vfp_reg_offset(0, rn); + off_rm = vfp_reg_offset(0, rm); + } + if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); @@ -8287,15 +8308,11 @@ static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn) opr_sz = (1 + q) * 8; if (fn_gvec_ptr) { TCGv_ptr fpst = get_fpstatus_ptr(1); - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), fpst, + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, fpst, opr_sz, opr_sz, data, fn_gvec_ptr); tcg_temp_free_ptr(fpst); } else { - tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), + tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm, opr_sz, opr_sz, data, fn_gvec); } return 0; @@ -8314,14 +8331,8 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) gen_helper_gvec_3 *fn_gvec = NULL; gen_helper_gvec_3_ptr *fn_gvec_ptr = NULL; int rd, rn, rm, opr_sz, data; - bool q; - - q = extract32(insn, 6, 1); - VFP_DREG_D(rd, insn); - VFP_DREG_N(rn, insn); - if ((rd | rn) & q) { - return 1; - } + int off_rn, off_rm; + bool is_long = false, q = extract32(insn, 6, 1); if ((insn & 0xff000f10) == 0xfe000800) { /* VCMLA (indexed) -- 1111 1110 S.RR .... .... 1000 ...0 .... */ @@ -8350,6 +8361,7 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) } else if ((insn & 0xffb00f00) == 0xfe200d00) { /* V[US]DOT -- 1111 1110 0.10 .... .... 1101 .Q.U .... */ int u = extract32(insn, 4, 1); + if (!dc_isar_feature(aa32_dp, s)) { return 1; } @@ -8357,10 +8369,48 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) /* rm is just Vm, and index is M. */ data = extract32(insn, 5, 1); /* index */ rm = extract32(insn, 0, 4); + } else if ((insn & 0xffa00f10) == 0xfe000810) { + /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */ + int sub = extract32(insn, 20, 1); + int vm20 = extract32(insn, 0, 3); + int vm3 = extract32(insn, 3, 1); + int m = extract32(insn, 5, 1); + int index; + + if (!dc_isar_feature(aa32_fhm, s)) { + return 1; + } + if (q) { + rm = vm20; + index = m * 2 + vm3; + } else { + rm = vm20 * 2 + m; + index = vm3; + } + is_long = true; + data = index << 1; /* is_2 == 0 */ + fn_gvec_ptr = (sub ? gen_helper_gvec_fmlsl_idx_h + : gen_helper_gvec_fmlal_idx_h); } else { return 1; } + VFP_DREG_D(rd, insn); + if (rd & q) { + return 1; + } + if (q || !is_long) { + VFP_DREG_N(rn, insn); + if (rn & q & !is_long) { + return 1; + } + off_rn = vfp_reg_offset(1, rn); + off_rm = vfp_reg_offset(1, rm); + } else { + rn = VFP_SREG_N(insn); + off_rn = vfp_reg_offset(0, rn); + off_rm = vfp_reg_offset(0, rm); + } if (s->fp_excp_el) { gen_exception_insn(s, 4, EXCP_UDEF, syn_simd_access_trap(1, 0xe, false), s->fp_excp_el); @@ -8373,15 +8423,11 @@ static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn) opr_sz = (1 + q) * 8; if (fn_gvec_ptr) { TCGv_ptr fpst = get_fpstatus_ptr(1); - tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), fpst, + tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, fpst, opr_sz, opr_sz, data, fn_gvec_ptr); tcg_temp_free_ptr(fpst); } else { - tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), - vfp_reg_offset(1, rn), - vfp_reg_offset(1, rm), + tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm, opr_sz, opr_sz, data, fn_gvec); } return 0; From patchwork Thu Feb 14 03:43:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 158308 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp875411jaa; Wed, 13 Feb 2019 20:01:56 -0800 (PST) X-Google-Smtp-Source: AHgI3IZRrLWBXVdduyArdwkg01bQoQ/ohWoybYkfZ2KQf88mHm0QBGkWZ7JU1IGy0XnvqEtdRdVP X-Received: by 2002:a25:e684:: with SMTP id d126mr1375745ybh.92.1550116916880; Wed, 13 Feb 2019 20:01:56 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550116916; cv=none; d=google.com; s=arc-20160816; b=umHxsYDUfK32jDds8ttFNBZ3+ju/9aASaxpSlRUgS3SOZl/gTNykZnAuB0aoBkGyPw VOgwwkf2nrtI2x0FYloqpuniT8MKPBX6pgcScEdbJx6xUE9ddc6QvvtKoMdC6pNyXK+e RukPs/QpA/aBtAfXyx67uuBsmTEK49wldZxFCHDp4/kcfbnip46N9obo1UDHscSjVCmG OntxV4tt/KIzY066BHop+smdeo4ky27+6GYHiTsWNDlBS/3iTdEyH/ojg4G69bFRM1J4 cYJAnvcarDggGl6jVpx311RU44223DksVJIT7pwBDJwUvaLVOZxrOoutoem1aHvzuKmn 2caQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=cbskW479OhNUzyJNbm1VlQPK+6mCdYvQdwJmmMsXd+Q=; b=HJXLpBcLhCVwvVwXEocZBECNuwrQIUVfEsS7Y6NOBtOkAMoI+0psL7S4FbeHC3soJW MRWQFsQFZC3A/yDs4Sfwt1J8qqP+PU1S+lvE6waf4TvdqvzkESrJ1Ve3Xqh6yMRFrY+5 RqpBz0X4F1IDSLqFTnWadZX78tvR6NOqkOD6FWJWVweeMe8MMdZvP9c6mxgMDE8FGqz2 fGiJhkVAQsY1AbnSAMsQsvO0jMTm7Ssr3y4s8lNMynXVx4s4AmE903T5KPzJ0+x1T82d md8JQ74vLjHZbm+USVnm73k0Ud3PQRv30N0Cre62c9w61XFjAcIkJIQX0RH5scZn3Wf4 pTuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=LCl+ylO6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.113.188.82]) by smtp.gmail.com with ESMTPSA id o2sm972713pgq.90.2019.02.13.19.43.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 13 Feb 2019 19:43:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 13 Feb 2019 19:43:45 -0800 Message-Id: <20190214034345.24722-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190214034345.24722-1-richard.henderson@linaro.org> References: <20190214034345.24722-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH 4/4] target/arm: Enable ARMv8.2-FHM for -cpu max X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/cpu.c | 1 + target/arm/cpu64.c | 2 ++ 2 files changed, 3 insertions(+) -- 2.17.2 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index edf6e0e1f1..f4aa6202f5 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2002,6 +2002,7 @@ static void arm_max_initfn(Object *obj) t = cpu->isar.id_isar6; t = FIELD_DP32(t, ID_ISAR6, DP, 1); + t = FIELD_DP32(t, ID_ISAR6, FHM, 1); cpu->isar.id_isar6 = t; t = cpu->id_mmfr4; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eff0f164dd..bffce337a4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -308,6 +308,7 @@ static void aarch64_max_initfn(Object *obj) t = FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1); + t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); cpu->isar.id_aa64isar0 = t; t = cpu->isar.id_aa64isar1; @@ -345,6 +346,7 @@ static void aarch64_max_initfn(Object *obj) u = cpu->isar.id_isar6; u = FIELD_DP32(u, ID_ISAR6, DP, 1); + u = FIELD_DP32(u, ID_ISAR6, FHM, 1); cpu->isar.id_isar6 = u; /*