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[59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d40400b001750361f430sm4484728ple.155.2022.09.08.07.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 07:44:32 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v3 1/6] dt-bindings: sifive-ccache: change Sifive L2 cache to Composable cache Date: Thu, 8 Sep 2022 14:44:19 +0000 Message-Id: <20220908144424.4232-2-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220908144424.4232-1-zong.li@sifive.com> References: <20220908144424.4232-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Since composable cache may be L3 cache if private L2 cache exists, we should use its original name Composable cache to prevent confusion. Signed-off-by: Zong Li Suggested-by: Conor Dooley Suggested-by: Ben Dooks Reviewed-by: Conor Dooley --- ...five-l2-cache.yaml => sifive,ccache0.yaml} | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) rename Documentation/devicetree/bindings/riscv/{sifive-l2-cache.yaml => sifive,ccache0.yaml} (83%) diff --git a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml similarity index 83% rename from Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml rename to Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml index ca3b9be58058..bf3f07421f7e 100644 --- a/Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml +++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml @@ -2,18 +2,18 @@ # Copyright (C) 2020 SiFive, Inc. %YAML 1.2 --- -$id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml# +$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: SiFive L2 Cache Controller +title: SiFive Composable Cache Controller maintainers: - Sagar Kadam - Paul Walmsley description: - The SiFive Level 2 Cache Controller is used to provide access to fast copies - of memory for masters in a Core Complex. The Level 2 Cache Controller also + The SiFive Composable Cache Controller is used to provide access to fast copies + of memory for masters in a Core Complex. The Composable Cache Controller also acts as directory-based coherency manager. All the properties in ePAPR/DeviceTree specification applies for this platform. @@ -22,6 +22,7 @@ select: compatible: contains: enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache @@ -33,6 +34,7 @@ properties: oneOf: - items: - enum: + - sifive,ccache0 - sifive,fu540-c000-ccache - sifive,fu740-c000-ccache - const: cache @@ -45,7 +47,7 @@ properties: const: 64 cache-level: - const: 2 + enum: [2, 3] cache-sets: enum: [1024, 2048] @@ -115,6 +117,22 @@ allOf: cache-sets: const: 1024 + - if: + properties: + compatible: + contains: + const: sifive,ccache0 + + then: + properties: + cache-level: + enum: [2, 3] + + else: + properties: + cache-level: + const: 2 + additionalProperties: false required: From patchwork Thu Sep 8 14:44:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 603974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CA01C6FA86 for ; Thu, 8 Sep 2022 14:45:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232654AbiIHOpC (ORCPT ); Thu, 8 Sep 2022 10:45:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44368 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232670AbiIHOou (ORCPT ); Thu, 8 Sep 2022 10:44:50 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2F34B1D327 for ; Thu, 8 Sep 2022 07:44:41 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id l65so18148662pfl.8 for ; Thu, 08 Sep 2022 07:44:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=wbDb2kYWAgkEIDQJ0UPQIA/ni5c6F+53yNgIrgtwFqg=; b=RPY6YbXBMfH6OjFQCvIy89jlsC0KuKV5tW0FbZ+TIVdlcGl3QeYd+tWC9H+HQSlah5 MSg6DLrxaEIPFDl4i8nXe/D6YWR8XkalmkKHlO48poWzIyuls1jf+Z/bGkOxFwv7XBeM HF+evbgdHPBfYvxGw0fnwmSzw5jPSGU586SQAVLr/ow9mTtsIpxCb2cT8ULwLIdwhyCS r9FDWOU5zG5K56WgQnPYTcjpg7hCQwAHhk5GWZcuaaJ0PMLNGClwnH/m4Fpl63FExsKE bDfTOdiXd8+vEKpnPwZKn/dnWiuXJQO/jZFOpWbOj0kLZ7lTcUaJEADeeJpchHB/Rp4W rOag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=wbDb2kYWAgkEIDQJ0UPQIA/ni5c6F+53yNgIrgtwFqg=; b=6tCbDNDG9i1ca0bNF5Lp9Bti7rsPKctpWMU/wk4pcqsCVE0fNkYfxIFKJtNA/2BwQc vMrKWNn4RcghVpXELlXNbr77q+ozgBGxtACzCXvcG3CXbth2vGvrwmUA5qqzAnDzeCyR Ry8eYxDcDAm6zpThyQPkyKstDmOUDRK1Pg/B1iSLK71CeUExFQ2JKODD9yIpXS/1lfA1 EZY3rFEplEzpwHgJLymPjwburLEtHcXpxUmAMtYRmCimyuur9dItTjv7/T9OQCjBeHm5 Jwt4gdcGUZL91T9sQSmLWu4MvnUdyJGyJcL6fuFqjkkiHoM4AGkXHqOtQSB1aKQLNgK+ soRg== X-Gm-Message-State: ACgBeo2yq9jSDOY42MU6oBBEsnrDGnynO9qwfUEropVFwm6LB1BxbeCq ggQkN008kmldz88dEjxyvIN4JQ== X-Google-Smtp-Source: AA6agR663AyOqfGUkOT49zEGbKqr9aPBFRFvp4ECi5xXjdQRyEI1Zr+ZkPWMBtnpfODNRLJFqlEmng== X-Received: by 2002:a63:5b42:0:b0:429:d283:8a51 with SMTP id l2-20020a635b42000000b00429d2838a51mr8342571pgm.610.1662648279862; Thu, 08 Sep 2022 07:44:39 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d40400b001750361f430sm4484728ple.155.2022.09.08.07.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 07:44:39 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v3 3/6] soc: sifive: ccache: determine the cache level from dts Date: Thu, 8 Sep 2022 14:44:21 +0000 Message-Id: <20220908144424.4232-4-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220908144424.4232-1-zong.li@sifive.com> References: <20220908144424.4232-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Composable cache could be L2 or L3 cache, use 'cache-level' property of device node to determine the level. Signed-off-by: Zong Li Signed-off-by: Greentime Hu --- drivers/soc/sifive/sifive_ccache.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index 949b824e89ad..690c19489317 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -38,6 +38,7 @@ static void __iomem *ccache_base; static int g_irq[SIFIVE_CCACHE_MAX_ECCINTR]; static struct riscv_cacheinfo_ops ccache_cache_ops; +static int level; enum { DIR_CORR = 0, @@ -144,7 +145,7 @@ static const struct attribute_group *ccache_get_priv_group(struct cacheinfo *this_leaf) { /* We want to use private group for composable cache only */ - if (this_leaf->level == 2) + if (this_leaf->level == level) return &priv_attr_group; else return NULL; @@ -215,6 +216,9 @@ static int __init sifive_ccache_init(void) if (!ccache_base) return -ENOMEM; + if (of_property_read_u32(np, "cache-level", &level)) + return -ENODEV; + intr_num = of_property_count_u32_elems(np, "interrupts"); if (!intr_num) { pr_err("CCACHE: no interrupts property\n"); From patchwork Thu Sep 8 14:44:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Zong Li X-Patchwork-Id: 603973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6F50FC6FA8A for ; Thu, 8 Sep 2022 14:45:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232674AbiIHOpI (ORCPT ); Thu, 8 Sep 2022 10:45:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232666AbiIHOpC (ORCPT ); Thu, 8 Sep 2022 10:45:02 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 536701A389 for ; Thu, 8 Sep 2022 07:44:50 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id u9-20020a17090a1f0900b001fde6477464so2554365pja.4 for ; Thu, 08 Sep 2022 07:44:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=references:in-reply-to:message-id:date:subject:cc:to:from:from:to :cc:subject:date; bh=J1tHlju2+cXYieX/pEOr8qlvVRzsaNnqR5zd8sgRAW4=; b=gmV61+9vUSmtpDQFopsJ2ku3wTMWgbaDlPMVRXv9AHl4iBvo7ocd62TOfwkJbaLlD3 sdT+g6nLvNMzHUhHmtJMNBASiEfsmw5xvFYEEpF5JM8o+Z95TepA0A+CNZRGuWl2+0Ib FSOAE6spy6vcklkB7VHY1c58jGl7J+cTfUZGw3XEpdmxWADy8O7kPJ70CNnTLI4noPYb 3kDm38AsD9c3hqaGc0CFGnWsvAUdNYGezZtE2RgipI8yB0lzYIr45BNTI/FRQzPqNSq2 TPB8PMf0lwv6udO9FeRhJ7E/YjNbr2+Col9SKCnYpk4TdSc9Kyt66l7al4XJYsNNmdU9 rxHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=references:in-reply-to:message-id:date:subject:cc:to:from :x-gm-message-state:from:to:cc:subject:date; bh=J1tHlju2+cXYieX/pEOr8qlvVRzsaNnqR5zd8sgRAW4=; b=6Uqi98Me3xvc1BAIPTN/qgD7bcBTW6QWZBZ51QcfomaZJ2jk0IEoZ2+Gp0ntknGLfI oQaDx6qkHEtR+h5drH67o82N+hb+yS7xOL7i2kX2tzk+97koWj4RL2gL+fhrV249ZGhn 5tFgSy5SK38eWLohSaHAPwQDLTuuIUKMbsBQhgZtdo8Jv6jfmWrLawOSaGArD1JI97Kq lxWW8L1D2JX+LbbIKdQ8OFLjrTiQcKQqgJTq8jYtfzYJIWQc2gEVNFmnc6g0Sf4cKwCz Xnh997uFUEARLn+NubdLnOaiVyhLx4AkhzRb91f7bIKos7xg/gavyv2PvIBkPKDmo7cf 0KXw== X-Gm-Message-State: ACgBeo1FrV/8FF7QDtVq7q9SCiQhukboJEF2CVn7A9Z/St45wGqOR3Yw mk+ne5/nqmj37Jyz3+3ExLMOxA== X-Google-Smtp-Source: AA6agR40T8VGOwQPVPXwn0xDEJUAihdvvc+xd5Ba8Hk/nOFgbOdiZAU3choIZea4zpjK/11k8ZrXAg== X-Received: by 2002:a17:902:d2c7:b0:176:c8a4:2f2 with SMTP id n7-20020a170902d2c700b00176c8a402f2mr9425217plc.119.1662648289321; Thu, 08 Sep 2022 07:44:49 -0700 (PDT) Received: from localhost.localdomain (59-124-168-89.hinet-ip.hinet.net. [59.124.168.89]) by smtp.gmail.com with ESMTPSA id b4-20020a170902d40400b001750361f430sm4484728ple.155.2022.09.08.07.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Sep 2022 07:44:48 -0700 (PDT) From: Zong Li To: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu, greentime.hu@sifive.com, conor.dooley@microchip.com, ben.dooks@sifive.com, bp@alien8.de, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Zong Li Subject: [PATCH v3 6/6] soc: sifive: ccache: define the macro for the register shifts Date: Thu, 8 Sep 2022 14:44:24 +0000 Message-Id: <20220908144424.4232-7-zong.li@sifive.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220908144424.4232-1-zong.li@sifive.com> References: <20220908144424.4232-1-zong.li@sifive.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define the macro for the register shifts, it could make the code be more readable Signed-off-by: Zong Li --- drivers/soc/sifive/sifive_ccache.c | 16 +++++++++++----- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/drivers/soc/sifive/sifive_ccache.c b/drivers/soc/sifive/sifive_ccache.c index b3929c4d6d5b..0ddcc657c694 100644 --- a/drivers/soc/sifive/sifive_ccache.c +++ b/drivers/soc/sifive/sifive_ccache.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -33,6 +34,11 @@ #define SIFIVE_CCACHE_DATECCFAIL_COUNT 0x168 #define SIFIVE_CCACHE_CONFIG 0x00 +#define SIFIVE_CCACHE_CONFIG_BANK_MASK GENMASK_ULL(7, 0) +#define SIFIVE_CCACHE_CONFIG_WAYS_MASK GENMASK_ULL(15, 8) +#define SIFIVE_CCACHE_CONFIG_SETS_MASK GENMASK_ULL(23, 16) +#define SIFIVE_CCACHE_CONFIG_BLKS_MASK GENMASK_ULL(31, 24) + #define SIFIVE_CCACHE_WAYENABLE 0x08 #define SIFIVE_CCACHE_ECCINJECTERR 0x40 @@ -87,11 +93,11 @@ static void ccache_config_read(void) u32 cfg; cfg = readl(ccache_base + SIFIVE_CCACHE_CONFIG); - - pr_info("%u banks, %u ways, sets/bank=%llu, bytes/block=%llu\n", - (cfg & 0xff), (cfg >> 8) & 0xff, - BIT_ULL((cfg >> 16) & 0xff), - BIT_ULL((cfg >> 24) & 0xff)); + pr_info("%llu banks, %llu ways, sets/bank=%llu, bytes/block=%llu\n", + FIELD_GET(SIFIVE_CCACHE_CONFIG_BANK_MASK, cfg), + FIELD_GET(SIFIVE_CCACHE_CONFIG_WAYS_MASK, cfg), + BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_SETS_MASK, cfg)), + BIT_ULL(FIELD_GET(SIFIVE_CCACHE_CONFIG_BLKS_MASK, cfg))); cfg = readl(ccache_base + SIFIVE_CCACHE_WAYENABLE); pr_info("Index of the largest way enabled: %u\n", cfg);