From patchwork Wed Feb 13 15:44:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 158234 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp216599jaa; Wed, 13 Feb 2019 07:45:51 -0800 (PST) X-Google-Smtp-Source: AHgI3IZkbrOjaFMu6oU1t3RKT5lHwShipDhR+ceArNYnasCvjxXzCCaCrYBcPQfn1QmiumAP6COV X-Received: by 2002:a81:1e13:: with SMTP id e19mr5334181ywe.234.1550072751420; Wed, 13 Feb 2019 07:45:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550072751; cv=none; d=google.com; s=arc-20160816; b=wjVJUJju+bm86NbRnMF51r+v4ZB5eiZTmVwrCVHNRNpBv1QZcHjn71UP8j1eztcacx cTErOgCpl3nzb3P2x54DMcB+q86jf5Tii38d50xdnROS73ff0/ZjtoNJlVL0QkXgRol2 FV4jDTSGiMamdq8vUw58AQRMvpKmHk5nZKfdV/tPK+z515/jya30BtNqFZIYxYRr0m2v Xo/7uUqkCYkBF+qjHpRd+C55P7IvGInIkhPzhX4RM1Rk47mSG11UH14LOnAjW9HeHrGk B+CLjGdRhj77OUPAh8GeBx9wsOUEW/Jr9Eaj5kg8vP6bkphib91qZ8xkuorouJVsoJ9m dETA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from:references :in-reply-to:message-id:date:dkim-signature; bh=z6Oe5++7//00+8jf3KOesDxKK2wIxkTBsez1SGK1Kro=; b=xHtVijDnleGwb9J/6g0HCZz8PmUCi5tpZI97/6djYUgmwd8zwGqRT4Ab4Uwq9/GqOn fJiarGqjPg+BGi7thJm4N8UVU6f51yKmbY/Z0M5hZW+TFOyKqMQClFVaUfVA8Kgq9Pyk qhjQH6K4DuSeg0njAECpsjl8Nmiwm90Lmy1iqya38Pkc2jC44Hs6oDG5o8wlXC+jLOrq YezJvcaFHPxJ8SCaz7EimXoqMpcnPJX9r47QCeKvGCfANfjFxL9pPzEdwuvlj6frlSFS cj92ZD/HGuGFv7JZoy1SYklPjEwQ4yv/GSSVtEOmxXn7Ep6h+3+uFjGXyYbHQyKbDBCE OtXQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@sifive.com header.s=google header.b=h+lk7J0Z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::634 Subject: [Qemu-devel] [PULL 01/11] RISC-V: Split out mstatus_fs from tb_flags X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Richard Henderson , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Signed-off-by: Michael Clark Reviewed-by: Michael Clark Signed-off-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.h | 6 +++--- target/riscv/translate.c | 10 +++++----- 2 files changed, 8 insertions(+), 8 deletions(-) -- 2.18.1 diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 743f02c8b95a..681341f5d5a4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -275,8 +275,8 @@ void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, target_ulong cpu_riscv_get_fflags(CPURISCVState *env); void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong); -#define TB_FLAGS_MMU_MASK 3 -#define TB_FLAGS_FP_ENABLE MSTATUS_FS +#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_MSTATUS_FS MSTATUS_FS static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, target_ulong *cs_base, uint32_t *flags) @@ -284,7 +284,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, *pc = env->pc; *cs_base = 0; #ifdef CONFIG_USER_ONLY - *flags = TB_FLAGS_FP_ENABLE; + *flags = TB_FLAGS_MSTATUS_FS; #else *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); #endif diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 312bf298b3c2..3d07d651b60c 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -44,7 +44,7 @@ typedef struct DisasContext { /* pc_succ_insn points to the instruction following base.pc_next */ target_ulong pc_succ_insn; uint32_t opcode; - uint32_t flags; + uint32_t mstatus_fs; uint32_t mem_idx; /* Remember the rounding mode encoded in the previous fp instruction, which we have already installed into env->fp_status. Or -1 for @@ -656,7 +656,7 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -686,7 +686,7 @@ static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, { TCGv t0; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { gen_exception_illegal(ctx); return; } @@ -945,7 +945,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, { TCGv t0 = NULL; - if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + if (ctx->mstatus_fs == 0) { goto do_illegal; } @@ -1818,8 +1818,8 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) DisasContext *ctx = container_of(dcbase, DisasContext, base); ctx->pc_succ_insn = ctx->base.pc_first; - ctx->flags = ctx->base.tb->flags; ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; + ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS; ctx->frm = -1; /* unknown rounding mode */ } From patchwork Wed Feb 13 15:44:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 158235 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp219325jaa; Wed, 13 Feb 2019 07:49:05 -0800 (PST) X-Google-Smtp-Source: AHgI3IYJ4DGgW/n8KXvUj05fu+2NoX/UeoHGBnVg3HK3+tdhPYTiKL1AKkWyMSScnBnmfd2nIUXL X-Received: by 2002:a0d:eac3:: with SMTP id t186mr4985013ywe.73.1550072945929; Wed, 13 Feb 2019 07:49:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1550072945; cv=none; d=google.com; s=arc-20160816; b=uLBJvWUyLk6KL14S8nSOHb/c71Zd+xBIh5q8+L5JbI2jFekk0kYJE/7qTUjmCNuCxv ra2ISE3XhRF3qhJ8/0EbXQJbqOa22HVbxhoIgsIUlCa7rNq5tsis5v2bYnjIhmPx3P3S sVkUF1nqHgW02TuBfc5/F1mrqVhHpokxINOflJ0Pb/jN1txeKWyVLo5J6McdMzInG2Mq rPNUd7Je7uslEPhzD/L7X3y6p7wSaEoJM58gbompw9nBSYkiQno1CUC6r2PzIuBT/5Q6 1yeKYlpuusth30EC36ntG+RLDMSTQbGCYcJ35BVQBYzdX+zcZRy44pKufj3vFglxXCCo rMzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:to:from:references :in-reply-to:message-id:date:dkim-signature; bh=m3QyX5GKKen9C2A//gm0itW+Zbw+s4kREoS0dubIg4I=; b=IEg4duuxNg8n/oqjN1k9Vq7NcILFK9xMqiwZmK2jg98X4o/UW+RKkJdiGbG1sIJytY JLHI9t9zWuHx4ACaEFnIPilBNjyGinUDDrkkPJ01nfYqxgDhNCtK1V19699dUISFoWqY obGphFFBKrsXhT9+KB8VFkrX+Sg2CwtJhURnjt75zMCSL7vDqlc2fOKTsKO3rEn9fTSX n/U4ZNgz5fiKzHIQQ3pOq2RY8iJ3J5OG1l90ebVPyBEd/nynTgnq7LJxRPNa1YLYdcVd IiJGKjHtxhwU9BMbI8PwBkVuOnTFryh+Lz0sKq7UL3xAqx5NGtf9/TJveyk1bdL2Y2ig 7wpw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@sifive.com header.s=google header.b="kCTva/bC"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org" Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::432 Subject: [Qemu-devel] [PULL 02/11] RISC-V: Mark mstatus.fs dirty X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Richard Henderson , qemu-devel@nongnu.org, Michael Clark , Alistair Francis Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson Modifed from Richard Henderson's patch [1] to integrate with the new control and status register implementation. [1] https://lists.nongnu.org/archive/html/qemu-devel/2018-03/msg07034.html Note: the f* CSRs already mark mstatus.FS dirty using env->mstatus |= mstatus.FS so the bug in the first spin of this patch has been fixed in a prior commit. Signed-off-by: Michael Clark Reviewed-by: Michael Clark Signed-off-by: Alistair Francis Co-authored-by: Richard Henderson Co-authored-by: Michael Clark Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 12 ------------ target/riscv/translate.c | 40 +++++++++++++++++++++++++++++++++++++++- 2 files changed, 39 insertions(+), 13 deletions(-) -- 2.18.1 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5e7e7d16b8b5..571414768992 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -317,18 +317,6 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) mstatus = (mstatus & ~mask) | (val & mask); - /* Note: this is a workaround for an issue where mstatus.FS - does not report dirty after floating point operations - that modify floating point state. This workaround is - technically compliant with the RISC-V Privileged - specification as it is legal to return only off, or dirty. - at the expense of extra floating point save/restore. */ - - /* FP is always dirty or off */ - if (mstatus & MSTATUS_FS) { - mstatus |= MSTATUS_FS; - } - int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | ((mstatus & MSTATUS_XS) == MSTATUS_XS); mstatus = set_field(mstatus, MSTATUS_SD, dirty); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 3d07d651b60c..0581b3c1f7d7 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -651,6 +651,31 @@ static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, tcg_temp_free(dat); } +#ifndef CONFIG_USER_ONLY +/* The states of mstatus_fs are: + * 0 = disabled, 1 = initial, 2 = clean, 3 = dirty + * We will have already diagnosed disabled state, + * and need to turn initial/clean into dirty. + */ +static void mark_fs_dirty(DisasContext *ctx) +{ + TCGv tmp; + if (ctx->mstatus_fs == MSTATUS_FS) { + return; + } + /* Remember the state change for the rest of the TB. */ + ctx->mstatus_fs = MSTATUS_FS; + + tmp = tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_gen_ori_tl(tmp, tmp, MSTATUS_FS); + tcg_gen_st_tl(tmp, cpu_env, offsetof(CPURISCVState, mstatus)); + tcg_temp_free(tmp); +} +#else +static inline void mark_fs_dirty(DisasContext *ctx) { } +#endif + static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, target_long imm) { @@ -679,6 +704,8 @@ static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, break; } tcg_temp_free(t0); + + mark_fs_dirty(ctx); } static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, @@ -944,6 +971,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, int rs2, int rm) { TCGv t0 = NULL; + bool fp_output = true; if (ctx->mstatus_fs == 0) { goto do_illegal; @@ -1006,6 +1034,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_W_S: @@ -1035,6 +1064,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_S_W: @@ -1085,6 +1115,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FMV_S_X: @@ -1177,6 +1208,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_W_D: @@ -1206,6 +1238,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } gen_set_gpr(rd, t0); tcg_temp_free(t0); + fp_output = false; break; case OPC_RISC_FCVT_D_W: @@ -1254,6 +1287,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, default: goto do_illegal; } + fp_output = false; break; #if defined(TARGET_RISCV64) @@ -1271,7 +1305,11 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t0); } gen_exception_illegal(ctx); - break; + return; + } + + if (fp_output) { + mark_fs_dirty(ctx); } }