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[Patch v2 01/15] dt-bindings: media: s5p-mfc: Add new DT schema for MFC Date: Wed, 7 Sep 2022 12:17:01 +0530 Message-Id: <20220907064715.55778-2-smitha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220907064715.55778-1-smitha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTf1CTdRzH7/s82/MMaNzToPrGFa2n6JL4scmGX1DCTrLnwoyT7rrrShjb 0+CAbW3DAjOXkx+igAVeiIAEKBci4IQ5flg0UfxB3A2Q6dmCEEHwvCEkBdNqbFj/vT4/3p/P 5/v5fr88XDBBBPEyVHpWq5Jl0YQvx3xhXWh420YoFz2wEuiO5SgXTdSaCdTw1wyGxhsWOch6 tpNEHaPHcNQ00MdFx/uHuOjcz5McdOauO2o76uCgmeOtAM1W/UYg0+0xLvp97kM00l1NoEPt nVx0ut9BohN2G4ZOmh5hqL7zDxLln+8nkaPXDND+gn5sM2RaalsAY3E0AsbeuIAzXVUOkmno ncUYU/MBgvl1rJdgzjbuZfIvrnCY0o5mwPy9r4ZkivvtBLNoCmauPlwkk/w/ytyUzsoUrFbI quRqRYZKGUcnJqdsSZFGi8Th4hi0gRaqZNlsHJ2wLSl8a0aWew20cJcsK8ftSpLpdHTkm5u0 6hw9K0xX6/RxNKtRZGkkmgidLFuXo1JGqFh9rFgkWi91J6Zmpt+3Xic150RfzFQYcQO48mox 8OFBSgIP7LtEFANfnoDqAfCWsx54jQUApxrbuV5jCcD5O/OcYsDzSAptEq//PICHvx3HVksJ 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20220907063313epcas5p114f793010fd0f2797e93bd83ed18a1d7 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220907063313epcas5p114f793010fd0f2797e93bd83ed18a1d7 References: <20220907064715.55778-1-smitha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Adds DT schema for s5p-mfc in yaml format Signed-off-by: Aakarsh Jain Signed-off-by: Smitha T Murthy --- .../devicetree/bindings/media/s5p-mfc.txt | 77 +------------ .../bindings/media/samsung,s5p-mfc.yaml | 109 ++++++++++++++++++ 2 files changed, 110 insertions(+), 76 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml diff --git a/Documentation/devicetree/bindings/media/s5p-mfc.txt b/Documentation/devicetree/bindings/media/s5p-mfc.txt index aa54c8159d9f..0b7c4dd40095 100644 --- a/Documentation/devicetree/bindings/media/s5p-mfc.txt +++ b/Documentation/devicetree/bindings/media/s5p-mfc.txt @@ -1,76 +1 @@ -* Samsung Multi Format Codec (MFC) - -Multi Format Codec (MFC) is the IP present in Samsung SoCs which -supports high resolution decoding and encoding functionalities. -The MFC device driver is a v4l2 driver which can encode/decode -video raw/elementary streams and has support for all popular -video codecs. - -Required properties: - - compatible : value should be either one among the following - (a) "samsung,mfc-v5" for MFC v5 present in Exynos4 SoCs - (b) "samsung,mfc-v6" for MFC v6 present in Exynos5 SoCs - (c) "samsung,mfc-v7" for MFC v7 present in Exynos5420 SoC - (d) "samsung,mfc-v8" for MFC v8 present in Exynos5800 SoC - (e) "samsung,exynos5433-mfc" for MFC v8 present in Exynos5433 SoC - (f) "samsung,mfc-v10" for MFC v10 present in Exynos7880 SoC - - - reg : Physical base address of the IP registers and length of memory - mapped region. - - - interrupts : MFC interrupt number to the CPU. - - clocks : from common clock binding: handle to mfc clock. - - clock-names : from common clock binding: must contain "mfc", - corresponding to entry in the clocks property. - -Optional properties: - - power-domains : power-domain property defined with a phandle - to respective power domain. - - memory-region : from reserved memory binding: phandles to two reserved - memory regions, first is for "left" mfc memory bus interfaces, - second if for the "right" mfc memory bus, used when no SYSMMU - support is available; used only by MFC v5 present in Exynos4 SoCs - -Obsolete properties: - - samsung,mfc-r, samsung,mfc-l : support removed, please use memory-region - property instead - - -Example: -SoC specific DT entry: - -mfc: codec@13400000 { - compatible = "samsung,mfc-v5"; - reg = <0x13400000 0x10000>; - interrupts = <0 94 0>; - power-domains = <&pd_mfc>; - clocks = <&clock 273>; - clock-names = "mfc"; -}; - -Reserved memory specific DT entry for given board (see reserved memory binding -for more information): - -reserved-memory { - #address-cells = <1>; - #size-cells = <1>; - ranges; - - mfc_left: region@51000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x51000000 0x800000>; - }; - - mfc_right: region@43000000 { - compatible = "shared-dma-pool"; - no-map; - reg = <0x43000000 0x800000>; - }; -}; - -Board specific DT entry: - -codec@13400000 { - memory-region = <&mfc_left>, <&mfc_right>; -}; +This file has moved to samsung,s5p-mfc.yaml diff --git a/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml new file mode 100644 index 000000000000..7cd26d4acbe4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/samsung,s5p-mfc.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/samsung,s5p-mfc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung Exynos Multi Format Codec (MFC) + +maintainers: + - Marek Szyprowski + - Aakarsh Jain + +description: + Multi Format Codec (MFC) is the IP present in Samsung SoCs which + supports high resolution decoding and encoding functionalities. + +properties: + compatible: + enum: + - samsung,mfc-v5 # Exynos4 + - samsung,mfc-v6 # Exynos5 + - samsung,mfc-v7 # Exynos5420 + - samsung,mfc-v8 # Exynos5800 + - samsung,exynos5433-mfc # Exynos5433 + - samsung,mfc-v10 # Exynos7880 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 3 + + clock-names: + minItems: 1 + maxItems: 3 + + interrupts: + maxItems: 1 + + iommus: + maxItems: 2 + + iommu-names: + maxItems: 2 + + power-domains: + maxItems: 1 + + memory-region: + maxItems: 1 + +allOf: + - if: + properties: + compatible: + contains: + enum: + - samsung,mfc-v5 + then: + properties: + memory-region: + maxItems: 2 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +additionalProperties: false + +examples: + - | + # SoC specific DT entry + mfc: mfc@12880000 { + compatible = "samsung,fsd-mfc"; + reg = <0x0 0x12880000 0x0 0x10000>; + interrupts = ; + clock-names = "mfc"; + clocks = <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>; + iommus = <&smmu_isp 0x1000 0x0>, <&smmu_isp 0x1400 0x0>; + iommu-names = "left", "right"; + power-domains = <&pd_mfc>; + memory-region = <&mfc_left>, <&mfc_right>; + }; + + - | + # Reserved memory specific DT entry for given board + # (see reserved memory binding for more information) + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mfc_left: region@84000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0x84000000 0x800000>; + }; + + mfc_right: region@a9000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0xa9000000 0x800000>; + }; + }; + From patchwork Wed Sep 7 06:47:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smitha T Murthy X-Patchwork-Id: 603560 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on 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20220907063319epsmtip19a37f3b3c6ee9845a5d1ec6a33d283ea~SgGiqp9B02638126381epsmtip1A; Wed, 7 Sep 2022 06:33:19 +0000 (GMT) From: Smitha T Murthy To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v2 03/15] media: s5p-mfc: Rename IS_MFCV10 macro Date: Wed, 7 Sep 2022 12:17:03 +0530 Message-Id: <20220907064715.55778-4-smitha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: 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<20220907064715.55778-1-smitha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Renames macro IS_MFCV10 to IS_MFCV10_PLUS so that the MFCv10 code can be resued for MFCv12 support. Since some part of MFCv10 specific code holds good for MFCv12 also. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy --- .../platform/samsung/s5p-mfc/s5p_mfc_common.h | 10 +++---- .../platform/samsung/s5p-mfc/s5p_mfc_ctrl.c | 2 +- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 28 +++++++++---------- 3 files changed, 20 insertions(+), 20 deletions(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h index 5304f42c8c72..e6ec4a43b290 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h @@ -771,11 +771,11 @@ void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq); #define HAS_PORTNUM(dev) (dev ? (dev->variant ? \ (dev->variant->port_num ? 1 : 0) : 0) : 0) #define IS_TWOPORT(dev) (dev->variant->port_num == 2 ? 1 : 0) -#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60 ? 1 : 0) -#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70 ? 1 : 0) -#define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80 ? 1 : 0) -#define IS_MFCV10(dev) (dev->variant->version >= 0xA0 ? 1 : 0) -#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10(dev)) +#define IS_MFCV6_PLUS(dev) (dev->variant->version >= 0x60) +#define IS_MFCV7_PLUS(dev) (dev->variant->version >= 0x70) +#define IS_MFCV8_PLUS(dev) (dev->variant->version >= 0x80) +#define IS_MFCV10_PLUS(dev) (dev->variant->version >= 0xA0) +#define FW_HAS_E_MIN_SCRATCH_BUF(dev) (IS_MFCV10_PLUS(dev)) #define MFC_V5_BIT BIT(0) #define MFC_V6_BIT BIT(1) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c index 72d70984e99a..ffe9f7e79eca 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_ctrl.c @@ -236,7 +236,7 @@ int s5p_mfc_init_hw(struct s5p_mfc_dev *dev) else mfc_write(dev, 0x3ff, S5P_FIMV_SW_RESET); - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_write(dev, 0x0, S5P_FIMV_MFC_CLOCK_OFF_V10); mfc_debug(2, "Will now wait for completion of firmware transfer\n"); diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c index 8227004f6746..728d255e65fc 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c @@ -72,9 +72,9 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->luma_size, ctx->chroma_size, ctx->mv_size); mfc_debug(2, "Totals bufs: %d\n", ctx->total_dpb_count); } else if (ctx->type == MFCINST_ENCODER) { - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) ctx->tmv_buffer_size = 0; - } else if (IS_MFCV8_PLUS(dev)) + else if (IS_MFCV8_PLUS(dev)) ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V8(mb_width, mb_height), S5P_FIMV_TMV_BUFFER_ALIGN_V6); @@ -82,7 +82,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->tmv_buffer_size = S5P_FIMV_NUM_TMV_BUFFERS_V6 * ALIGN(S5P_FIMV_TMV_BUFFER_SIZE_V6(mb_width, mb_height), S5P_FIMV_TMV_BUFFER_ALIGN_V6); - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { lcu_width = S5P_MFC_LCU_WIDTH(ctx->img_width); lcu_height = S5P_MFC_LCU_HEIGHT(ctx->img_height); if (ctx->codec_mode != S5P_FIMV_CODEC_HEVC_ENC) { @@ -133,7 +133,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) switch (ctx->codec_mode) { case S5P_MFC_CODEC_H264_DEC: case S5P_MFC_CODEC_H264_MVC_DEC: - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_debug(2, "Use min scratch buffer size\n"); else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = @@ -152,7 +152,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) (ctx->mv_count * ctx->mv_size); break; case S5P_MFC_CODEC_MPEG4_DEC: - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_debug(2, "Use min scratch buffer size\n"); else if (IS_MFCV7_PLUS(dev)) { ctx->scratch_buf_size = @@ -172,7 +172,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) break; case S5P_MFC_CODEC_VC1RCV_DEC: case S5P_MFC_CODEC_VC1_DEC: - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_debug(2, "Use min scratch buffer size\n"); else ctx->scratch_buf_size = @@ -189,7 +189,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank2.size = 0; break; case S5P_MFC_CODEC_H263_DEC: - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_debug(2, "Use min scratch buffer size\n"); else ctx->scratch_buf_size = @@ -201,7 +201,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank1.size = ctx->scratch_buf_size; break; case S5P_MFC_CODEC_VP8_DEC: - if (IS_MFCV10(dev)) + if (IS_MFCV10_PLUS(dev)) mfc_debug(2, "Use min scratch buffer size\n"); else if (IS_MFCV8_PLUS(dev)) ctx->scratch_buf_size = @@ -230,7 +230,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) DEC_VP9_STATIC_BUFFER_SIZE; break; case S5P_MFC_CODEC_H264_ENC: - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); ctx->me_buffer_size = ALIGN(ENC_V100_H264_ME_SIZE(mb_width, mb_height), 16); @@ -254,7 +254,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) break; case S5P_MFC_CODEC_MPEG4_ENC: case S5P_MFC_CODEC_H263_ENC: - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); ctx->me_buffer_size = ALIGN(ENC_V100_MPEG4_ME_SIZE(mb_width, @@ -273,7 +273,7 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->bank2.size = 0; break; case S5P_MFC_CODEC_VP8_ENC: - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { mfc_debug(2, "Use min scratch buffer size\n"); ctx->me_buffer_size = ALIGN(ENC_V100_VP8_ME_SIZE(mb_width, mb_height), @@ -452,7 +452,7 @@ static void s5p_mfc_dec_calc_dpb_size_v6(struct s5p_mfc_ctx *ctx) if (ctx->codec_mode == S5P_MFC_CODEC_H264_DEC || ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) { - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { ctx->mv_size = S5P_MFC_DEC_MV_SIZE_V10(ctx->img_width, ctx->img_height); } else { @@ -668,7 +668,7 @@ static int s5p_mfc_set_enc_ref_buffer_v6(struct s5p_mfc_ctx *ctx) mfc_debug(2, "Buf1: %p (%d)\n", (void *)buf_addr1, buf_size1); - if (IS_MFCV10(dev)) { + if (IS_MFCV10_PLUS(dev)) { /* start address of per buffer is aligned */ for (i = 0; i < ctx->pb_count; i++) { writel(buf_addr1, mfc_regs->e_luma_dpb + (4 * i)); @@ -2455,7 +2455,7 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) R(e_h264_options, S5P_FIMV_E_H264_OPTIONS_V8); R(e_min_scratch_buffer_size, S5P_FIMV_E_MIN_SCRATCH_BUFFER_SIZE_V8); - if (!IS_MFCV10(dev)) + if (!IS_MFCV10_PLUS(dev)) goto done; /* Initialize registers used in MFC v10 only. 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Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy --- .../media/v4l/ext-ctrls-codec.rst | 167 ++++++++++++++++++ 1 file changed, 167 insertions(+) diff --git a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst index 2a165ae063fb..2277d83a7cf0 100644 --- a/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst +++ b/Documentation/userspace-api/media/v4l/ext-ctrls-codec.rst @@ -2187,6 +2187,16 @@ enum v4l2_mpeg_video_vp8_profile - * - ``V4L2_MPEG_VIDEO_VP8_PROFILE_3`` - Profile 3 +VP9 Control Reference +--------------------- + +The VP9 controls include controls for encoding parameters of VP9 video +codec. + +.. _vp9-control-id: + +VP9 Control IDs + .. _v4l2-mpeg-video-vp9-profile: ``V4L2_CID_MPEG_VIDEO_VP9_PROFILE`` @@ -2253,6 +2263,163 @@ enum v4l2_mpeg_video_vp9_level - * - ``V4L2_MPEG_VIDEO_VP9_LEVEL_6_2`` - Level 6.2 +``V4L2_CID_CODEC_VP9_I_FRAME_QP`` + Quantization parameter for an I frame for VP9. Valid range: from 1 to 255. + +``V4L2_CID_CODEC_VP9_P_FRAME_QP`` + Quantization parameter for an P frame for VP9. Valid range: from 1 to 255. + +``V4L2_CID_CODEC_VP9_MAX_QP`` + Maximum quantization parameter for VP9. Valid range: from 1 to 255. + Recommended range for MFC is from 230 to 255. + +``V4L2_CID_CODEC_VP9_MIN_QP`` + Minimum quantization parameter for VP9. Valid range: from 1 to 255. + Recommended range for MFC is from 1 to 24. + +``V4L2_CID_CODEC_VP9_RC_FRAME_RATE`` + Indicates the number of evenly spaced subintervals, called ticks, within + one second. This is a 16 bit unsigned integer and has a maximum value up to + 0xffff and a minimum value of 1. + +``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` + Indicates the refresh period of the golden frame for VP9 encoder. + +.. _v4l2-vp9-golden-frame-sel: + +``V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL`` + (enum) + +enum v4l2_mpeg_vp9_golden_framesel - + Selects the golden frame for encoding. Valid when NUM_OF_REF is 2. + Possible values are: + +.. raw:: latex + + \footnotesize + +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV`` + - Use the (n-2)th frame as a golden frame, current frame index being + 'n'. + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD`` + - Use the previous specific frame indicated by + ``V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD`` as a + golden frame. + +.. raw:: latex + + \normalsize + + +``V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE`` + Allows host to specify the quantization parameter values for each + temporal layer through HIERARCHICAL_QP_LAYER. This is valid only + if HIERARCHICAL_CODING_LAYER is greater than 1. Setting the control + value to 1 enables setting of the QP values for the layers. + +.. _v4l2-vp9-ref-number-of-pframes: + +``V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES`` + (enum) + +enum v4l2_mpeg_vp9_ref_num_for_pframes - + Number of reference pictures for encoding P frames. + +.. raw:: latex + + \footnotesize + +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + * - ``V4L2_CID_CODEC_VP9_1_REF_PFRAME`` + - Indicates one reference frame, last encoded frame will be searched. + * - ``V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD`` + - Indicates 2 reference frames, last encoded frame and golden frame + will be searched. + +.. raw:: latex + + \normalsize + + +``V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER`` + Indicates the number of hierarchial coding layer. + In normal encoding (non-hierarchial coding), it should be zero. + VP9 has upto 3 layer of encoder. + +``V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE`` + Indicates enabling of bit rate for hierarchical coding layers VP9 encoder. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR`` + Indicates bit rate for hierarchical coding layer 0 for VP9 encoder. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR`` + Indicates bit rate for hierarchical coding layer 1 for VP9 encoder. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR`` + Indicates bit rate for hierarchical coding layer 2 for VP9 encoder. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP`` + Indicates quantization parameter for hierarchical coding layer 0. + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP, + V4L2_CID_CODEC_VP9_MAX_QP]. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP`` + Indicates quantization parameter for hierarchical coding layer 1. + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP, + V4L2_CID_CODEC_VP9_MAX_QP]. + +``V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP`` + Indicates quantization parameter for hierarchical coding layer 2. + Valid range: [V4L2_CID_CODEC_VP9_MIN_QP, + V4L2_CID_CODEC_VP9_MAX_QP]. + +.. _v4l2-vp9-max-partition-depth: + +``V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH`` + (enum) + +enum v4l2_mpeg_vp9_num_partitions - + Indicate maximum coding unit depth. + +.. raw:: latex + + \footnotesize + +.. tabularcolumns:: |p{9.0cm}|p{8.0cm}| + +.. flat-table:: + :header-rows: 0 + :stub-columns: 0 + + * - ``V4L2_CID_CODEC_VP9_0_PARTITION`` + - No coding unit partition depth. + * - ``V4L2_CID_CODEC_VP9_1_PARTITION`` + - Allows one coding unit partition depth. + +.. raw:: latex + + \normalsize + + +``V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT`` + Zero indicates enable intra NxN PU split. + One indicates disable intra NxN PU split. + +``V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER`` + Indicates IVF header generation. Zero indicates enable IVF format. + One indicates disable IVF format. + High Efficiency Video Coding (HEVC/H.265) Control Reference =========================================================== From patchwork Wed Sep 7 06:47:07 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smitha T Murthy X-Patchwork-Id: 603558 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90C7CC38145 for ; Wed, 7 Sep 2022 06:37:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229994AbiIGGhG (ORCPT ); Wed, 7 Sep 2022 02:37:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49870 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229981AbiIGGhF (ORCPT ); Wed, 7 Sep 2022 02:37:05 -0400 Received: from mailout2.samsung.com (mailout2.samsung.com [203.254.224.25]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D998286700 for ; Tue, 6 Sep 2022 23:36:36 -0700 (PDT) Received: from epcas5p2.samsung.com (unknown [182.195.41.40]) by mailout2.samsung.com (KnoxPortal) with ESMTP id 20220907063634epoutp027204ec3d70ced01fb64e2118984a4c9d~SgJYfupQf0553305533epoutp02G for ; Wed, 7 Sep 2022 06:36:34 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 mailout2.samsung.com 20220907063634epoutp027204ec3d70ced01fb64e2118984a4c9d~SgJYfupQf0553305533epoutp02G DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=samsung.com; s=mail20170921; t=1662532594; bh=NQWsb4RqKxQPijk9VzjtYpuZhWQOFu052/B3OQdNnMs=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ICLImu7pr+cg/s1JtUe9IWhAc++tnvM/EmnXWSOe6rQlQvzbDv274bF7R+2KL4DU5 jJvG1NE4/r9ZBYNDyTSqF2lvk337x4JAXI4oZvKeed9bkHN7mbQuvRI/zZ9tOP0M+R Qlug96Bhv1QxULbR/X6tZtHMp5+GrZBcsK6r2Pw4= Received: from epsnrtp2.localdomain (unknown [182.195.42.163]) by epcas5p3.samsung.com (KnoxPortal) with ESMTP id 20220907063633epcas5p3e79d620c6d7634ee7ff431b1d98f71e6~SgJXikwKc0368303683epcas5p3-; Wed, 7 Sep 2022 06:36:33 +0000 (GMT) Received: from epsmges5p2new.samsung.com (unknown [182.195.38.178]) by epsnrtp2.localdomain (Postfix) with ESMTP id 4MMswY5mWqz4x9Q0; Wed, 7 Sep 2022 06:36:29 +0000 (GMT) Received: from epcas5p4.samsung.com ( [182.195.41.42]) by epsmges5p2new.samsung.com (Symantec Messaging Gateway) with SMTP id CE.53.53458.AEB38136; Wed, 7 Sep 2022 15:36:26 +0900 (KST) Received: from epsmtrp2.samsung.com (unknown [182.195.40.14]) by epcas5p2.samsung.com (KnoxPortal) with ESMTPA id 20220907063340epcas5p2d7eb2452918dfc593c47f48d05cfb83b~SgG2MTIQy0472404724epcas5p2S; Wed, 7 Sep 2022 06:33:40 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp2.samsung.com (KnoxPortal) with ESMTP id 20220907063340epsmtrp273c79c086f3c98874741392dc94b0a6e~SgG2LEffa1916519165epsmtrp2A; Wed, 7 Sep 2022 06:33:40 +0000 (GMT) X-AuditID: b6c32a4a-a5bff7000000d0d2-0c-63183bead58f Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 38.DC.14392.44B38136; Wed, 7 Sep 2022 15:33:40 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.109.115.6]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220907063336epsmtip12efc78b19c9eb3abde794aefe4a415f5~SgGyxT-s52432724327epsmtip1c; Wed, 7 Sep 2022 06:33:36 +0000 (GMT) From: Smitha T Murthy To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v2 07/15] media: s5p-mfc: Add support for VP9 encoder. Date: Wed, 7 Sep 2022 12:17:07 +0530 Message-Id: <20220907064715.55778-8-smitha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220907064715.55778-1-smitha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTe0xbVRzHPX3dstnlhocemjhJzRbBAS0r9ZTXdOByM/cA1C2bGHZtbwqh r/W2uDGMKK+NwB46ojAeCsURNsZWnk4wwKoFhgQmlEyoUJjyCK+tyogwY0uL/vf5/X7f3+P8 zjlcpredw+emqvWUTk0qBZxtrJZ7gUHB85FQJvzy2m70e1sJG01WtHBQ9doMA01UO1iou7EZ Q03D15jouqWTjSrNA2zU2jXFQndmndGhEhsLzVTeAmiu9DcOMk1b2cg+fxz9creMgwpvN7NR vdmGoZrRIQb61rTBQFXNf2Iot8OMIVt7C0A5eWbGG5C4WXETEG02IyBGjU+YxHelNoyobp9j EKa6Cxxi3NrOIRqNnxC5P/7NIi421QHin8/KMaLAPMohHKadRN9fDix+x8m0qBSKlFO6AEot 08hT1YpowdvvJMcmh0uEomCRFL0uCFCTKipaEHcoPvhAqtK5BkFAOqk0OF3xJE0LQmOidBqD ngpI0dD6aAGllSu1Ym0ITapog1oRoqb0ESKhMCzcKTyVljJlucTWPiwEZ3KtlVgWeEgXAC8u xMXw0VIXqwBs43rj3wN4wTqGuY0nAE46Vj3GKoD1pZOMrZS6jqccF3vjHU5VLnJzNgNOZ0e7 mIPvgavL9zc1vvinAE6f17sKMfFsFrT1r2OugA9+AJYvP94UsfBd8OLyAsvFPFwKxwprWe5m L8MbtzuZLvbCI+DQ1R62qxDE871gV7/JI4qDtZWLmJt94LylycN86Fjq4LhZAScc2cDNWlie 1eQ5zT7YOVzmrMN1ThcIG+6Gut0vweK+W5sSJr4DFq0/8sh5sK1iiwWwqr/H0wrCkcVmtpsJ WFM/y3BvrgjA3pw+5mWws/T/Fl8DUAf8KS2tUlB0uDZMTX3037XJNCoT2HzrQQfbgH1yJaQb MLigG0AuU+DLk7f5yrx5cvJsBqXTJOsMSoruBuHOBV5h8v1kGudnUeuTRWKpUCyRSMTSvRKR 4EXe1deAzBtXkHoqjaK0lG4rj8H14mcxYkSH2XmNqsj9K0TsgtEYmiSfW89/5VwCumKgn5/t UZ08Js0pCSOOhuMf2gPPB4wUf5N5/dT6q09B9pA1L8JnJqPsLUnLACnrbGrM+EnKbf8itlz+ a4L53YO89y+ZVh/U2ONm/UmuhWeI3bi3kVBlESUeOzEcEhrhM5L5s/+6bu1y5MSgOE/93oMT Z0taKxoOpXcl7m/8uGifbXuKIske+mx8Ip/I8D9T/XmmwSrsXTndYEpLWpIpnw3dqU98PLar wHj/cPzeqDfrb+TWbO89Z0kv+cprcHfq+B/8PTbMb2pBS6/xa6tK/XyLbV0vBLUeh8+d7phY PGIY+CG/ImbwA6QWsOgUUhTE1NHkv2gIrPl0BAAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprBIsWRmVeSWpSXmKPExsWy7bCSnK6LtUSywfJZohZPd8xktXgwbxub xeIfz5ks7i/+zGJxaPNWdostV2YzWyw/foDVYv6Rc6wW2w8+YrHY+AIoe3HmXRaL5/PXMVq8 nHWPzWLT42usFg9fhVtc3jWHzaJnw1ZWi7VH7rJbLL1+kcli2aY/TBaLtn5ht2jde4Td4u6e bYwWLW1HmBwkPNbMW8PosePuEkaP60s+MXvsnHWX3WPxnpdMHptWdbJ53Lm2h81j85J6j9aj v1g8+rasYvT41zSX3aPryHU2j8+b5DxOff3MHsAXxWWTkpqTWZZapG+XwJXx6Hg/a8HNHsaK 1mvz2RsYbxZ3MXJySAiYSKza+50NxBYS2M0o8eJcMkRcQmLl70mMELawxMp/z9khahqZJFrX mILYbAI6Et/enwbq5eIQEWhllLi+spMJxGEWmM0i8WPSAVaQKmEBN4m57z+CbWARUJXoe/+G BcTmFbCUuN2zggVig7zE6g0HmEFsTgEriYtTTrBCbLOUeDxjG/sERr4FjAyrGCVTC4pz03OL DQsM81LL9YoTc4tL89L1kvNzNzGCI09Lcwfj9lUf9A4xMnEwHmKU4GBWEuFN2SGSLMSbklhZ lVqUH19UmpNafIhRmoNFSZz3QtfJeCGB9MSS1OzU1ILUIpgsEwenVAOTrIzskwOn3B8sUp9n vHj6/Enm6ptvVtu9iZh8WMldfomYYceFGWETXP9mrH115YjIrJrwyEN+63b73fW6nGEQsCT/ /oEnBVbXlv25oJp7w29X+uy52w+f2ukYF/TyTP6pV6dW2nuoOkZUzJRvXqWjmyQn8tCsfqvv sRDTHeXB3/ZUviubd+030yH/exKzJOMKVb5aTpoyMypcKf7b2Qfnw1KNeT5HrtSKsfS407Pa 1XFlxeI19+6aT+I4cF4qt+lORcj0WMU9zzZcUu811nA7eG9JueKFyeuvbZpc6vjy5ULBk5Yn ee9ynnx2pKhUuOYo9/OZa6+ofFQI/ek0obJqiY7dpGjhyg7Ja6f9BTUT4pVYijMSDbWYi4oT AQtz3+wrAwAA X-CMS-MailID: 20220907063340epcas5p2d7eb2452918dfc593c47f48d05cfb83b X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220907063340epcas5p2d7eb2452918dfc593c47f48d05cfb83b References: <20220907064715.55778-1-smitha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add VP9 encoder support and necessary registers, V4L2 CIDs, vp9 encoder parameters. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy --- .../platform/samsung/s5p-mfc/regs-mfc-v12.h | 8 + .../platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c | 3 + .../platform/samsung/s5p-mfc/s5p_mfc_common.h | 27 +- .../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 272 ++++++++++++++++++ .../platform/samsung/s5p-mfc/s5p_mfc_opr.h | 2 + .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 121 ++++++++ 6 files changed, 432 insertions(+), 1 deletion(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h index 6c68a45082d0..7cb74a9cb769 100644 --- a/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h +++ b/drivers/media/platform/samsung/s5p-mfc/regs-mfc-v12.h @@ -12,6 +12,10 @@ #include #include "regs-mfc-v10.h" +/* MFCv12 register definitions*/ +#define S5P_FIMV_E_VP9_OPTION_V12 0xFD90 +#define S5P_FIMV_E_VP9_GOLDEN_FRAME_OPTION_V12 0xFD98 + /* MFCv12 Context buffer sizes */ #define MFC_CTX_BUF_SIZE_V12 (30 * SZ_1K) #define MFC_H264_DEC_CTX_BUF_SIZE_V12 (2 * SZ_1M) @@ -47,4 +51,8 @@ ALIGN((((x + 3) * (y + 3) * 32) \ + (((y * 128) + 2304) * (x + 3) / 4)), 256) +#define ENC_V120_VP9_ME_SIZE(x, y) \ + ((((x * 2) + 3) * ((y * 2) + 3) * 128) \ + + (((y * 256) + 2304) * (x + 1) / 2)) + #endif /*_REGS_MFC_V12_H*/ diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c index f8588e52dfc8..d524815cd38a 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_cmd_v6.c @@ -121,6 +121,9 @@ static int s5p_mfc_open_inst_cmd_v6(struct s5p_mfc_ctx *ctx) case S5P_MFC_CODEC_HEVC_ENC: codec_type = S5P_FIMV_CODEC_HEVC_ENC; break; + case S5P_MFC_CODEC_VP9_ENC: + codec_type = S5P_FIMV_CODEC_VP9_ENC; + break; default: codec_type = S5P_FIMV_CODEC_NONE_V6; } diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h index 088fd1c96b96..870d57bcf346 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_common.h @@ -57,7 +57,7 @@ #define MFC_ENC_CAP_PLANE_COUNT 1 #define MFC_ENC_OUT_PLANE_COUNT 2 #define STUFF_BYTE 4 -#define MFC_MAX_CTRLS 128 +#define MFC_MAX_CTRLS 147 #define S5P_MFC_CODEC_NONE -1 #define S5P_MFC_CODEC_H264_DEC 0 @@ -77,6 +77,7 @@ #define S5P_MFC_CODEC_H263_ENC 23 #define S5P_MFC_CODEC_VP8_ENC 24 #define S5P_MFC_CODEC_HEVC_ENC 26 +#define S5P_MFC_CODEC_VP9_ENC 27 #define S5P_MFC_R2H_CMD_EMPTY 0 #define S5P_MFC_R2H_CMD_SYS_INIT_RET 1 @@ -483,6 +484,29 @@ struct s5p_mfc_hevc_enc_params { u8 prepend_sps_pps_to_idr; }; +/** + * struct s5p_mfc_vp9_enc_params - encoding parameters for vp9 + */ +struct s5p_mfc_vp9_enc_params { + u32 rc_framerate; + u8 vp9_profile; + u8 rc_min_qp; + u8 rc_max_qp; + u8 rc_frame_qp; + u8 rc_p_frame_qp; + u8 vp9_goldenframesel; + u8 vp9_gfrefreshperiod; + u8 hier_qp_enable; + u8 hier_qp_layer[3]; + u8 hier_rc_enable; + u32 hier_bit_layer[3]; + u8 num_refs_for_p; + u8 num_hier_layer; + u8 max_partition_depth; + u8 intra_pu_split_disable; + u8 ivf_header; +}; + /* * struct s5p_mfc_enc_params - general encoding parameters */ @@ -521,6 +545,7 @@ struct s5p_mfc_enc_params { struct s5p_mfc_mpeg4_enc_params mpeg4; struct s5p_mfc_vp8_enc_params vp8; struct s5p_mfc_hevc_enc_params hevc; + struct s5p_mfc_vp9_enc_params vp9; } codec; }; diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c index 26e3ed2e2b6f..f15324e64aec 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c @@ -94,6 +94,13 @@ static struct s5p_mfc_fmt formats[] = { .num_planes = 1, .versions = MFC_V10_BIT | MFC_V12_BIT, }, + { + .fourcc = V4L2_PIX_FMT_VP9, + .codec_mode = S5P_FIMV_CODEC_VP9_ENC, + .type = MFC_FMT_ENC, + .num_planes = 1, + .versions = MFC_V12_BIT, + }, }; #define NUM_FORMATS ARRAY_SIZE(formats) @@ -1055,6 +1062,174 @@ static struct mfc_control controls[] = { .step = 1, .default_value = 0, }, + { + .id = V4L2_CID_MPEG_VIDEO_VP9_PROFILE, + .type = V4L2_CTRL_TYPE_MENU, + .minimum = V4L2_MPEG_VIDEO_VP9_PROFILE_0, + .maximum = V4L2_MPEG_VIDEO_VP9_PROFILE_2, + .step = 1, + .default_value = V4L2_MPEG_VIDEO_VP9_PROFILE_0, + }, + { + .id = V4L2_CID_CODEC_VP9_I_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 1, + .maximum = 255, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_CODEC_VP9_P_FRAME_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 1, + .maximum = 255, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_CODEC_VP9_MAX_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 230, + .maximum = 255, + .step = 1, + .default_value = 255, + }, + { + .id = V4L2_CID_CODEC_VP9_MIN_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 1, + .maximum = 24, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_CODEC_VP9_RC_FRAME_RATE, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 1, + .maximum = (1 << 16) - 1, + .step = 1, + .default_value = 1, + }, + { + .id = V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL, + .type = V4L2_CTRL_TYPE_MENU, + .minimum = V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV, + .maximum = V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_REF_PERIOD, + .step = 1, + .default_value = V4L2_CID_CODEC_VP9_GOLDEN_FRAME_USE_PREV, + }, + { + .id = V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 0, + .maximum = ((1 << 16) - 1), + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES, + .type = V4L2_CTRL_TYPE_MENU, + .minimum = V4L2_CID_CODEC_VP9_1_REF_PFRAME, + .maximum = V4L2_CID_CODEC_VP9_2_REF_PFRAME, + .step = 1, + .default_value = V4L2_CID_CODEC_VP9_1_REF_PFRAME, + }, + { + .id = V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = 0, + .maximum = 2, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH, + .type = V4L2_CTRL_TYPE_MENU, + .minimum = V4L2_CID_CODEC_VP9_0_PARTITION, + .maximum = V4L2_CID_CODEC_VP9_1_PARTITION, + .step = 1, + .default_value = V4L2_CID_CODEC_VP9_0_PARTITION, + }, + { + .id = V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR, + .type = V4L2_CTRL_TYPE_INTEGER, + .minimum = INT_MIN, + .maximum = INT_MAX, + .step = 1, + .default_value = 0, + }, + { + .id = V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER, + .type = V4L2_CTRL_TYPE_BOOLEAN, + .minimum = 0, + .maximum = 1, + .step = 1, + .default_value = 0, + }, { .id = V4L2_CID_MIN_BUFFERS_FOR_OUTPUT, .type = V4L2_CTRL_TYPE_INTEGER, @@ -1791,6 +1966,36 @@ static void __enc_update_hevc_qp_ctrls_range(struct s5p_mfc_ctx *ctx, } } +/* + * Update range of all VP9 quantization parameter controls that depend on the + * V4L2_CID_CODEC_VP9_MIN_QP, V4L2_CID_CODEC_VP9_MAX_QP controls. + */ +static void __enc_update_vp9_qp_ctrls_range(struct s5p_mfc_ctx *ctx, + int min, int max) +{ + static const int __vp9_qp_ctrls[] = { + V4L2_CID_CODEC_VP9_I_FRAME_QP, + V4L2_CID_CODEC_VP9_P_FRAME_QP, + V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP, + V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP, + V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP, + }; + struct v4l2_ctrl *ctrl = NULL; + int i, j; + + for (i = 0; i < ARRAY_SIZE(__vp9_qp_ctrls); i++) { + for (j = 0; j < ARRAY_SIZE(ctx->ctrls); j++) { + if (ctx->ctrls[j]->id == __vp9_qp_ctrls[i]) { + ctrl = ctx->ctrls[j]; + break; + } + } + if (WARN_ON(!ctrl)) + break; + __v4l2_ctrl_modify_range(ctrl, min, max, ctrl->step, min); + } +} + static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl) { struct s5p_mfc_ctx *ctx = ctrl_to_ctx(ctrl); @@ -2194,6 +2399,73 @@ static int s5p_mfc_enc_s_ctrl(struct v4l2_ctrl *ctrl) case V4L2_CID_MPEG_VIDEO_PREPEND_SPSPPS_TO_IDR: p->codec.hevc.prepend_sps_pps_to_idr = ctrl->val; break; + case V4L2_CID_MPEG_VIDEO_VP9_PROFILE: + p->codec.vp9.vp9_profile = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_RC_FRAME_RATE: + p->codec.vp9.rc_framerate = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_MIN_QP: + p->codec.vp9.rc_min_qp = ctrl->val; + __enc_update_vp9_qp_ctrls_range(ctx, ctrl->val, + p->codec.vp9.rc_max_qp); + break; + case V4L2_CID_CODEC_VP9_MAX_QP: + p->codec.vp9.rc_max_qp = ctrl->val; + __enc_update_vp9_qp_ctrls_range(ctx, + p->codec.vp9.rc_min_qp, ctrl->val); + break; + case V4L2_CID_CODEC_VP9_I_FRAME_QP: + p->codec.vp9.rc_frame_qp = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_P_FRAME_QP: + p->codec.vp9.rc_p_frame_qp = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_GOLDEN_FRAMESEL: + p->codec.vp9.vp9_goldenframesel = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_GF_REFRESH_PERIOD: + p->codec.vp9.vp9_gfrefreshperiod = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIERARCHY_QP_ENABLE: + p->codec.vp9.hier_qp_enable = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIERARCHY_RC_ENABLE: + p->codec.vp9.hier_rc_enable = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L0_QP: + p->codec.vp9.hier_qp_layer[0] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L1_QP: + p->codec.vp9.hier_qp_layer[1] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L2_QP: + p->codec.vp9.hier_qp_layer[2] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L0_BR: + p->codec.vp9.hier_bit_layer[0] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L1_BR: + p->codec.vp9.hier_bit_layer[1] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIER_CODING_L2_BR: + p->codec.vp9.hier_bit_layer[2] = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_REF_NUMBER_FOR_PFRAMES: + p->codec.vp9.num_refs_for_p = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_HIERARCHICAL_CODING_LAYER: + p->codec.vp9.num_hier_layer = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_MAX_PARTITION_DEPTH: + p->codec.vp9.max_partition_depth = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_DISABLE_INTRA_PU_SPLIT: + p->codec.vp9.intra_pu_split_disable = ctrl->val; + break; + case V4L2_CID_CODEC_VP9_DISABLE_IVF_HEADER: + p->codec.vp9.ivf_header = ctrl->val; + break; default: v4l2_err(&dev->v4l2_dev, "Invalid control, id=%d, val=%d\n", ctrl->id, ctrl->val); diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h index 87ac56756a16..a005623e2daa 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr.h @@ -277,6 +277,8 @@ struct s5p_mfc_regs { void __iomem *e_hevc_lf_beta_offset_div2; /* v10 */ void __iomem *e_hevc_lf_tc_offset_div2; /* v10 */ void __iomem *e_hevc_nal_control; /* v10 */ + void __iomem *e_vp9_options; /* v12 */ + void __iomem *e_vp9_golden_frame_option; /* v12 */ }; struct s5p_mfc_hw_ops { diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c index db8ecc2740d7..048950778eee 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c @@ -365,6 +365,17 @@ static int s5p_mfc_alloc_codec_buffers_v6(struct s5p_mfc_ctx *ctx) ctx->chroma_dpb_size + ctx->me_buffer_size)); ctx->bank2.size = 0; break; + case S5P_FIMV_CODEC_VP9_ENC: + mfc_debug(2, "Use min scratch buffer size\n"); + ctx->me_buffer_size = + ALIGN(ENC_V120_VP9_ME_SIZE(lcu_width, lcu_height), 16); + ctx->scratch_buf_size = ALIGN(ctx->scratch_buf_size, 256); + ctx->bank1.size = + ctx->scratch_buf_size + ctx->tmv_buffer_size + + (ctx->pb_count * (ctx->luma_dpb_size + + ctx->chroma_dpb_size + ctx->me_buffer_size)); + ctx->bank2.size = 0; + break; default: break; } @@ -420,6 +431,7 @@ static int s5p_mfc_alloc_instance_buffer_v6(struct s5p_mfc_ctx *ctx) case S5P_MFC_CODEC_MPEG4_ENC: case S5P_MFC_CODEC_H263_ENC: case S5P_MFC_CODEC_VP8_ENC: + case S5P_FIMV_CODEC_VP9_ENC: ctx->ctx.size = buf_size->other_enc_ctx; break; default: @@ -1654,6 +1666,102 @@ static int s5p_mfc_set_enc_params_hevc(struct s5p_mfc_ctx *ctx) return 0; } +int s5p_mfc_set_enc_params_vp9(struct s5p_mfc_ctx *ctx) +{ + struct s5p_mfc_dev *dev = ctx->dev; + const struct s5p_mfc_regs *mfc_regs = dev->mfc_regs; + struct s5p_mfc_enc_params *p = &ctx->enc_params; + struct s5p_mfc_vp9_enc_params *p_vp9 = &p->codec.vp9; + unsigned int reg = 0; + int i; + + mfc_debug_enter(); + + s5p_mfc_set_enc_params(ctx); + + /* profile*/ + reg = 0; + reg |= (p_vp9->vp9_profile); + writel(reg, mfc_regs->e_picture_profile); + + reg = 0; + reg |= ((p_vp9->ivf_header & 0x1) << 12); + reg |= ((p_vp9->hier_qp_enable & 0x1) << 11); + reg |= (p_vp9->max_partition_depth & 0x1) << 3; + reg |= (p_vp9->intra_pu_split_disable & 0x1) << 1; + reg |= (p_vp9->num_refs_for_p - 1) & 0x1; + writel(reg, mfc_regs->e_vp9_options); + + reg = 0; + reg |= (p_vp9->vp9_goldenframesel & 0x1); + reg |= (p_vp9->vp9_gfrefreshperiod & 0xffff) << 1; + writel(reg, mfc_regs->e_vp9_golden_frame_option); + + reg = 0; + if (p_vp9->num_hier_layer) { + reg |= p_vp9->num_hier_layer & 0x3; + writel(reg, mfc_regs->e_num_t_layer); + /* QP value for each layer */ + if (p_vp9->hier_qp_enable) { + for (i = 0; i < (p_vp9->num_hier_layer & 0x3); i++) + writel(p_vp9->hier_qp_layer[i], + mfc_regs->e_hier_qp_layer0 + + i * 4); + } + if (p_vp9->hier_rc_enable) { + for (i = 0; i < (p_vp9->num_hier_layer & 0x3); i++) + writel(p_vp9->hier_bit_layer[i], + mfc_regs->e_hier_bit_rate_layer0 + + i * 4); + } + } + /* number of coding layer should be zero when hierarchical is disable */ + reg |= p_vp9->num_hier_layer; + writel(reg, mfc_regs->e_num_t_layer); + + /* qp */ + writel(0x0, mfc_regs->e_fixed_picture_qp); + if (!p->rc_frame && !p->rc_mb) { + reg = 0; + reg &= ~(0xff << 8); + reg |= (p_vp9->rc_p_frame_qp << 8); + reg &= ~(0xff); + reg |= p_vp9->rc_frame_qp; + writel(reg, mfc_regs->e_fixed_picture_qp); + } + + /* frame rate */ + if (p->rc_frame) { + reg = 0; + reg &= ~(0xffff << 16); + reg |= ((p_vp9->rc_framerate * FRAME_DELTA_DEFAULT) << 16); + reg &= ~(0xffff); + reg |= FRAME_DELTA_DEFAULT; + writel(reg, mfc_regs->e_rc_frame_rate); + } + + /* rate control config. */ + reg = readl(mfc_regs->e_rc_config); + /** macroblock level rate control */ + reg &= ~(0x1 << 8); + reg |= ((p->rc_mb & 0x1) << 8); + writel(reg, mfc_regs->e_rc_config); + + /* max & min value of QP */ + reg = 0; + /** max QP */ + reg &= ~(0xFF << 8); + reg |= (p_vp9->rc_max_qp << 8); + /** min QP */ + reg &= ~(0xFF); + reg |= p_vp9->rc_min_qp; + writel(reg, mfc_regs->e_rc_qp_bound); + + mfc_debug_leave(); + + return 0; +} + /* Initialize decoding */ static int s5p_mfc_init_decode_v6(struct s5p_mfc_ctx *ctx) { @@ -1775,6 +1883,8 @@ static int s5p_mfc_init_encode_v6(struct s5p_mfc_ctx *ctx) s5p_mfc_set_enc_params_vp8(ctx); else if (ctx->codec_mode == S5P_FIMV_CODEC_HEVC_ENC) s5p_mfc_set_enc_params_hevc(ctx); + else if (ctx->codec_mode == S5P_FIMV_CODEC_VP9_ENC) + s5p_mfc_set_enc_params_vp9(ctx); else { mfc_err("Unknown codec for encoding (%x).\n", ctx->codec_mode); @@ -2538,6 +2648,17 @@ const struct s5p_mfc_regs *s5p_mfc_init_regs_v6_plus(struct s5p_mfc_dev *dev) R(e_hevc_lf_tc_offset_div2, S5P_FIMV_E_HEVC_LF_TC_OFFSET_DIV2_V10); R(e_hevc_nal_control, S5P_FIMV_E_HEVC_NAL_CONTROL_V10); + if (!IS_MFCV12(dev)) + goto done; + + /* Initialize registers used in MFC v10 only. + * Also, over-write the registers which have + * a different offset for MFC v10. + */ + + R(e_vp9_options, S5P_FIMV_E_VP9_OPTION_V12); + R(e_vp9_golden_frame_option, S5P_FIMV_E_VP9_GOLDEN_FRAME_OPTION_V12); + done: return &mfc_regs; #undef S5P_MFC_REG_ADDR From patchwork Wed Sep 7 06:47:09 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smitha T Murthy X-Patchwork-Id: 603557 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6129AC54EE9 for ; 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Wed, 7 Sep 2022 06:33:48 +0000 (GMT) Received: from epsmgms1p1new.samsung.com (unknown [182.195.42.41]) by epsmtrp1.samsung.com (KnoxPortal) with ESMTP id 20220907063348epsmtrp190de2606b8f9671f6d3f4d7303682145~SgG93sh0K0507305073epsmtrp1E; Wed, 7 Sep 2022 06:33:48 +0000 (GMT) X-AuditID: b6c32a4b-e33fb7000000d32c-a4-63183c06c377 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id EC.DC.14392.C4B38136; Wed, 7 Sep 2022 15:33:48 +0900 (KST) Received: from Jaguar.sa.corp.samsungelectronics.net (unknown [107.109.115.6]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220907063344epsmtip1929229c3dfbd42a64dc308759b19a404~SgG6Vcsse2625726257epsmtip1z; Wed, 7 Sep 2022 06:33:44 +0000 (GMT) From: Smitha T Murthy To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v2 09/15] media: s5p-mfc: Add support for rate controls in MFCv12 Date: Wed, 7 Sep 2022 12:17:09 +0530 Message-Id: <20220907064715.55778-10-smitha.t@samsung.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220907064715.55778-1-smitha.t@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA0WTeVBTVxTG5+blvRdgwryJtL3FCvShreyJQLwotM5o6WuxHabMtLQzlcbk FRBIQhKqbdksBVpGcCN1QCAWsDjIIpGwFTDQuAxVpwjIaI0iS1kUEDCojV0SAu1/v3POd865 8917eZhghHDnJco1rEouSaYJZ27LLz6+AUQ4lAoX+gLQRFsJjkYqWghU9XSSg+5VLXFR73kD iZoHT2Ko5rIRRzrTdRy19oxyUdOUrdpfYuaiSV0DQNOldwmkH7uJo/szH6GBjjICHTpnwFG9 yUyi08P9HPST/jkHVRoekyi3y0Qic2cLQN/mmTg7IFNXUQeYNnM1YIarFzGmvdRMMlWd0xxG X/s9wdy52Ukw56uzmNyLf3KZouZawPz9TTnJFJiGCWZJ78H0WZbIaNdPksITWImMVXmxcqlC liiPj6CjYuJ2xoWKhaIAURjaSnvJJSlsBL1rd3RAZGKyzQba6wtJcpotFS1Rq+mgN8JVijQN 65WgUGsiaFYpS1aGKAPVkhR1mjw+UM5qtomEwi2hNuFnSQn92iOk0kgd0JuO4dlghF8AnHiQ CoF/VY9zC4AzT0D9DKD1bAXuCBYBPKm1chzBMoDdlVP4WkteewPmKHQBeKPlDGkvCKgcDmx+ EmZngvKHy/O/EnZ2ow4COPadxt6AUTlcaL5qXWlYR8XAW/88xOzMpTbB1u45YGc+tQ2O/D5G OLZ5wrPnjCsaJ1u+v/jKyvkgle8EB4tybIN4tmAXvD5xwKFfB2cuN5MOdofTh/NWOR7eW8oB DlbC8uxmjoPfhMbBMq59DEb5wMaOIEd6A9T2NaxIMMoVFlrHV+V82FaxxjSsvHpldTyEQ7OG VYMYuDz6kHQYVAjgb7nF5BHgUfr/ilMA1IKXWaU6JZ5VhyqD5ez+/25NqkjRg5Wn7hvVBkZH HgX2Ag4P9ALIw2g3vqzNTSrgyyRffsWqFHGqtGRW3QtCbf4dxdxfkCpsf0WuiROFhAlDxGJx SFiwWES/xC/2A1IBFS/RsEksq2RVa30cnpN7Nqc93byZ+/RZmf8HlmzhNaHLAn5i/ef7H+cc xBbYzNvbvV/8+EJXRNZRqRUvOHPn7a2H3ztkFfMHjGDxIjOXGr2vMXxmPPi4Nvlr3Y6qiQ/T R0XbhzZlusTGOm+5XXqKAHs2L+wiVaOe3htTO++aJyvfz3qk6I7VavH1+X1+GxcF003X5D2t sownp12U0Zf2zhsMPuV7s/YEZWfEzIWPxw75DfhHRT6riHkVznulH9upHC7KS3prt+Bdy63M Joux435GZuM+b/zEhQHnpeJPTa46z+P1+cJ3dBbNK38oX7uxwZWcqrLkL88+eD3ywSxd2Fh4 6Ycf63sa63Q1qaklRO9zj+EamqtOkIh8MZVa8i8nndPvcwQAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJIsWRmVeSWpSXmKPExsWy7bCSnK6PtUSywdKtyhZPd8xktXgwbxub xeIfz5ks7i/+zGJxaPNWdostV2YzWyw/foDVYv6Rc6wW2w8+YrHY+AIoe3HmXRaL5/PXMVq8 nHWPzWLT42usFg9fhVtc3jWHzaJnw1ZWi7VH7rJbLL1+kcli2aY/TBaLtn5ht2jde4Td4u6e bYwWLW1HmBwkPNbMW8PosePuEkaP60s+MXvsnHWX3WPxnpdMHptWdbJ53Lm2h81j85J6j9aj v1g8+rasYvT41zSX3aPryHU2j8+b5DxOff3MHsAXxWWTkpqTWZZapG+XwJVxceoE9oIDAhWb jkxibWB8wNvFyMkhIWAi0bZzHXMXIxeHkMBuRol9d56zQyQkJFb+nsQIYQtLrPwHEgcpamSS uLepDSzBJqAj8e39aTaQhIhAK6PE9ZWdTCAOs8BsFokfkw6wglQJCwRKHN+7AayDRUBVYvu+ d2A2r4CVxIPbj9kgVshLrN5wgBnE5gSKX5xyAqxXSMBS4vGMbewTGPkWMDKsYpRMLSjOTc8t NiwwzEst1ytOzC0uzUvXS87P3cQIjj0tzR2M21d90DvEyMTBeIhRgoNZSYQ3ZYdIshBvSmJl VWpRfnxRaU5q8SFGaQ4WJXHeC10n44UE0hNLUrNTUwtSi2CyTBycUg1MU9eECM7cIdA2U5l/ gUjMry9eS52SfJRepPdvWhIkIbNcYcGxyGPdOXkOmipPq+ddtd4bX97b+CvjYoVvw/9cQ+b2 d69vTGiU8/GXaDx/48t97zye3gR5F4fK/zOEH0rwrpI3P1Obutf6/0M20ct3OYytAmIPm0/O y3/1dv6Gx4s+CjXxuTMlOaVwbqno4O4QS56QeuLIr0N7aoQt9ZzmNvxdoOa8UiicM37Nbi+z SE8vifgdjBtPT+tQcHn+u7tbKOv6LmanKHGrr64OitqytZlvnz4xZes6scZp9lKBHLNX1btX 7PHP9xdaFTdd56rUjcVn4qafO9Mx+XDoOcbvW89NuThn/529R+ImhvsrsRRnJBpqMRcVJwIA AKyzyCwDAAA= X-CMS-MailID: 20220907063348epcas5p15d482a6f03f21489aedde74f93c64ae4 X-Msg-Generator: CA X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20220907063348epcas5p15d482a6f03f21489aedde74f93c64ae4 References: <20220907064715.55778-1-smitha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In MFCv12, the rc configs are changed with support for CBR loose, CBR tight and Variable Bitrate (VBR) added. Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy --- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c | 22 +++++++++++++++---- .../platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h | 1 + 2 files changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c index eecefcfc683b..c0b8434812e0 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.c @@ -1039,10 +1039,24 @@ static int s5p_mfc_set_enc_params(struct s5p_mfc_ctx *ctx) /* reaction coefficient */ if (p->rc_frame) { - if (p->rc_reaction_coeff < TIGHT_CBR_MAX) /* tight CBR */ - writel(1, mfc_regs->e_rc_mode); - else /* loose CBR */ - writel(2, mfc_regs->e_rc_mode); + if (IS_MFCV12(dev)) { + /* loose CBR */ + if (p->rc_reaction_coeff < LOOSE_CBR_MAX) + writel(1, mfc_regs->e_rc_mode); + /* tight CBR */ + else if (p->rc_reaction_coeff < TIGHT_CBR_MAX) + writel(0, mfc_regs->e_rc_mode); + /* VBR */ + else + writel(2, mfc_regs->e_rc_mode); + } else { + /* tight CBR */ + if (p->rc_reaction_coeff < TIGHT_CBR_MAX) + writel(1, mfc_regs->e_rc_mode); + /* loose CBR */ + else + writel(2, mfc_regs->e_rc_mode); + } } /* seq header ctrl */ diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h index 30269f3e68e8..24752a712fbf 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_opr_v6.h @@ -40,6 +40,7 @@ #define ENC_H264_LEVEL_MAX 42 #define ENC_MPEG4_VOP_TIME_RES_MAX ((1 << 16) - 1) #define FRAME_DELTA_H264_H263 1 +#define LOOSE_CBR_MAX 5 #define TIGHT_CBR_MAX 10 #define ENC_HEVC_RC_FRAME_RATE_MAX ((1 << 16) - 1) #define ENC_HEVC_QP_INDEX_MIN -12 From patchwork Wed Sep 7 06:47:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smitha T 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Jaguar.sa.corp.samsungelectronics.net (unknown [107.109.115.6]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20220907063352epsmtip10ceff6624ed0d28849c7b02bf8fa426c~SgHBQQTHf2639226392epsmtip1p; Wed, 7 Sep 2022 06:33:52 +0000 (GMT) From: Smitha T Murthy To: linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Cc: m.szyprowski@samsung.com, andrzej.hajda@intel.com, mchehab@kernel.org, hverkuil-cisco@xs4all.nl, ezequiel@vanguardiasur.com.ar, jernej.skrabec@gmail.com, benjamin.gaignard@collabora.com, stanimir.varbanov@linaro.org, dillon.minfei@gmail.com, david.plowman@raspberrypi.com, mark.rutland@arm.com, robh+dt@kernel.org, krzk+dt@kernel.org, andi@etezian.org, alim.akhtar@samsung.com, aswani.reddy@samsung.com, pankaj.dubey@samsung.com, linux-fsd@tesla.com, smitha.t@samsung.com, aakarsh.jain@samsung.com Subject: [Patch v2 11/15] media: s5p-mfc: Add support for DMABUF for encoder Date: Wed, 7 Sep 2022 12:17:11 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X-CMS-RootMailID: 20220907063355epcas5p4738968135cdc376beb4a8c621131e2f1 References: <20220907064715.55778-1-smitha.t@samsung.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dmabuf support for mfc encoder Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy --- .../media/platform/samsung/s5p-mfc/s5p_mfc.c | 4 ++-- .../platform/samsung/s5p-mfc/s5p_mfc_enc.c | 21 +++++++++++-------- 2 files changed, 14 insertions(+), 11 deletions(-) diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c index c483a95d5e92..2987f8984553 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc.c @@ -850,7 +850,7 @@ static int s5p_mfc_open(struct file *file) q->io_modes = VB2_MMAP; q->ops = get_dec_queue_ops(); } else if (vdev == dev->vfd_enc) { - q->io_modes = VB2_MMAP | VB2_USERPTR; + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; q->ops = get_enc_queue_ops(); } else { ret = -ENOENT; @@ -877,7 +877,7 @@ static int s5p_mfc_open(struct file *file) q->io_modes = VB2_MMAP; q->ops = get_dec_queue_ops(); } else if (vdev == dev->vfd_enc) { - q->io_modes = VB2_MMAP | VB2_USERPTR; + q->io_modes = VB2_MMAP | VB2_USERPTR | VB2_DMABUF; q->ops = get_enc_queue_ops(); } else { ret = -ENOENT; diff --git a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c index 119e55c6f759..404bce3641b9 100644 --- a/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c +++ b/drivers/media/platform/samsung/s5p-mfc/s5p_mfc_enc.c @@ -1704,9 +1704,10 @@ static int vidioc_reqbufs(struct file *file, void *priv, struct s5p_mfc_ctx *ctx = fh_to_ctx(priv); int ret = 0; - /* if memory is not mmp or userptr return error */ + /* if memory is not mmp or userptr or dmabuf return error */ if ((reqbufs->memory != V4L2_MEMORY_MMAP) && - (reqbufs->memory != V4L2_MEMORY_USERPTR)) + (reqbufs->memory != V4L2_MEMORY_USERPTR) && + (reqbufs->memory != V4L2_MEMORY_DMABUF)) return -EINVAL; if (reqbufs->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { if (reqbufs->count == 0) { @@ -1783,9 +1784,10 @@ static int vidioc_querybuf(struct file *file, void *priv, struct s5p_mfc_ctx *ctx = fh_to_ctx(priv); int ret = 0; - /* if memory is not mmp or userptr return error */ + /* if memory is not mmp or userptr or dmabuf return error */ if ((buf->memory != V4L2_MEMORY_MMAP) && - (buf->memory != V4L2_MEMORY_USERPTR)) + (buf->memory != V4L2_MEMORY_USERPTR) && + (buf->memory != V4L2_MEMORY_DMABUF)) return -EINVAL; if (buf->type == V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE) { if (ctx->state != MFCINST_GOT_INST) { @@ -2841,11 +2843,12 @@ static int s5p_mfc_start_streaming(struct vb2_queue *q, unsigned int count) S5P_MFC_R2H_CMD_SEQ_DONE_RET, 0); } - - if (ctx->src_bufs_cnt < ctx->pb_count) { - mfc_err("Need minimum %d OUTPUT buffers\n", - ctx->pb_count); - return -ENOBUFS; + if (q->memory != V4L2_MEMORY_DMABUF) { + if (ctx->src_bufs_cnt < ctx->pb_count) { + mfc_err("Need minimum %d OUTPUT buffers\n", + ctx->pb_count); + return -ENOBUFS; + } } } From patchwork Wed Sep 7 06:47:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Smitha T Murthy X-Patchwork-Id: 603555 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D16EEC6FA86 for ; Wed, 7 Sep 2022 06:38:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230081AbiIGGio (ORCPT ); Wed, 7 Sep 2022 02:38:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230098AbiIGGil (ORCPT ); Wed, 7 Sep 2022 02:38:41 -0400 Received: from mailout3.samsung.com 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Cc: linux-fsd@tesla.com Signed-off-by: Smitha T Murthy --- arch/arm64/boot/dts/tesla/fsd-evb.dts | 4 ++++ arch/arm64/boot/dts/tesla/fsd.dtsi | 22 ++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/tesla/fsd-evb.dts b/arch/arm64/boot/dts/tesla/fsd-evb.dts index 1db6ddf03f01..17bb048f9d47 100644 --- a/arch/arm64/boot/dts/tesla/fsd-evb.dts +++ b/arch/arm64/boot/dts/tesla/fsd-evb.dts @@ -30,6 +30,10 @@ }; }; +&clock_mfc { + status = "okay"; +}; + &fin_pll { clock-frequency = <24000000>; }; diff --git a/arch/arm64/boot/dts/tesla/fsd.dtsi b/arch/arm64/boot/dts/tesla/fsd.dtsi index f35bc5a288c2..bca0ba030ee7 100644 --- a/arch/arm64/boot/dts/tesla/fsd.dtsi +++ b/arch/arm64/boot/dts/tesla/fsd.dtsi @@ -340,6 +340,18 @@ #clock-cells = <0>; }; + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + mfc_left: region@84000000 { + compatible = "shared-dma-pool"; + no-map; + reg = <0 0x84000000 0 0x8000000>; + }; + }; + soc: soc@0 { compatible = "simple-bus"; #address-cells = <2>; @@ -832,6 +844,16 @@ clock-names = "fin_pll", "mct"; }; + mfc: mfc@12880000 { + compatible = "samsung,fsd-mfc"; + reg = <0x0 0x12880000 0x0 0x10000>; + interrupts = ; + clock-names = "mfc"; + clocks = <&clock_mfc MFC_MFC_IPCLKPORT_ACLK>; + memory-region = <&mfc_left>; + status = "okay"; + }; + ufs: ufs@15120000 { compatible = "tesla,fsd-ufs"; reg = <0x0 0x15120000 0x0 0x200>, /* 0: HCI standard */