From patchwork Tue Sep 6 19:04:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: matthew.gerlach@linux.intel.com X-Patchwork-Id: 603301 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9C91ECAAA1 for ; Tue, 6 Sep 2022 19:04:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229490AbiIFTEc (ORCPT ); Tue, 6 Sep 2022 15:04:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50820 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229720AbiIFTEZ (ORCPT ); Tue, 6 Sep 2022 15:04:25 -0400 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BB0B6443; Tue, 6 Sep 2022 12:04:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1662491061; x=1694027061; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=xz+4geY51LylIndKYTx2HwbrKO8DoCD/2r2Fypr/EGY=; b=GkoMcGc3n84Xr/D8llj8YCjn9zroURYcuyqtsGLGPnksGhDS+bbomih/ z/LlrbDVw5Tf1imFlDWbS/XlKDov3bP/+uyMskmucOMATKtrwz5CTJHuS zsn8VBwNhq25EmEVBD7JW+CMYh0qvvQvDVvwqbGpTPolAK/pI/8UP+s0X xO6atkeWAuXA9O5ybd/5rfnL9RdBpeDIszeFY+4CQohUqKxRc/2M/Nc5F G+jLDUMHmNLpVxE/IjCSZGiMHSf/KhvUKym0rhzMg5ATTvPujfIjTXJzh iw+zDTHnEH8zWlCMgi57ePUndGxq6+SY+TZBtPkz2L5LkB+fhuf/FAP74 g==; X-IronPort-AV: E=McAfee;i="6500,9779,10462"; a="283677336" X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="283677336" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2022 12:04:18 -0700 X-IronPort-AV: E=Sophos;i="5.93,294,1654585200"; d="scan'208";a="789782545" Received: from rhweight-wrk1.ra.intel.com ([137.102.106.43]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Sep 2022 12:04:18 -0700 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de Cc: Basheer Ahmed Muddebihal , Matthew Gerlach Subject: [PATCH v1 2/5] fpga: dfl: Move the DFH definitions Date: Tue, 6 Sep 2022 12:04:23 -0700 Message-Id: <20220906190426.3139760-3-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906190426.3139760-1-matthew.gerlach@linux.intel.com> References: <20220906190426.3139760-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Basheer Ahmed Muddebihal Moving the DFH register offset and register definitions from drivers/fpga/dfl.h to include/linux/dfl.h. These definitions need to be accessed by dfl drivers that are outside of drivers/fpga. Signed-off-by: Basheer Ahmed Muddebihal Signed-off-by: Matthew Gerlach --- drivers/fpga/dfl.h | 22 ++-------------------- include/linux/dfl.h | 23 ++++++++++++++++++++++- 2 files changed, 24 insertions(+), 21 deletions(-) diff --git a/drivers/fpga/dfl.h b/drivers/fpga/dfl.h index 06cfcd5e84bb..d4dfc03a0b61 100644 --- a/drivers/fpga/dfl.h +++ b/drivers/fpga/dfl.h @@ -2,7 +2,7 @@ /* * Driver Header File for FPGA Device Feature List (DFL) Support * - * Copyright (C) 2017-2018 Intel Corporation, Inc. + * Copyright (C) 2017-2022 Intel Corporation, Inc. * * Authors: * Kang Luwei @@ -17,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -53,28 +54,9 @@ #define PORT_FEATURE_ID_UINT 0x12 #define PORT_FEATURE_ID_STP 0x13 -/* - * Device Feature Header Register Set - * - * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. - * For AFUs, they have DFH + GUID as common header registers. - * For private features, they only have DFH register as common header. - */ -#define DFH 0x0 -#define GUID_L 0x8 -#define GUID_H 0x10 -#define NEXT_AFU 0x18 - -#define DFH_SIZE 0x8 - /* Device Feature Header Register Bitfield */ -#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ #define DFH_ID_FIU_FME 0 #define DFH_ID_FIU_PORT 1 -#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ -#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ -#define DFH_EOL BIT_ULL(40) /* End of list */ -#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ #define DFH_TYPE_AFU 1 #define DFH_TYPE_PRIVATE 3 #define DFH_TYPE_FIU 4 diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 431636a0dc78..b5accdcfa368 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -2,7 +2,7 @@ /* * Header file for DFL driver and device API * - * Copyright (C) 2020 Intel Corporation, Inc. + * Copyright (C) 2020-2022 Intel Corporation, Inc. */ #ifndef __LINUX_DFL_H @@ -11,6 +11,27 @@ #include #include +/* + * Device Feature Header Register Set + * + * For FIUs, they all have DFH + GUID + NEXT_AFU as common header registers. + * For AFUs, they have DFH + GUID as common header registers. + * For private features, they only have DFH register as common header. + */ +#define DFH 0x0 +#define GUID_L 0x8 +#define GUID_H 0x10 +#define NEXT_AFU 0x18 + +#define DFH_SIZE 0x8 + +/* Device Feature Header Register Bitfield */ +#define DFH_ID GENMASK_ULL(11, 0) /* Feature ID */ +#define DFH_REVISION GENMASK_ULL(15, 12) /* Feature revision */ +#define DFH_NEXT_HDR_OFST GENMASK_ULL(39, 16) /* Offset to next DFH */ +#define DFH_EOL BIT_ULL(40) /* End of list */ +#define DFH_TYPE GENMASK_ULL(63, 60) /* Feature type */ + /** * enum dfl_id_type - define the DFL FIU types */ From patchwork Tue Sep 6 19:04:25 2022 Content-Type: text/plain; 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06 Sep 2022 12:04:18 -0700 From: matthew.gerlach@linux.intel.com To: hao.wu@intel.com, yilun.xu@intel.com, russell.h.weight@intel.com, basheer.ahmed.muddebihal@intel.com, trix@redhat.com, mdf@kernel.org, linux-fpga@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, tianfei.zhang@intel.com, corbet@lwn.net, gregkh@linuxfoundation.org, linux-serial@vger.kernel.org, jirislaby@kernel.org, geert+renesas@glider.be, andriy.shevchenko@linux.intel.com, niklas.soderlund+renesas@ragnatech.se, phil.edworthy@renesas.com, macro@orcam.me.uk, johan@kernel.org, lukas@wunner.de Cc: Matthew Gerlach Subject: [PATCH v1 4/5] fpga: dfl: add generic support for MSIX interrupts Date: Tue, 6 Sep 2022 12:04:25 -0700 Message-Id: <20220906190426.3139760-5-matthew.gerlach@linux.intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220906190426.3139760-1-matthew.gerlach@linux.intel.com> References: <20220906190426.3139760-1-matthew.gerlach@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Matthew Gerlach Define and use a DFHv1 parameter to add generic support for MSIX interrupts for DFL devices. Signed-off-by: Matthew Gerlach --- drivers/fpga/dfl.c | 59 +++++++++++++++++++++++++++++++++------------ include/linux/dfl.h | 13 ++++++++++ 2 files changed, 57 insertions(+), 15 deletions(-) diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index b9aae85ba930..17f704dc8483 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -941,25 +941,11 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, void __iomem *base = binfo->ioaddr + ofst; unsigned int i, ibase, inr = 0; enum dfl_id_type type; - int virq; + int virq, off; u64 v; type = feature_dev_id_type(binfo->feature_dev); - /* - * Ideally DFL framework should only read info from DFL header, but - * current version DFL only provides mmio resources information for - * each feature in DFL Header, no field for interrupt resources. - * Interrupt resource information is provided by specific mmio - * registers of each private feature which supports interrupt. So in - * order to parse and assign irq resources, DFL framework has to look - * into specific capability registers of these private features. - * - * Once future DFL version supports generic interrupt resource - * information in common DFL headers, the generic interrupt parsing - * code will be added. But in order to be compatible to old version - * DFL, the driver may still fall back to these quirks. - */ if (type == PORT_ID) { switch (fid) { case PORT_FEATURE_ID_UINT: @@ -981,6 +967,28 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, } } + if (fid != FEATURE_ID_AFU && fid != PORT_FEATURE_ID_ERROR && + fid != PORT_FEATURE_ID_UINT && fid != FME_FEATURE_ID_GLOBAL_ERR) { + v = readq(base); + v = FIELD_GET(DFH_VERSION, v); + + if (v == 1) { + v = readq(base + DFHv1_CSR_SIZE_GRP); + if (FIELD_GET(DFHv1_CSR_SIZE_GRP_HAS_PARAMS, v)) { + off = dfl_find_param(base + DFHv1_PARAM_HDR, ofst, + DFHv1_PARAM_ID_MSIX); + if (off >= 0) { + ibase = readl(base + DFHv1_PARAM_HDR + + off + DFHv1_PARAM_MSIX_STARTV); + inr = readl(base + DFHv1_PARAM_HDR + + off + DFHv1_PARAM_MSIX_NUMV); + dev_dbg(binfo->dev, "%s start %d num %d fid 0x%x\n", + __func__, ibase, inr, fid); + } + } + } + } + if (!inr) { *irq_base = 0; *nr_irqs = 0; @@ -1879,6 +1887,27 @@ long dfl_feature_ioctl_set_irq(struct platform_device *pdev, } EXPORT_SYMBOL_GPL(dfl_feature_ioctl_set_irq); +int dfl_find_param(void __iomem *base, resource_size_t max, int param) +{ + int off = 0; + u64 v, next; + + while (off < max) { + v = readq(base + off); + if (param == FIELD_GET(DFHv1_PARAM_HDR_ID, v)) + return off; + + next = FIELD_GET(DFHv1_PARAM_HDR_NEXT_OFFSET, v); + if (!next) + break; + + off += next; + } + + return -ENOENT; +} +EXPORT_SYMBOL_GPL(dfl_find_param); + static void __exit dfl_fpga_exit(void) { dfl_chardev_uinit(); diff --git a/include/linux/dfl.h b/include/linux/dfl.h index 61bcf20c1bc8..5652879ab48e 100644 --- a/include/linux/dfl.h +++ b/include/linux/dfl.h @@ -69,6 +69,10 @@ #define DFHv1_PARAM_HDR_VERSION GENMASK_ULL(31, 16) /* Version Param */ #define DFHv1_PARAM_HDR_NEXT_OFFSET GENMASK_ULL(63, 32) /* Offset of next Param */ +#define DFHv1_PARAM_ID_MSIX 0x1 +#define DFHv1_PARAM_MSIX_STARTV 0x8 +#define DFHv1_PARAM_MSIX_NUMV 0xc + /** * enum dfl_id_type - define the DFL FIU types */ @@ -142,4 +146,13 @@ void dfl_driver_unregister(struct dfl_driver *dfl_drv); module_driver(__dfl_driver, dfl_driver_register, \ dfl_driver_unregister) +/* + * dfl_find_param() - find the offset of the given parameter + * @base: base pointer to start of dfl parameters in DFH + * @max: maximum offset to search + * @param: id of dfl parameter + * + * Return: positive offset on success, negative error code otherwise. + */ +int dfl_find_param(void __iomem *base, resource_size_t max, int param); #endif /* __LINUX_DFL_H */