From patchwork Tue Sep 6 17:22:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 603042 Delivered-To: patch@linaro.org Received: by 2002:a05:6504:2213:b0:1da:4c02:b5e7 with SMTP id z19csp3232568ltw; Tue, 6 Sep 2022 10:23:55 -0700 (PDT) X-Google-Smtp-Source: AA6agR4R1L0GRRzxVgaLDX082yubF2cyDvvTr5pbGykCQ+ERTa8Wdbh4FwCwsJnjuR4Dfm977bEM X-Received: by 2002:a05:620a:4549:b0:6bb:bcd5:bebd with SMTP id u9-20020a05620a454900b006bbbcd5bebdmr36272385qkp.281.1662485035418; Tue, 06 Sep 2022 10:23:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662485035; cv=none; d=google.com; s=arc-20160816; b=bSTGARwijphRd/Ohv8zRveH4NtArrbCu2OjSqnC7sVdiTmoRp1tJ3LA+HLE6frSiPs b6HLkJOWoWQ7pAyCHgK8GC/AFQWJWX7RMqetMgA0pHCDiDUs2GtuXgkBq90JJEhDFvzi qLRtpMLMS7f62gWqNWqtSEXHp8fEDh97rcIlYPFQ0AI0Trzt/qmPBroVlbeOsYq405Xh li0HKCKG5k2TBrKgFLqAvUm/7NeiSK47I9q9aG2+6uK5OCmlDSx/KD7OQVEaNz1upD0V BtzcZa+l555DBv3agRHofACEAp+Sm0U4Xo+Av5T7DW5efJVVJkLkvzaFdG0ldojE6HLw 7yUg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature; bh=WDkpvIkbzjHzfAeFRpYWMbLOj1xKc5WDtqfzvZ/DNrY=; b=Z2wLckBcW9sanVWft5EB09/ZlsvQTByoWY4+pbdMjYCtlDgUf0BdDPL2/EMJ+RCRMa XNDFFfWR4i+WdqpZTy66r9LAZZ2SMwMVRyxlEubf2RsjMlbRbTzEbweaKCCz4nKFvGPd VkjHNdVB8SSfZg4INzZK1xxGo0OM0t3KdXbhoDOFboXD45GdkYfXeUM5tuiLOWfjWRy7 LU5VSHfEktcwF/CkMVgw7k1j/RTg0K78HX9bqTC7FLWicYel+KI73sWW2N9fXXvlNee5 5Z/tG2+8s/SBKvJ7UqbCACJo07wM6Wtrjm7hIpuO1jDSiSNB9sb79QbRn+2FcwudHb8g SmRQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R6cM4RWK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h5-20020a05620a400500b006bb66b325adsi8380595qko.618.2022.09.06.10.23.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Sep 2022 10:23:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=R6cM4RWK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:40288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVcIk-0002ad-SY for patch@linaro.org; Tue, 06 Sep 2022 13:23:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51446) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVcI8-0002ZK-Lw for qemu-devel@nongnu.org; Tue, 06 Sep 2022 13:23:16 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:42647) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oVcI7-0002Zd-1v for qemu-devel@nongnu.org; Tue, 06 Sep 2022 13:23:16 -0400 Received: by mail-wr1-x429.google.com with SMTP id bp20so16009583wrb.9 for ; Tue, 06 Sep 2022 10:23:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date; bh=WDkpvIkbzjHzfAeFRpYWMbLOj1xKc5WDtqfzvZ/DNrY=; b=R6cM4RWKU1ITlzs8h5nxoNJ5Jq+Tp7e7wFYGHkjCS73aR0FcIpPAQrxmSGJALAoqh8 NLz3+Y8zNaHVVi85uuxPckVEDQY/Sy37GKM3qoS3PqR2cmMyzCyq4pHLFr1Q8WnGjLJg IT5UQ6+1U5SXOOf81Iehj7TdfSUjp+P1UbWvo5lXZVlivitlMrOcG7YIEtWUkB+2n5Bc pYgFGVYd7CpE2UVubp5SYZB1lSKKd5ww57j+CSggapjz4UPh7ZfSKA/QUnDmID0VizkY fF3+OhX12wiaD3nDCtEC7PkUtTp8Lp6xDDuyXhfE0//JU8IZyyZ1TfDJq2KJLKxHhMKy 9NAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date; bh=WDkpvIkbzjHzfAeFRpYWMbLOj1xKc5WDtqfzvZ/DNrY=; b=mt7tgjMNuDnxQ+nioYO+xsBEnS2ZCSowrkUrhkerQ3Jdpc2/7+v+OUg9t+cm0ly4RG ouVyMzV2LjbHD+PHYxkGBd8flLtLy57yR8Cwrk9OA+i7U/SlheOibEj9OnY2WD6H2Imn p8zKaV+E8GzQdBTzMuatXYyAjouCiSsN87LOQXJ7X5YNzCHJp54zjBiHFMCfZObgotrj bzNRtjValilccmLWSHdPaVWjUJ4Tb+0pAuiXYl0btWNCPuvRH17y2VZtUanWUzF0rEmt Qzh6PpkcRLfH7KBZzVgBNSsQqa2aqZ3YQ/BTkGpQ2fw5+k5pTnZwL+d3Wqokvn7XzZ3+ 86Hw== X-Gm-Message-State: ACgBeo37/3QWh89iYNEbVlqg+8/ZwjM+XGu0fXTabgZF9uNLKomzh2ed ntSGUJaz3k1yy52eqisScreDJw== X-Received: by 2002:a5d:6987:0:b0:228:623e:2dc5 with SMTP id g7-20020a5d6987000000b00228623e2dc5mr9142379wru.574.1662484992847; Tue, 06 Sep 2022 10:23:12 -0700 (PDT) Received: from zen.linaroharston ([185.81.254.11]) by smtp.gmail.com with ESMTPSA id n6-20020a05600c4f8600b003a54d610e5fsm23435275wmq.26.2022.09.06.10.23.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 10:23:12 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 89C7F1FFB7; Tue, 6 Sep 2022 18:23:11 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: =?utf-8?q?Alex_Benn=C3=A9e?= , Arnd Bergmann , Anders Roxell , Peter Maydell , qemu-arm@nongnu.org (open list:ARM TCG CPUs) Subject: [RFC PATCH] target/arm: update the cortex-a15 MIDR to latest rev Date: Tue, 6 Sep 2022 18:22:57 +0100 Message-Id: <20220906172257.2776521-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.34.1 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=alex.bennee@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" QEMU doesn't model micro-architectural details which includes most chip errata. The ARM_ERRATA_798181 work around in the Linux kernel (see erratum_a15_798181_init) currently detects QEMU's cortex-a15 as broken and triggers additional expensive TLB flushes as a result. Change the MIDR to report what the latest silicon would (r4p0) as well as setting the IMPDEF revidr bit to indicate these flushes are not needed. This cuts about 5s from my Debian kernel boot with the latest 6.0rc1 kernel (29s->24s). Signed-off-by: Alex Bennée Cc: Arnd Bergmann Cc: Anders Roxell Reviewed-by: Philippe Mathieu-Daudé Tested-by: Anders Roxell --- target/arm/cpu_tcg.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 3099b38e32..59d5278868 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -588,7 +588,9 @@ static void cortex_a15_initfn(Object *obj) set_feature(&cpu->env, ARM_FEATURE_EL3); set_feature(&cpu->env, ARM_FEATURE_PMU); cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15; - cpu->midr = 0x412fc0f1; + /* r4p0 cpu, not requiring expensive tlb flush errata */ + cpu->midr = 0x414fc0f0; + cpu->revidr = 0x200; cpu->reset_fpsid = 0x410430f0; cpu->isar.mvfr0 = 0x10110222; cpu->isar.mvfr1 = 0x11111111;