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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 114 +++++++++++++++++++----------------- 1 file changed, 60 insertions(+), 54 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index d6420df31d..1e24bb2985 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -76,7 +76,6 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; /* pc = eip + cs_base */ - target_ulong pc_start; /* pc at TB entry */ target_ulong cs_base; /* base of CS segment */ MemOp aflag; @@ -1345,13 +1344,13 @@ static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) the instruction is known, but it isn't allowed in the current cpu mode. */ static void gen_illegal_opcode(DisasContext *s) { - gen_exception(s, EXCP06_ILLOP, s->pc_start - s->cs_base); + gen_exception(s, EXCP06_ILLOP, s->base.pc_next - s->cs_base); } /* Generate #GP for the current instruction. */ static void gen_exception_gpf(DisasContext *s) { - gen_exception(s, EXCP0D_GPF, s->pc_start - s->cs_base); + gen_exception(s, EXCP0D_GPF, s->base.pc_next - s->cs_base); } /* Check for cpl == 0; if not, raise #GP and return false. */ @@ -2016,7 +2015,7 @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes) } s->pc += num_bytes; - if (unlikely(s->pc - s->pc_start > X86_MAX_INSN_LENGTH)) { + if (unlikely(s->pc - s->base.pc_next > X86_MAX_INSN_LENGTH)) { /* If the instruction's 16th byte is on a different page than the 1st, a * page fault on the second page wins over the general protection fault * caused by the instruction being too long. @@ -2589,7 +2588,7 @@ static void gen_unknown_opcode(CPUX86State *env, DisasContext *s) if (qemu_loglevel_mask(LOG_UNIMP)) { FILE *logfile = qemu_log_trylock(); if (logfile) { - target_ulong pc = s->pc_start, end = s->pc; + target_ulong pc = s->base.pc_next, end = s->pc; fprintf(logfile, "ILLOPC: " TARGET_FMT_lx ":", pc); for (; pc < end; ++pc) { @@ -3199,8 +3198,7 @@ static const struct SSEOpHelper_table7 sse_op_table7[256] = { goto illegal_op; \ } while (0) -static void gen_sse(CPUX86State *env, DisasContext *s, int b, - target_ulong pc_start) +static void gen_sse(CPUX86State *env, DisasContext *s, int b) { int b1, op1_offset, op2_offset, is_xmm, val; int modrm, mod, rm, reg; @@ -3242,7 +3240,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, } /* simple MMX/SSE operation */ if (s->flags & HF_TS_MASK) { - gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); + gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); return; } if (s->flags & HF_EM_MASK) { @@ -4675,11 +4673,10 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) MemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; target_ulong next_eip, tval; - target_ulong pc_start = s->base.pc_next; bool orig_cc_op_dirty = s->cc_op_dirty; CCOp orig_cc_op = s->cc_op; - s->pc_start = s->pc = pc_start; + s->pc = s->base.pc_next; s->override = -1; #ifdef TARGET_X86_64 s->rex_w = false; @@ -4703,7 +4700,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) s->base.num_insns--; tcg_remove_ops_after(s->prev_insn_end); s->base.is_jmp = DISAS_TOO_MANY; - return pc_start; + return s->base.pc_next; default: g_assert_not_reached(); } @@ -6044,7 +6041,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { /* if CR0.EM or CR0.TS are set, generate an FPU exception */ /* XXX: what to do if illegal op ? */ - gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); + gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); break; } modrm = x86_ldub_code(env, s); @@ -6585,7 +6582,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) offsetof(CPUX86State, segs[R_CS].selector)); tcg_gen_st16_i32(s->tmp2_i32, cpu_env, offsetof(CPUX86State, fpcs)); - tcg_gen_st_tl(tcg_constant_tl(pc_start - s->cs_base), + tcg_gen_st_tl(tcg_constant_tl(s->base.pc_next - s->cs_base), cpu_env, offsetof(CPUX86State, fpip)); } } @@ -6597,7 +6594,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xa5: ot = mo_b_d(b, dflag); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { - gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); + gen_repz_movs(s, ot, s->base.pc_next - s->cs_base, + s->pc - s->cs_base); } else { gen_movs(s, ot); } @@ -6607,7 +6605,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xab: ot = mo_b_d(b, dflag); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { - gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); + gen_repz_stos(s, ot, s->base.pc_next - s->cs_base, + s->pc - s->cs_base); } else { gen_stos(s, ot); } @@ -6616,7 +6615,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xad: ot = mo_b_d(b, dflag); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { - gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); + gen_repz_lods(s, ot, s->base.pc_next - s->cs_base, + s->pc - s->cs_base); } else { gen_lods(s, ot); } @@ -6625,9 +6625,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xaf: ot = mo_b_d(b, dflag); if (prefixes & PREFIX_REPNZ) { - gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); + gen_repz_scas(s, ot, s->base.pc_next - s->cs_base, + s->pc - s->cs_base, 1); } else if (prefixes & PREFIX_REPZ) { - gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); + gen_repz_scas(s, ot, s->base.pc_next - s->cs_base, + s->pc - s->cs_base, 0); } else { gen_scas(s, ot); } @@ -6637,9 +6639,11 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0xa7: ot = mo_b_d(b, dflag); if (prefixes & PREFIX_REPNZ) { - gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1); + gen_repz_cmps(s, ot, s->base.pc_next - s->cs_base, + s->pc - s->cs_base, 1); } else if (prefixes & PREFIX_REPZ) { - gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0); + gen_repz_cmps(s, ot, s->base.pc_next - s->cs_base, + s->pc - s->cs_base, 0); } else { gen_cmps(s, ot); } @@ -6657,7 +6661,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_io_start(); } if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { - gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); + gen_repz_ins(s, ot, s->base.pc_next - s->cs_base, + s->pc - s->cs_base); /* jump generated by gen_repz_ins */ } else { gen_ins(s, ot); @@ -6678,7 +6683,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) gen_io_start(); } if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { - gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base); + gen_repz_outs(s, ot, s->base.pc_next - s->cs_base, + s->pc - s->cs_base); /* jump generated by gen_repz_outs */ } else { gen_outs(s, ot); @@ -6790,7 +6796,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) do_lret: if (PE(s) && !VM86(s)) { gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1), tcg_const_i32(val)); } else { @@ -7260,7 +7266,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; val = x86_ldub_code(env, s); if (val == 0) { - gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base); + gen_exception(s, EXCP00_DIVZ, s->base.pc_next - s->cs_base); } else { gen_helper_aam(cpu_env, tcg_const_i32(val)); set_cc_op(s, CC_OP_LOGICB); @@ -7286,34 +7292,34 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) } if (prefixes & PREFIX_REPZ) { gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_pause(cpu_env, tcg_const_i32(s->pc - pc_start)); + gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_helper_pause(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); s->base.is_jmp = DISAS_NORETURN; } break; case 0x9b: /* fwait */ if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == (HF_MP_MASK | HF_TS_MASK)) { - gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); + gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); } else { gen_helper_fwait(cpu_env); } break; case 0xcc: /* int3 */ - gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base); + gen_interrupt(s, EXCP03_INT3, s->base.pc_next - s->cs_base, s->pc - s->cs_base); break; case 0xcd: /* int N */ val = x86_ldub_code(env, s); if (check_vm86_iopl(s)) { - gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base); + gen_interrupt(s, val, s->base.pc_next - s->cs_base, s->pc - s->cs_base); } break; case 0xce: /* into */ if (CODE64(s)) goto illegal_op; gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start)); + gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_helper_into(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); break; #ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ @@ -7419,7 +7425,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x132: /* rdmsr */ if (check_cpl0(s)) { gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); if (b & 2) { gen_helper_rdmsr(cpu_env); } else { @@ -7431,7 +7437,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x131: /* rdtsc */ gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -7442,7 +7448,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; case 0x133: /* rdpmc */ gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_rdpmc(cpu_env); s->base.is_jmp = DISAS_NORETURN; break; @@ -7472,8 +7478,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x105: /* syscall */ /* XXX: is it usable in real mode ? */ gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start)); + gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); /* TF handling for the syscall insn is different. The TF bit is checked after the syscall insn completes. This allows #DB to not be generated after one has entered CPL0 if TF is set in FMASK. */ @@ -7498,14 +7504,14 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) #endif case 0x1a2: /* cpuid */ gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_cpuid(cpu_env); break; case 0xf4: /* hlt */ if (check_cpl0(s)) { gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start)); + gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); s->base.is_jmp = DISAS_NORETURN; } break; @@ -7601,7 +7607,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); tcg_gen_mov_tl(s->A0, cpu_regs[R_EAX]); gen_extu(s->aflag, s->A0); gen_add_A0_ds_seg(s); @@ -7613,8 +7619,8 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); - gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start)); + gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); s->base.is_jmp = DISAS_NORETURN; break; @@ -7691,9 +7697,9 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; } gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), - tcg_const_i32(s->pc - pc_start)); + tcg_const_i32(s->pc - s->base.pc_next)); tcg_gen_exit_tb(NULL, 0); s->base.is_jmp = DISAS_NORETURN; break; @@ -7703,7 +7709,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_vmmcall(cpu_env); break; @@ -7715,7 +7721,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; } gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1)); break; @@ -7727,7 +7733,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; } gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1)); break; @@ -7753,7 +7759,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) break; } gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_clgi(cpu_env); break; @@ -7899,7 +7905,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_jmp_im(s, pc_start - s->cs_base); + gen_jmp_im(s, s->base.pc_next - s->cs_base); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -8351,7 +8357,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { - gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); + gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); break; } gen_lea_modrm(env, s, modrm); @@ -8364,7 +8370,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { - gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); + gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); break; } gen_lea_modrm(env, s, modrm); @@ -8376,7 +8382,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->flags & HF_TS_MASK) { - gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); + gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); break; } gen_lea_modrm(env, s, modrm); @@ -8389,7 +8395,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->flags & HF_TS_MASK) { - gen_exception(s, EXCP07_PREX, pc_start - s->cs_base); + gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); break; } gen_helper_update_mxcsr(cpu_env); @@ -8598,7 +8604,7 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) case 0x1c2: case 0x1c4 ... 0x1c6: case 0x1d0 ... 0x1fe: - gen_sse(env, s, b, pc_start); + gen_sse(env, s, b); break; default: goto unknown_op; From patchwork Tue Sep 6 10:09:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603008 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4424333mae; Tue, 6 Sep 2022 04:09:30 -0700 (PDT) X-Google-Smtp-Source: AA6agR72i/tHCoSwGhFKxiFZ+4i5Mb6PGxmLVpHwiw7b5I+GzTYQQgIp8fVshefH/NwO8nSALA3t X-Received: by 2002:ac8:59cf:0:b0:344:5626:6d54 with SMTP id f15-20020ac859cf000000b0034456266d54mr42358763qtf.636.1662462570589; Tue, 06 Sep 2022 04:09:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662462570; cv=none; d=google.com; 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This is false when we detect a page crossing and must undo the insn under translation. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/i386/tcg/translate.c | 42 +++++++++++++++++++------------------ 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 1e24bb2985..46300ffd91 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -4665,7 +4665,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b) /* convert one instruction. s->base.is_jmp is set if the translation must be stopped. Return the next pc value */ -static target_ulong disas_insn(DisasContext *s, CPUState *cpu) +static bool disas_insn(DisasContext *s, CPUState *cpu) { CPUX86State *env = cpu->env_ptr; int b, prefixes; @@ -4695,12 +4695,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) return s->pc; case 2: /* Restore state that may affect the next instruction. */ + s->pc = s->base.pc_next; s->cc_op_dirty = orig_cc_op_dirty; s->cc_op = orig_cc_op; s->base.num_insns--; tcg_remove_ops_after(s->prev_insn_end); s->base.is_jmp = DISAS_TOO_MANY; - return s->base.pc_next; + return false; default: g_assert_not_reached(); } @@ -8609,13 +8610,13 @@ static target_ulong disas_insn(DisasContext *s, CPUState *cpu) default: goto unknown_op; } - return s->pc; + return true; illegal_op: gen_illegal_opcode(s); - return s->pc; + return true; unknown_op: gen_unknown_opcode(env, s); - return s->pc; + return true; } void tcg_x86_init(void) @@ -8780,7 +8781,6 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); - target_ulong pc_next; #ifdef TARGET_VSYSCALL_PAGE /* @@ -8793,21 +8793,23 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } #endif - pc_next = disas_insn(dc, cpu); - dc->base.pc_next = pc_next; + if (disas_insn(dc, cpu)) { + target_ulong pc_next = dc->pc; + dc->base.pc_next = pc_next; - if (dc->base.is_jmp == DISAS_NEXT) { - if (dc->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)) { - /* - * If single step mode, we generate only one instruction and - * generate an exception. - * If irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear - * the flag and abort the translation to give the irqs a - * chance to happen. - */ - dc->base.is_jmp = DISAS_TOO_MANY; - } else if (!is_same_page(&dc->base, pc_next)) { - dc->base.is_jmp = DISAS_TOO_MANY; + if (dc->base.is_jmp == DISAS_NEXT) { + if (dc->flags & (HF_TF_MASK | HF_INHIBIT_IRQ_MASK)) { + /* + * If single step mode, we generate only one instruction and + * generate an exception. + * If irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear + * the flag and abort the translation to give the irqs a + * chance to happen. + */ + dc->base.is_jmp = DISAS_TOO_MANY; + } else if (!is_same_page(&dc->base, pc_next)) { + dc->base.is_jmp = DISAS_TOO_MANY; + } } } } From patchwork Tue Sep 6 10:09:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602993 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4404515mae; Tue, 6 Sep 2022 03:43:46 -0700 (PDT) X-Google-Smtp-Source: AA6agR4M7khaxVGBpORD/CUSfqXpLwcbwCb7Brap1isCsXH1tH7oWaZlT2ADf/ap2d93O3WEhRtO X-Received: by 2002:ac8:5f54:0:b0:344:a210:3f64 with SMTP id y20-20020ac85f54000000b00344a2103f64mr42868621qta.683.1662461026221; Tue, 06 Sep 2022 03:43:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662461026; cv=none; d=google.com; s=arc-20160816; b=K3ppQrt5iv9iL5g3O/ZBUjbNecGCu5oi9pPK7g/lRrJoKlJdQfXU0TdRWvW9gU9y0V xV1asbnJ7BpHvwlYxfBfGHkSYFwBpT0ul7axFTsqJLxyft5S/uXcOIqP4TUp009GIxD+ Vl8feR9UefmJtOVP87y1k8Fqs9xHYHu2FbLkn3M7QEaRUafKQN7x3LkTj4D/6bCfh3Dr 56zHXtj3ocWqCbMwJ6xREHT8+lcqg6GpMf7T6+rUQRGaCWJ/tFkXXQMOnzougs33v/Dw XzSIbPtfHmM/LW6pEXFGKyO1n30E5Gx5A2Px2zG/TwxFKe2YM4+rYJHmx3Go4lTxmlrQ zqMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RhzKSK5t9n+kSLhXSJS3gAkwrU8yfE69BjVDNOiZ1lI=; b=iUnsXjAmlnvSXcvJntTIcZuZ8819VC6+KbeiBxijqo6vUlciortuaZOsuq2GCQocM9 r27nsv/cQL1VokIFiWmi0Wb8kSEXvOTUNORvVrFBoySEEDKaQSOWiTplSPFJPNeAGDfj UwHRwuGlB9tuYhPBAMJvlLhz44Y9L/ZfEDvl3IOJRZUMKPpDgEjefDfBuGvu6EjAG1CK uCewjl+1JM5jyem+wE/iCJo7Ohkr70eXweeamyesKubpv7RHau9FoRLieZIyKDLgrTqH DperRezqjvZKh2HGV4jEdrenKNP+JPK2tE1JqIjcQqhDA+oSDdaic0NCTRf/A8AJtW0b Nt/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LMhHqvzf; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Note the special case of EXCP_VSYSCALL in which s->cs_base didn't have the subtraction, but cs_base is always zero in 64-bit mode, when vsyscall is used. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 46300ffd91..58e74c3162 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -1332,10 +1332,10 @@ static void gen_helper_fp_arith_STN_ST0(int op, int opreg) } } -static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) +static void gen_exception(DisasContext *s, int trapno) { gen_update_cc_op(s); - gen_jmp_im(s, cur_eip); + gen_jmp_im(s, s->base.pc_next - s->cs_base); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); s->base.is_jmp = DISAS_NORETURN; } @@ -1344,13 +1344,13 @@ static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip) the instruction is known, but it isn't allowed in the current cpu mode. */ static void gen_illegal_opcode(DisasContext *s) { - gen_exception(s, EXCP06_ILLOP, s->base.pc_next - s->cs_base); + gen_exception(s, EXCP06_ILLOP); } /* Generate #GP for the current instruction. */ static void gen_exception_gpf(DisasContext *s) { - gen_exception(s, EXCP0D_GPF, s->base.pc_next - s->cs_base); + gen_exception(s, EXCP0D_GPF); } /* Check for cpl == 0; if not, raise #GP and return false. */ @@ -3240,7 +3240,7 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b) } /* simple MMX/SSE operation */ if (s->flags & HF_TS_MASK) { - gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); + gen_exception(s, EXCP07_PREX); return; } if (s->flags & HF_EM_MASK) { @@ -6042,7 +6042,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { /* if CR0.EM or CR0.TS are set, generate an FPU exception */ /* XXX: what to do if illegal op ? */ - gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); + gen_exception(s, EXCP07_PREX); break; } modrm = x86_ldub_code(env, s); @@ -7267,7 +7267,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; val = x86_ldub_code(env, s); if (val == 0) { - gen_exception(s, EXCP00_DIVZ, s->base.pc_next - s->cs_base); + gen_exception(s, EXCP00_DIVZ); } else { gen_helper_aam(cpu_env, tcg_const_i32(val)); set_cc_op(s, CC_OP_LOGICB); @@ -7301,7 +7301,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0x9b: /* fwait */ if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) == (HF_MP_MASK | HF_TS_MASK)) { - gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); + gen_exception(s, EXCP07_PREX); } else { gen_helper_fwait(cpu_env); } @@ -8358,7 +8358,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { - gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); + gen_exception(s, EXCP07_PREX); break; } gen_lea_modrm(env, s, modrm); @@ -8371,7 +8371,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) { - gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); + gen_exception(s, EXCP07_PREX); break; } gen_lea_modrm(env, s, modrm); @@ -8383,7 +8383,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->flags & HF_TS_MASK) { - gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); + gen_exception(s, EXCP07_PREX); break; } gen_lea_modrm(env, s, modrm); @@ -8396,7 +8396,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } if (s->flags & HF_TS_MASK) { - gen_exception(s, EXCP07_PREX, s->base.pc_next - s->cs_base); + gen_exception(s, EXCP07_PREX); break; } gen_helper_update_mxcsr(cpu_env); @@ -8787,7 +8787,7 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * Detect entry into the vsyscall page and invoke the syscall. */ if ((dc->base.pc_next & TARGET_PAGE_MASK) == TARGET_VSYSCALL_PAGE) { - gen_exception(dc, EXCP_VSYSCALL, dc->base.pc_next); + gen_exception(dc, EXCP_VSYSCALL); dc->base.pc_next = dc->pc + 1; return; } From patchwork Tue Sep 6 10:09:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603005 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4416008mae; Tue, 6 Sep 2022 04:01:11 -0700 (PDT) X-Google-Smtp-Source: AA6agR61BFBxce2x9AV4og31DYUN38dB1B219jns8tHB9tgOex0U6DYcsAAhjrr9QxS7iss/blDy X-Received: by 2002:a05:622a:24a:b0:343:75d6:ad0a with SMTP id c10-20020a05622a024a00b0034375d6ad0amr43476966qtx.564.1662462071197; Tue, 06 Sep 2022 04:01:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662462071; cv=none; d=google.com; s=arc-20160816; b=Q6pALYpZirmdJPb25Gr6dVsesrHzbvs7CUXdojmVKlTRGEYwEMARMkVtjRSzpz/0HI YrU9PF9o/zyNC+t5qQtuvIzVL2/yxaYL4THnq1bNAbY9wPRP3Aj5Lw/lvYRtNLWEL/A7 Nqp55SQD4ywS+n+vo/Rvp2SxMdtNU10yj4u6KKQdxLSo9Lvyt7g62njVO9pG2l4fiAW4 Eykwosc/61xAXB8NsCYYJt/5C1BjWXPpwuvB1NS6wuahiDdAFGhGqBTZPU9B9JaZGTcv ao9e2dM+JVFD696OvOXkzLjJK5WN0GX5vvarB8d1uP0Q2jDXRT9tAS+NlTk5J9ilvlDo 0XmQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Od9/5sVYEyw5aM2oCw6JowpUd9okmRwg1CwHbwIH7Qk=; b=mMWQbZWs0ElIuSqBLI7/imE+sFvNB+yLI8pMKpVAJmP4hilMI3vRBbzhF4LJUxM9ES 4czcuDl8joV7EWBH0KHSswPuq+Gs+yfQDmNFp0nSADsAH5oJLexQPQSN1iLZqFZXjppG 9pKDGpg9svThaBv50/Z6+9Z3891ANp6iwy/ersvCDSgsbZ5rSgkCS2Xp97DWegnm1nw8 SJX9lChv/in/RFTXpWRU/ycKdhGKsuQMh1oo8Im3HyUAJBUZs3/PfItX8KWeDSP05Rxw E6jlKnLHPtsKqNOwPxc3ZoV3/5Rz8tztZobc+WAFtC9J5V4IZySd5DnUKLgW4HtLH4FB oClQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a4UOPUzQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 13 ++++++------- 1 file changed, 6 insertions(+), 7 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 58e74c3162..0210382f77 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2602,13 +2602,12 @@ static void gen_unknown_opcode(CPUX86State *env, DisasContext *s) /* an interrupt is different from an exception because of the privilege checks */ -static void gen_interrupt(DisasContext *s, int intno, - target_ulong cur_eip, target_ulong next_eip) +static void gen_interrupt(DisasContext *s, int intno) { gen_update_cc_op(s); - gen_jmp_im(s, cur_eip); - gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno), - tcg_const_i32(next_eip - cur_eip)); + gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_helper_raise_interrupt(cpu_env, tcg_constant_i32(intno), + tcg_constant_i32(s->pc - s->base.pc_next)); s->base.is_jmp = DISAS_NORETURN; } @@ -7307,12 +7306,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } break; case 0xcc: /* int3 */ - gen_interrupt(s, EXCP03_INT3, s->base.pc_next - s->cs_base, s->pc - s->cs_base); + gen_interrupt(s, EXCP03_INT3); break; case 0xcd: /* int N */ val = x86_ldub_code(env, s); if (check_vm86_iopl(s)) { - gen_interrupt(s, val, s->base.pc_next - s->cs_base, s->pc - s->cs_base); + gen_interrupt(s, val); } break; case 0xce: /* into */ From patchwork Tue Sep 6 10:09:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602985 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4394600mae; Tue, 6 Sep 2022 03:29:21 -0700 (PDT) X-Google-Smtp-Source: AA6agR7q6nrgTEjJy/OAegoi6KFGvKYLap5CMP0kQDlo1f1tuRqdKCJc/bDPQaoYTqubcd9vC/3P X-Received: by 2002:a05:620a:1525:b0:6bb:871f:ec8e with SMTP id n5-20020a05620a152500b006bb871fec8emr34719420qkk.48.1662460161316; Tue, 06 Sep 2022 03:29:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662460161; cv=none; d=google.com; s=arc-20160816; b=cmD0kSnmzDXfDVjnaeKnr2mOJa74hz5brmB7IoynNoBSzzYzgYUQb/LXgZJGi3OAqX tMt4SlEX6NXuiAtFqte6YR3I8SAp/LAKNovF1c/H70hm4dgQsKKpGBPMIAvLi4uOxddW CFsflLr/qqUTHgyriREk1t7A6t9u7boNsUJ7wmfshS8hnGeGUegGCXjbXesrVg978VSw Wo5mMCf2fjIpgLQVpcFifv4NcRqeWGncgwgLgSEIZYumM6U+WJnx78hzWWoeC7avnQBQ ZzYhc+ZvQJhtZHJlXmbs3R7q8r8DSC36g6QvNBTDiVmI2pc568shC6fSM/LFMA7vdrNg YcVA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XY3jiDR+YnmV+m9xmzJFb65HCrzmHvlIwh0Te8PR9uk=; b=ieGVrDe+ke8XpL31zvtQIdZsku43QFDBX0UV6IyG4kJl1acWt8/VlT9jb3W51HkhG/ 5UtJNp7h6sO03p0wtn19FwWrCzZNfT0rEFTOmvZVr+d1Oor5HvuTZynvOCFi2BY9x27w udMrp/lQeroI7DjBZGFvOVEo1CQaPIiWAdshqbtG05NKpWn2QmMPitHkoF41OIS93pa1 xABBLW7fETv/2MVSKR7wKeb1IwylHVX2BctHln4SwqT+CLGKeQdcXTmin9e9MzPLQdnS t/5IOIEy2EQbPXp3cJOtncB+bypSjjcOxA/xynjZvDavaAS2U/dVYrxG9p9UgXqUZI2I juHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="FECEh/M9"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Replace all gen_jmp_im that use s->base.pc_next. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 52 ++++++++++++++++++++----------------- 1 file changed, 28 insertions(+), 24 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 0210382f77..83cb925571 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -511,10 +511,14 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) } } -static inline void gen_jmp_im(DisasContext *s, target_ulong pc) +static void gen_jmp_im(DisasContext *s, target_ulong pc) { - tcg_gen_movi_tl(s->tmp0, pc); - gen_op_jmp_v(s->tmp0); + gen_op_jmp_v(tcg_constant_tl(pc)); +} + +static void gen_update_eip_cur(DisasContext *s) +{ + gen_jmp_im(s, s->base.pc_next - s->cs_base); } /* Compute SEG:REG into A0. SEG is selected from the override segment @@ -703,7 +707,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port, target_ulong next_eip = s->pc - s->cs_base; gen_update_cc_op(s); - gen_jmp_im(s, cur_eip); + gen_update_eip_cur(s); if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { svm_flags |= SVM_IOIO_REP_MASK; } @@ -1335,7 +1339,7 @@ static void gen_helper_fp_arith_STN_ST0(int op, int opreg) static void gen_exception(DisasContext *s, int trapno) { gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno)); s->base.is_jmp = DISAS_NORETURN; } @@ -2605,7 +2609,7 @@ static void gen_unknown_opcode(CPUX86State *env, DisasContext *s) static void gen_interrupt(DisasContext *s, int intno) { gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_raise_interrupt(cpu_env, tcg_constant_i32(intno), tcg_constant_i32(s->pc - s->base.pc_next)); s->base.is_jmp = DISAS_NORETURN; @@ -6796,7 +6800,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) do_lret: if (PE(s) && !VM86(s)) { gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_lret_protected(cpu_env, tcg_const_i32(dflag - 1), tcg_const_i32(val)); } else { @@ -7292,7 +7296,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } if (prefixes & PREFIX_REPZ) { gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_pause(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); s->base.is_jmp = DISAS_NORETURN; } @@ -7318,7 +7322,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (CODE64(s)) goto illegal_op; gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_into(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); break; #ifdef WANT_ICEBP @@ -7425,7 +7429,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0x132: /* rdmsr */ if (check_cpl0(s)) { gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); if (b & 2) { gen_helper_rdmsr(cpu_env); } else { @@ -7437,7 +7441,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; case 0x131: /* rdtsc */ gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -7448,7 +7452,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; case 0x133: /* rdpmc */ gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_rdpmc(cpu_env); s->base.is_jmp = DISAS_NORETURN; break; @@ -7478,7 +7482,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0x105: /* syscall */ /* XXX: is it usable in real mode ? */ gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); /* TF handling for the syscall insn is different. The TF bit is checked after the syscall insn completes. This allows #DB to not be @@ -7504,13 +7508,13 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) #endif case 0x1a2: /* cpuid */ gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_cpuid(cpu_env); break; case 0xf4: /* hlt */ if (check_cpl0(s)) { gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); s->base.is_jmp = DISAS_NORETURN; } @@ -7607,7 +7611,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); tcg_gen_mov_tl(s->A0, cpu_regs[R_EAX]); gen_extu(s->aflag, s->A0); gen_add_A0_ds_seg(s); @@ -7619,7 +7623,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); s->base.is_jmp = DISAS_NORETURN; break; @@ -7697,7 +7701,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), tcg_const_i32(s->pc - s->base.pc_next)); tcg_gen_exit_tb(NULL, 0); @@ -7709,7 +7713,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_vmmcall(cpu_env); break; @@ -7721,7 +7725,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag - 1)); break; @@ -7733,7 +7737,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag - 1)); break; @@ -7759,7 +7763,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); gen_helper_clgi(cpu_env); break; @@ -7905,7 +7909,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_update_cc_op(s); - gen_jmp_im(s, s->base.pc_next - s->cs_base); + gen_update_eip_cur(s); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); } @@ -8818,7 +8822,7 @@ static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) DisasContext *dc = container_of(dcbase, DisasContext, base); if (dc->base.is_jmp == DISAS_TOO_MANY) { - gen_jmp_im(dc, dc->base.pc_next - dc->cs_base); + gen_update_eip_cur(dc); gen_eob(dc); } } From patchwork Tue Sep 6 10:09:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603012 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4427152mae; Tue, 6 Sep 2022 04:13:16 -0700 (PDT) X-Google-Smtp-Source: AA6agR6pult/LBDLldfEuEzHJjvJ4B40g+d6zc1NIk3KIME+9uDCGOHiEpKj1vja4c69MtEby6eM X-Received: by 2002:ac8:5908:0:b0:344:5f5b:5497 with SMTP id 8-20020ac85908000000b003445f5b5497mr43158246qty.632.1662462796002; Tue, 06 Sep 2022 04:13:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662462795; cv=none; d=google.com; s=arc-20160816; b=pLURXZVyrrM/APkVMT+k2DKZx2+W3wH1wl8CSuuZlBmZY8JKD5KBJ0GpT457xfEQef WewySeHVt6HXQJ0RiDe7E/y5mkz1IHxaSSxEJSIMSe9/oatTo8LXvNa+CdbfsdZRNm9o t8FuW2HUMQjqxf39JKf5NZLuuLbEC47RkuuTOT1SnwH1vFJuKZIQRSvYyf0uH9XBnN/A L8B3cYmaMaCtCUpicOyBBIOTTunBweOPsN09N+T4OZvzLTs5ris7R8oTGwRwPcbjAw0/ tJOaeY6wD5bQ2TWUn2M6FaGfCRvVmAAVaR9x1ZZTwPrKQmMcXCiXNOX9+yHjDWPqhEGq uyQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=aUBsYW/QRw3rgQbxhH7BMtH6y0cZ7U+xZYhacWoq3cc=; b=DJORCHTSnmoeK46Bzsx12vdV0hdurRULohTQ7FQKpWJ2P11UBhbQYdIch+vp6jiD8E Rt8KyoDIXV5V3jA2L/sGIYk/O2KyORDc6YUYDFDHPE3/S+RmJSwqVgNsra+gL2zlTlSj PVe9obPngmgRIHidZh1M8sZ7ENoPG5Xkv4GIAfuR9jYrTZtRgiT9kzJxAPt/qYMgc+r7 1xou//RS9uzUmoO/4l9YNSrN+OQ4FgYQZvds0+MKajqgGLsSrNW8/DWhA6ydaarfBO9x 1LEQrsZ3Vjl+soVGTB3l1jLIesdIx2pnka9Ux4BiSVCPHkzgr7ecEvj+INGc6hMdI0jD W1RA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ibHvXVO+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Replace all gen_jmp_im that use s->pc. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 45 ++++++++++++++++++++----------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 83cb925571..6084c85609 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -521,6 +521,11 @@ static void gen_update_eip_cur(DisasContext *s) gen_jmp_im(s, s->base.pc_next - s->cs_base); } +static void gen_update_eip_next(DisasContext *s) +{ + gen_jmp_im(s, s->pc - s->cs_base); +} + /* Compute SEG:REG into A0. SEG is selected from the override segment (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to indicate no override. */ @@ -5675,7 +5680,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_pop_update(s, ot); /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */ if (s->base.is_jmp) { - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); if (reg == R_SS) { s->flags &= ~HF_TF_MASK; gen_eob_inhibit_irq(s, true); @@ -5690,7 +5695,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_movl_seg_T0(s, (b >> 3) & 7); gen_pop_update(s, ot); if (s->base.is_jmp) { - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); } break; @@ -5741,7 +5746,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_movl_seg_T0(s, reg); /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */ if (s->base.is_jmp) { - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); if (reg == R_SS) { s->flags &= ~HF_TF_MASK; gen_eob_inhibit_irq(s, true); @@ -5948,7 +5953,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) /* then put the data */ gen_op_mov_reg_v(s, ot, reg, s->T1); if (s->base.is_jmp) { - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); } break; @@ -7004,7 +7009,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_pop_update(s, ot); set_cc_op(s, CC_OP_EFLAGS); /* abort translation because TF/AC flag may change */ - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); } break; @@ -7340,7 +7345,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (check_iopl(s)) { gen_helper_sti(cpu_env); /* interruptions are enabled only the first insn after sti */ - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob_inhibit_irq(s, true); } break; @@ -7416,7 +7421,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_set_label(l3); - gen_jmp_im(s, next_eip); + gen_update_eip_next(s); tcg_gen_br(l2); gen_set_label(l1); @@ -7434,7 +7439,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_helper_rdmsr(cpu_env); } else { gen_helper_wrmsr(cpu_env); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); } } @@ -7634,7 +7639,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_helper_clac(cpu_env); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); break; @@ -7644,7 +7649,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_helper_stac(cpu_env); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); break; @@ -7689,7 +7694,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]); gen_helper_xsetbv(cpu_env, s->tmp2_i32, s->tmp1_i64); /* End TB because translation flags may change. */ - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); break; @@ -7751,7 +7756,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_helper_stgi(cpu_env); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); break; @@ -7790,7 +7795,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_ext32u_tl(s->A0, cpu_regs[R_EAX]); } gen_helper_flush_page(cpu_env, s->A0); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); break; @@ -7874,7 +7879,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_andi_tl(s->T1, s->T1, ~0xe); tcg_gen_or_tl(s->T0, s->T0, s->T1); gen_helper_write_crN(cpu_env, tcg_constant_i32(0), s->T0); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); break; @@ -7885,7 +7890,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, SVM_EXIT_INVLPG); gen_lea_modrm(env, s, modrm); gen_helper_flush_page(cpu_env, s->A0); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); break; @@ -8285,7 +8290,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg); gen_op_mov_v_reg(s, ot, s->T0, rm); gen_helper_write_crN(cpu_env, tcg_constant_i32(reg), s->T0); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); } else { gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg); @@ -8320,7 +8325,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_op_mov_v_reg(s, ot, s->T0, rm); tcg_gen_movi_i32(s->tmp2_i32, reg); gen_helper_set_dr(cpu_env, s->tmp2_i32, s->T0); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); } else { gen_svm_check_intercept(s, SVM_EXIT_READ_DR0 + reg); @@ -8335,7 +8340,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); gen_helper_clts(cpu_env); /* abort block because static cpu state changed */ - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); } break; @@ -8433,7 +8438,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) /* XRSTOR is how MPX is enabled, which changes how we translate. Thus we need to end the TB. */ gen_update_cc_op(s); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_eob(s); break; @@ -8567,7 +8572,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) g_assert_not_reached(); #else gen_update_cc_op(s); - gen_jmp_im(s, s->pc - s->cs_base); + gen_update_eip_next(s); gen_helper_rsm(cpu_env); #endif /* CONFIG_USER_ONLY */ gen_eob(s); From patchwork Tue Sep 6 10:09:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602988 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4398152mae; Tue, 6 Sep 2022 03:34:31 -0700 (PDT) X-Google-Smtp-Source: AA6agR4GTrXzbyqXO+Bpf6kTWRPh4iqhUZ1/0wr+4AnICOHCUul4QTjy7V/zb3jyFBLF4i4HYMgR X-Received: by 2002:ac8:5a96:0:b0:344:b3be:6931 with SMTP id c22-20020ac85a96000000b00344b3be6931mr43205645qtc.509.1662460471791; Tue, 06 Sep 2022 03:34:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662460471; cv=none; d=google.com; s=arc-20160816; b=uPRU1qdvcIfxPr1YCpepEbXVfkFLLT+W/3/WoSGvAVMn2beMmhEsL/UdQMSpENs5bK FJo3+hdEX5RMgxUDwZOLRLLRRlL9y3agUORSDT411fTw7lDejQUhJ8Awjl7ZfCPvKwsd hkP8mkYqRvsl9lzsRAoi4ZHR0xuDd349q7EK/TzkzwnG/IcUKcMoO+sStc34X+e/Crys xC6/IzDOKLn8SoLB53yAzuZgcs1jTpPJrD5OtQO7f2Z2tDXQcW9gAM8gA46+rlmEI/Ke qhvmptL08f8rwdqsFQXSX2Ke3p1f/HdhjIYpUVB7FrVKteaaLCBo3xdErbTQYTgQzZ+n O9Qg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+72IzKWpZvSMbM+2/DHbf+q0Byo3Mf/mB+Cs1AVNt98=; b=AuWO+mG6dj7tHZZdNObA5J0nYGu8D5YGXTvc83jnogqtN9ZgvRtCoZau8qiSFMraq1 6AhMoIjLp6ZJZlgYm4aTRJnEYNfo77Q4cj1GOhLLV5lL77APE/muVHltB/LJpmF30p+B cJU+k3qVUJ/OixgmRDti4x1HGnUG1Qw9D0VZ+d36lgal0VFARs55h6eiFb9JFt+hUZ2v erEo+tUnebhtHVjip2vFrWI/uD9pGb8w/3kO+GT8kBYdIFOOD8op8AmV2B1SJSWqZoOV IpGR9P/TNmFtTiY8fEW4XZg/zciYmhl92XwQ3nll/pCPqsrtYA48fz5M6CaF6iVd9qpE lhrw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JOY+U8W7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id a2-20020ac81082000000b003446b11e332si6285286qtj.316.2022.09.06.03.34.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Sep 2022 03:34:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JOY+U8W7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:35924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVVuZ-0001jG-Cl for patch@linaro.org; Tue, 06 Sep 2022 06:34:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47164) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVVWa-0000AK-35 for qemu-devel@nongnu.org; Tue, 06 Sep 2022 06:09:45 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:44015) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oVVWY-0003ZF-HF for qemu-devel@nongnu.org; Tue, 06 Sep 2022 06:09:43 -0400 Received: by mail-wr1-x42b.google.com with SMTP id t7so9629043wrm.10 for ; Tue, 06 Sep 2022 03:09:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=+72IzKWpZvSMbM+2/DHbf+q0Byo3Mf/mB+Cs1AVNt98=; b=JOY+U8W7Gm31IrQjc1zdq7B0ZCf5sFz5VxvA4DWpvNAsnhidtsyZ4t1ZPfp9jttUUB EndReDxRO+BDmO2g9oEyvTIFvQXJM1/So+um4o6LdTqOj33jcd5U3kfAdyRd6OsFBa6r 9qZ1GrAqijBOZyh6eABtWFnDIHe7mXsMJEhcJ7nfZRDqO93hpeqBRP5L1ywjdo2CUjgK b9ApOtm8tPEBTQuTBp2FHWtGUYPaHM/5VTMR1unBSkJFu/CjLRHT4lYELVM3hTVk7kqF VduXfPyFvw8bxoPKAywN0WlZXJOlTwW0YbRH/1TRvj8o1/lRvlD2jPqk5sVHC+i1pmwg Xw4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=+72IzKWpZvSMbM+2/DHbf+q0Byo3Mf/mB+Cs1AVNt98=; b=gwgVt414iXz8LZ5zi1jTkGkKvTYZG9+WHn1cyPFQ5wa0pOP9i9EFn/bDthE8UH7HKv RsOwtK4SfKB17N9zRG+rPx6z/WhDSDQ7QJgpjOQwiVWlHNYjoWJQQkh7C0yJY2flvQ0Z HJb2PiDy/bCxUzFO3t80+on0gdjqAY5rHXOHrfIug3NFbNNVXfpM2lCMwLnU4j0UIHd+ 7n9QeE1cwe2s29AIUbv+09dS6YFvJXdjFkh96ZOrYgwNZp1BX0cos6Mk8nBcxQtHyFrh b9Tz+z7bY18Xe2ZbSjD5R+Fe7qfEtvpREzTH2J+2pWa3RuIUqBvJFOFDoCiJMR8VE5r9 sRsA== X-Gm-Message-State: ACgBeo3kBymzzTXsDQ/UR9bYgnXsp6z7enEFZf0qtaW8urmUwS5ik3zu 2Urcf4MLc8YkVteBDe+R+myA+Uf3TeXwiZgw X-Received: by 2002:a5d:4e8b:0:b0:228:6439:eb35 with SMTP id e11-20020a5d4e8b000000b002286439eb35mr6906630wru.38.1662458980854; Tue, 06 Sep 2022 03:09:40 -0700 (PDT) Received: from localhost.localdomain ([2a02:8084:a5c0:5a80:ba98:3a71:8524:e0b1]) by smtp.gmail.com with ESMTPSA id f25-20020a1c6a19000000b003a840690609sm23125014wmc.36.2022.09.06.03.09.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 03:09:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 07/23] target/i386: Introduce DISAS_EOB* Date: Tue, 6 Sep 2022 11:09:16 +0100 Message-Id: <20220906100932.343523-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906100932.343523-1-richard.henderson@linaro.org> References: <20220906100932.343523-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Add a few DISAS_TARGET_* aliases to reduce the number of calls to gen_eob() and gen_eob_inhibit_irq(). So far, only update i386_tr_translate_insn for exiting the block because of single-step or previous inhibit irq. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 6084c85609..778ee4ed4c 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -132,6 +132,10 @@ typedef struct DisasContext { TCGOp *prev_insn_end; } DisasContext; +#define DISAS_EOB_ONLY DISAS_TARGET_0 +#define DISAS_EOB_NEXT DISAS_TARGET_1 +#define DISAS_EOB_INHIBIT_IRQ DISAS_TARGET_2 + /* The environment in which user-only runs is constrained. */ #ifdef CONFIG_USER_ONLY #define PE(S) true @@ -8814,7 +8818,7 @@ static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) * the flag and abort the translation to give the irqs a * chance to happen. */ - dc->base.is_jmp = DISAS_TOO_MANY; + dc->base.is_jmp = DISAS_EOB_NEXT; } else if (!is_same_page(&dc->base, pc_next)) { dc->base.is_jmp = DISAS_TOO_MANY; } @@ -8826,9 +8830,24 @@ static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); - if (dc->base.is_jmp == DISAS_TOO_MANY) { + switch (dc->base.is_jmp) { + case DISAS_NORETURN: + break; + case DISAS_TOO_MANY: + case DISAS_EOB_NEXT: + gen_update_cc_op(dc); gen_update_eip_cur(dc); + /* fall through */ + case DISAS_EOB_ONLY: gen_eob(dc); + break; + case DISAS_EOB_INHIBIT_IRQ: + gen_update_cc_op(dc); + gen_update_eip_cur(dc); + gen_eob_inhibit_irq(dc, true); + break; + default: + g_assert_not_reached(); } } From patchwork Tue Sep 6 10:09:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602997 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4409244mae; Tue, 6 Sep 2022 03:51:04 -0700 (PDT) X-Google-Smtp-Source: AA6agR6s3b8DuohoPUbwFKADc2vp5Cj6cJwKozemCuqzPwBOAurtcDFVge7lAm2/+2UnUa2CUOEi X-Received: by 2002:ad4:5d62:0:b0:4aa:9d09:2d63 with SMTP id fn2-20020ad45d62000000b004aa9d092d63mr3358211qvb.100.1662461464025; Tue, 06 Sep 2022 03:51:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662461464; cv=none; d=google.com; s=arc-20160816; b=XhsZKLSTCe6uZdG8JZRGyXMcJvZHcJKc9R4bzMRK+J61nZQsby0zAylCQyx0eYVIr4 UYrtI2KoewiSScnKOgzWgpCtVsKj3kPmg2TJxIDmgbJVCWXeolMf0mlEqHP3WxBuxrOF r1N0cpXSQuUT5lVhM+3TvuNGlNhw1NtRrC26PjL26pQbrQJzP4HTx9InNfVRfy/WPPZf oTHz6bFbYs8UhdXFAWjQmPM/ZvdRGLArKnrqXWchrRhDmXkrBgN50XHDT2YYWGCk0pNE qJuc2uVlRc5hbqkZ8YbsADrtlll/qKwQktep81t6h5CaAyHGPqT0/cT/b1V1vqceB8R7 72pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pstCvedhP85R8a4eYJRnMyGD8r8ruJDFqMM28CjwXss=; b=TEjSd5/6WbCskOnpLs8duYAZTwdmm07XAyqtpo5TgIchmK3cH1AX3X09xtljmJyZR6 ymeBDiC9R6F9B6FCg7E7wcbKbT6cWq41n3HalpBGn5e221M7ZnbdBxMg+O5B6fzTQa1Z hp15MbNVhHqdSndLKIgl8R+KLSJ56nTb0JcFzZkNfMTxqHh6yvWWrej/URRzQcAfEyqZ 5gIEUvXqxqemW/EQzRU8wZHEcWpEVy7JHgOlul2mZUhmBLVWzqOu2ZIAZ3sVkEOlqY6i P3/f1gL6khiBhKWcdqtRFw5X3KbjtMm4wjBoCLP07sShvWe5HYaQjhiBXMLPz7R+ohKe U1NA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wpVKiuOU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 36 +++++------------------------------- 1 file changed, 5 insertions(+), 31 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 778ee4ed4c..ea35d3e9b4 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2432,13 +2432,15 @@ static void gen_movl_seg_T0(DisasContext *s, X86Seg seg_reg) because ss32 may change. For R_SS, translation must always stop as a special handling must be done to disable hardware interrupts for the next instruction */ - if (seg_reg == R_SS || (CODE32(s) && seg_reg < R_FS)) { - s->base.is_jmp = DISAS_TOO_MANY; + if (seg_reg == R_SS) { + s->base.is_jmp = DISAS_EOB_INHIBIT_IRQ; + } else if (CODE32(s) && seg_reg < R_FS) { + s->base.is_jmp = DISAS_EOB_NEXT; } } else { gen_op_movl_seg_T0_vm(s, seg_reg); if (seg_reg == R_SS) { - s->base.is_jmp = DISAS_TOO_MANY; + s->base.is_jmp = DISAS_EOB_INHIBIT_IRQ; } } } @@ -5682,26 +5684,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) ot = gen_pop_T0(s); gen_movl_seg_T0(s, reg); gen_pop_update(s, ot); - /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */ - if (s->base.is_jmp) { - gen_update_eip_next(s); - if (reg == R_SS) { - s->flags &= ~HF_TF_MASK; - gen_eob_inhibit_irq(s, true); - } else { - gen_eob(s); - } - } break; case 0x1a1: /* pop fs */ case 0x1a9: /* pop gs */ ot = gen_pop_T0(s); gen_movl_seg_T0(s, (b >> 3) & 7); gen_pop_update(s, ot); - if (s->base.is_jmp) { - gen_update_eip_next(s); - gen_eob(s); - } break; /**************************/ @@ -5748,16 +5736,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; gen_ldst_modrm(env, s, modrm, MO_16, OR_TMP0, 0); gen_movl_seg_T0(s, reg); - /* Note that reg == R_SS in gen_movl_seg_T0 always sets is_jmp. */ - if (s->base.is_jmp) { - gen_update_eip_next(s); - if (reg == R_SS) { - s->flags &= ~HF_TF_MASK; - gen_eob_inhibit_irq(s, true); - } else { - gen_eob(s); - } - } break; case 0x8c: /* mov Gv, seg */ modrm = x86_ldub_code(env, s); @@ -5956,10 +5934,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_movl_seg_T0(s, op); /* then put the data */ gen_op_mov_reg_v(s, ot, reg, s->T1); - if (s->base.is_jmp) { - gen_update_eip_next(s); - gen_eob(s); - } break; /************************/ From patchwork Tue Sep 6 10:09:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602990 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4402689mae; Tue, 6 Sep 2022 03:41:13 -0700 (PDT) X-Google-Smtp-Source: AA6agR6W0gteLyOtH+ckQT+1I7LzlQREg4v8nleC6EJ9UaDqD5VyFMy7nufDn6CR0XDasKC0da47 X-Received: by 2002:a37:8744:0:b0:6bc:1d10:5369 with SMTP id j65-20020a378744000000b006bc1d105369mr34920925qkd.14.1662460873636; Tue, 06 Sep 2022 03:41:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662460873; cv=none; d=google.com; s=arc-20160816; b=r1bdS+KuoLQv4hnOt8rB2EzppPP397WEXvL4I+DrU9uciih9aoCtTGB0COlWi7KiEx c2A7ktZZ18cHHScNj4ex/6J/EYon0C1rb/UWqjAqY4ql6c3nN4SirnBnxrFMFWkIyMvS e1Oz+1WWAWsid0k+mxRgMj+Ay5UC+cC2mbX9NmqJyIQ93MxNLY/0h+j/AH/tweZxk2Ng 7MqPGfiOZuE3ZTKsTS8OiShJCkRwylSgu5ODC6sO3TFEL/vca9K7M+bMV58F+njoKb0K 9vIVIlFT7gUSoGM05oWVV6YotG/Vk8N70WNYM75g6wAc4f74NpCOORCGxYp1Jnw44EZF t7nQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HRPRLy7RM/tEvMRRlQvfL/D1iT20pN8vpm8/OZpor/k=; b=H9twyziDFLW29lHVlyIv0/fFgT3oGoAQ/iqHHT2GFzkktMFBhwPuESuDvxjLT8mBIJ srrSwKXcVvhTs4htIy8SVQxR+8Rqv3CemSQXXaei+74N/VhYEWqWBdcCkVQf9hUn4cPH +krgSjdWMrQOTvbCsDhX/4pmUX0nYcZ9RJ/eClkh4n/aHT6ReVjhm2YGo70d39oQosr8 VpZhwiA2krwS6NgTqVnd4mr51bIhA+B4TKV/rZZ5KyvY1Rwh54UGegILUCETV7wVBZN5 Xc5kNGXvbVImp3VGhTWaP8zCn8Nrfi5qRCshtFolNzQWZt2H/QTx6chHi7WbMHac+wJc 4INA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o6AOFI0s; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 40 ++++++++++++------------------------- 1 file changed, 13 insertions(+), 27 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index ea35d3e9b4..a7e5bcdec7 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -6987,8 +6987,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_pop_update(s, ot); set_cc_op(s, CC_OP_EFLAGS); /* abort translation because TF/AC flag may change */ - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; } break; case 0x9e: /* sahf */ @@ -7417,8 +7416,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_helper_rdmsr(cpu_env); } else { gen_helper_wrmsr(cpu_env); - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; } } break; @@ -7617,8 +7615,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_helper_clac(cpu_env); - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; break; case 0xcb: /* stac */ @@ -7627,8 +7624,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; } gen_helper_stac(cpu_env); - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; break; CASE_MODRM_MEM_OP(1): /* sidt */ @@ -7672,8 +7668,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_trunc_tl_i32(s->tmp2_i32, cpu_regs[R_ECX]); gen_helper_xsetbv(cpu_env, s->tmp2_i32, s->tmp1_i64); /* End TB because translation flags may change. */ - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; break; case 0xd8: /* VMRUN */ @@ -7734,8 +7729,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_helper_stgi(cpu_env); - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; break; case 0xdd: /* CLGI */ @@ -7773,8 +7767,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_ext32u_tl(s->A0, cpu_regs[R_EAX]); } gen_helper_flush_page(cpu_env, s->A0); - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; break; CASE_MODRM_MEM_OP(2): /* lgdt */ @@ -7857,8 +7850,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_gen_andi_tl(s->T1, s->T1, ~0xe); tcg_gen_or_tl(s->T0, s->T0, s->T1); gen_helper_write_crN(cpu_env, tcg_constant_i32(0), s->T0); - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; break; CASE_MODRM_MEM_OP(7): /* invlpg */ @@ -7868,8 +7860,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, SVM_EXIT_INVLPG); gen_lea_modrm(env, s, modrm); gen_helper_flush_page(cpu_env, s->A0); - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; break; case 0xf8: /* swapgs */ @@ -8268,8 +8259,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg); gen_op_mov_v_reg(s, ot, s->T0, rm); gen_helper_write_crN(cpu_env, tcg_constant_i32(reg), s->T0); - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; } else { gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg); gen_helper_read_crN(s->T0, cpu_env, tcg_constant_i32(reg)); @@ -8303,8 +8293,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_op_mov_v_reg(s, ot, s->T0, rm); tcg_gen_movi_i32(s->tmp2_i32, reg); gen_helper_set_dr(cpu_env, s->tmp2_i32, s->T0); - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; } else { gen_svm_check_intercept(s, SVM_EXIT_READ_DR0 + reg); tcg_gen_movi_i32(s->tmp2_i32, reg); @@ -8318,8 +8307,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0); gen_helper_clts(cpu_env); /* abort block because static cpu state changed */ - gen_update_eip_next(s); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_NEXT; } break; /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */ @@ -8415,9 +8403,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_helper_xrstor(cpu_env, s->A0, s->tmp1_i64); /* XRSTOR is how MPX is enabled, which changes how we translate. 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index a7e5bcdec7..5b77414a0a 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -6800,7 +6800,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) /* add stack offset */ gen_stack_update(s, val + (2 << dflag)); } - gen_eob(s); + s->base.is_jmp = DISAS_EOB_ONLY; break; case 0xcb: /* lret */ val = 0; @@ -6818,7 +6818,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_const_i32(s->pc - s->cs_base)); } set_cc_op(s, CC_OP_EFLAGS); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_ONLY; break; case 0xe8: /* call im */ { @@ -7404,7 +7404,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_set_label(l1); gen_jmp_im(s, tval); gen_set_label(l2); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_ONLY; } break; case 0x130: /* wrmsr */ @@ -7445,7 +7445,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_exception_gpf(s); } else { gen_helper_sysenter(cpu_env); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_ONLY; } break; case 0x135: /* sysexit */ @@ -7456,7 +7456,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_exception_gpf(s); } else { gen_helper_sysexit(cpu_env, tcg_const_i32(dflag - 1)); - gen_eob(s); + s->base.is_jmp = DISAS_EOB_ONLY; } break; #ifdef TARGET_X86_64 @@ -8539,7 +8539,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_update_eip_next(s); gen_helper_rsm(cpu_env); #endif /* CONFIG_USER_ONLY */ - gen_eob(s); + s->base.is_jmp = DISAS_EOB_ONLY; break; case 0x1b8: /* SSE4.2 popcnt */ if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) != From patchwork Tue Sep 6 10:09:20 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603001 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4412806mae; Tue, 6 Sep 2022 03:57:04 -0700 (PDT) X-Google-Smtp-Source: AA6agR6xFOlAvXA+8R6cWcFa9pADeBzw1W8p+JHDInSq6lYqc5SYBzOblq42QUGgmILTywdn724K X-Received: by 2002:a05:622a:1010:b0:342:fb08:271f with SMTP id d16-20020a05622a101000b00342fb08271fmr44141761qte.85.1662461824662; Tue, 06 Sep 2022 03:57:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662461824; cv=none; d=google.com; s=arc-20160816; b=aV88MZJYvRecj82z9DjQ/RKc3AUaeulY6UXHODI84sfwI1Lxh19Q1wWLMspojQ7x2r UkbZSU9b0BYpe6vrvRlDuaYNXvHUh0kVY6OEIwm24qDw/Q9sCp8uaJQeDETTMxuehQI9 dE/ABE6ZMzXNFKFbG3lhvMdYDlKZtlpSzu6cNgIeO+jVZ6MJjbeTAmjgaFxu54PuTJ4e a5UNL5HPh/lpI/lUqjwRkd0Fm+tRDrnPs6h3OWiNcy9dwOfgIkREbEUEYZa8Q+9+cixS 3Iw/9TLZR1xYqGNqjfBbm0cB9+ya/CK/m27LUz0iUtz6ggRpCLtOPYN068X/fFmIga0o DL1g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uhX1Xco1uYXotp7Ii6JdWoo4PEBreN+vBGI94DPHWfc=; b=GCOfZKnrZ74QC6WfFFa008aPhvw/rmMVyv22HkVU8nY3iz/fI3ba/P3lxh2P7Eah/k QxfEGLrbM1GIXEMLrlLnNhxX+y+ruRY/YVXGO8aDPOgVUANQp1SJgHPNV0Z4Ywh9Fcxb titwoucVV8fZQbxrM+Ord8oUzsbQAYsuEIUCvp121OmK6u/sAaS+8y9dvR/LQ1+h23lb sRnFMaM4tElNGE7rmHftRfcT0BzX+Yqi8+nXEEOEweGcs3zIsazjwhZ2IPm9XTMm/SMy sWEPWBc3Zj6T2vec7DLJaCjnnWDb3RWdSYAzh6sUWxifpbG/9vGGU1o8uQjg0OM8BP1p lcFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yT5Wpoam; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 5b77414a0a..393a1c1075 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -530,6 +530,16 @@ static void gen_update_eip_next(DisasContext *s) gen_jmp_im(s, s->pc - s->cs_base); } +static int cur_insn_len(DisasContext *s) +{ + return s->pc - s->base.pc_next; +} + +static TCGv_i32 cur_insn_len_i32(DisasContext *s) +{ + return tcg_constant_i32(cur_insn_len(s)); +} + /* Compute SEG:REG into A0. SEG is selected from the override segment (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to indicate no override. */ @@ -712,9 +722,6 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port, gen_helper_check_io(cpu_env, port, tcg_constant_i32(1 << ot)); } if (GUEST(s)) { - target_ulong cur_eip = s->base.pc_next - s->cs_base; - target_ulong next_eip = s->pc - s->cs_base; - gen_update_cc_op(s); gen_update_eip_cur(s); if (s->prefix & (PREFIX_REPZ | PREFIX_REPNZ)) { @@ -723,7 +730,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port, svm_flags |= 1 << (SVM_IOIO_SIZE_SHIFT + ot); gen_helper_svm_check_io(cpu_env, port, tcg_constant_i32(svm_flags), - tcg_constant_i32(next_eip - cur_eip)); + cur_insn_len_i32(s)); } return true; #endif @@ -2028,7 +2035,7 @@ static uint64_t advance_pc(CPUX86State *env, DisasContext *s, int num_bytes) } s->pc += num_bytes; - if (unlikely(s->pc - s->base.pc_next > X86_MAX_INSN_LENGTH)) { + if (unlikely(cur_insn_len(s) > X86_MAX_INSN_LENGTH)) { /* If the instruction's 16th byte is on a different page than the 1st, a * page fault on the second page wins over the general protection fault * caused by the instruction being too long. @@ -2622,7 +2629,7 @@ static void gen_interrupt(DisasContext *s, int intno) gen_update_cc_op(s); gen_update_eip_cur(s); gen_helper_raise_interrupt(cpu_env, tcg_constant_i32(intno), - tcg_constant_i32(s->pc - s->base.pc_next)); + cur_insn_len_i32(s)); s->base.is_jmp = DISAS_NORETURN; } @@ -7279,7 +7286,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (prefixes & PREFIX_REPZ) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_pause(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); + gen_helper_pause(cpu_env, cur_insn_len_i32(s)); s->base.is_jmp = DISAS_NORETURN; } break; @@ -7305,7 +7312,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) goto illegal_op; gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_into(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); + gen_helper_into(cpu_env, cur_insn_len_i32(s)); break; #ifdef WANT_ICEBP case 0xf1: /* icebp (undocumented, exits to external debugger) */ @@ -7464,7 +7471,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) /* XXX: is it usable in real mode ? */ gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); + gen_helper_syscall(cpu_env, cur_insn_len_i32(s)); /* TF handling for the syscall insn is different. The TF bit is checked after the syscall insn completes. This allows #DB to not be generated after one has entered CPL0 if TF is set in FMASK. */ @@ -7496,7 +7503,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (check_cpl0(s)) { gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); + gen_helper_hlt(cpu_env, cur_insn_len_i32(s)); s->base.is_jmp = DISAS_NORETURN; } break; @@ -7605,7 +7612,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - s->base.pc_next)); + gen_helper_mwait(cpu_env, cur_insn_len_i32(s)); s->base.is_jmp = DISAS_NORETURN; break; @@ -7681,7 +7688,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_update_cc_op(s); gen_update_eip_cur(s); gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag - 1), - tcg_const_i32(s->pc - s->base.pc_next)); + cur_insn_len_i32(s)); tcg_gen_exit_tb(NULL, 0); s->base.is_jmp = DISAS_NORETURN; break; From patchwork Tue Sep 6 10:09:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602992 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4403694mae; Tue, 6 Sep 2022 03:42:35 -0700 (PDT) X-Google-Smtp-Source: AA6agR793MRvLlm1mDsUUTAgXkzZofQI4h6nIDJ7vH57MyOInjHAyO0hAIeev4ieW6ec/innX0Xw X-Received: by 2002:a0c:904a:0:b0:498:2b0c:1940 with SMTP id o68-20020a0c904a000000b004982b0c1940mr42787189qvo.118.1662460955762; Tue, 06 Sep 2022 03:42:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662460955; cv=none; d=google.com; s=arc-20160816; b=gXPYRSPc2Fnq66b+3R1DSkGYTo+DbkHT+/wpz9Ho7TBAxFuzDU5PXLPQ03PlO26eES mmY3n2p1fAfAWdzZyCISacppY10xHJtmhTBvbxCGYwszoqZfmkLPnBs980qKRhmVENt4 lC17G6s6xFB9E8RE2ctckjPGa3xXeH6QaEk972lgSr+xEb5nZ8ptx0WJQ44aG6Gpy8Ib HUVsUq6AlMTKmmxqadPVgM1yTdugAA4DiIFzDMyPDfKgM9lM/60Ygao4fG7ZObAkHrmx R/ieDuneg069oeN8m8rDFLCgdVY17BOmihZwxjy5u/WsdyDls7NFcDyWiMJU9/gKrkHU nTEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ImMdEaTX3CEfZPkJk9oCqKJjJXONXGkJ+5PrZsNb4SQ=; b=md0xor0HuSP+Kc340BW6+UJO+Auh8aXPJpDvGO8b3CfzpABRcr31Hi89LRmqaPHkcG o7oL/2THGOcH+peR+tZ/Noq10DQZNIZ34Y2VpjSsduzhLG34u6zayZB7zVaEcbV741aK VU3DjTwvyOrmbK4o0/d10wtN+8BAqfOGUuVcfEyjyIzU2bmhrulDjhrsBZ48YpN4nKvF fM4prVAAkHq/6K5rXQLW7xYPqyAui+x+cfOfxHxuo/PUILaMGUL4pdBZ+VYNH6M8S78V rqAN7CPZKEhQKLbDWUeG1GT+1MRw2rdvOnLe48oYN8KFJ7ZrjzjAcvsGleKssGnWt8Gu V/UA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Rkx6iLz4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Pull out common helpers and reduce the amount of code under macros. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 116 ++++++++++++++++++------------------ 1 file changed, 57 insertions(+), 59 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 393a1c1075..f3c26a9956 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -736,7 +736,7 @@ static bool gen_check_io(DisasContext *s, MemOp ot, TCGv_i32 port, #endif } -static inline void gen_movs(DisasContext *s, MemOp ot) +static void gen_movs(DisasContext *s, MemOp ot) { gen_string_movl_A0_ESI(s); gen_op_ld_v(s, ot, s->T0, s->A0); @@ -1156,18 +1156,18 @@ static inline void gen_jcc1(DisasContext *s, int b, TCGLabel *l1) /* XXX: does not work with gdbstub "ice" single step - not a serious problem */ -static TCGLabel *gen_jz_ecx_string(DisasContext *s, target_ulong next_eip) +static TCGLabel *gen_jz_ecx_string(DisasContext *s) { TCGLabel *l1 = gen_new_label(); TCGLabel *l2 = gen_new_label(); gen_op_jnz_ecx(s, s->aflag, l1); gen_set_label(l2); - gen_jmp_tb(s, next_eip, 1); + gen_jmp_tb(s, s->pc - s->cs_base, 1); gen_set_label(l1); return l2; } -static inline void gen_stos(DisasContext *s, MemOp ot) +static void gen_stos(DisasContext *s, MemOp ot) { gen_op_mov_v_reg(s, MO_32, s->T0, R_EAX); gen_string_movl_A0_EDI(s); @@ -1176,7 +1176,7 @@ static inline void gen_stos(DisasContext *s, MemOp ot) gen_op_add_reg_T0(s, s->aflag, R_EDI); } -static inline void gen_lods(DisasContext *s, MemOp ot) +static void gen_lods(DisasContext *s, MemOp ot) { gen_string_movl_A0_ESI(s); gen_op_ld_v(s, ot, s->T0, s->A0); @@ -1185,7 +1185,7 @@ static inline void gen_lods(DisasContext *s, MemOp ot) gen_op_add_reg_T0(s, s->aflag, R_ESI); } -static inline void gen_scas(DisasContext *s, MemOp ot) +static void gen_scas(DisasContext *s, MemOp ot) { gen_string_movl_A0_EDI(s); gen_op_ld_v(s, ot, s->T1, s->A0); @@ -1194,7 +1194,7 @@ static inline void gen_scas(DisasContext *s, MemOp ot) gen_op_add_reg_T0(s, s->aflag, R_EDI); } -static inline void gen_cmps(DisasContext *s, MemOp ot) +static void gen_cmps(DisasContext *s, MemOp ot) { gen_string_movl_A0_EDI(s); gen_op_ld_v(s, ot, s->T1, s->A0); @@ -1222,7 +1222,7 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot) } } -static inline void gen_ins(DisasContext *s, MemOp ot) +static void gen_ins(DisasContext *s, MemOp ot) { gen_string_movl_A0_EDI(s); /* Note: we must do this dummy write first to be restartable in @@ -1238,7 +1238,7 @@ static inline void gen_ins(DisasContext *s, MemOp ot) gen_bpt_io(s, s->tmp2_i32, ot); } -static inline void gen_outs(DisasContext *s, MemOp ot) +static void gen_outs(DisasContext *s, MemOp ot) { gen_string_movl_A0_ESI(s); gen_op_ld_v(s, ot, s->T0, s->A0); @@ -1252,42 +1252,49 @@ static inline void gen_outs(DisasContext *s, MemOp ot) gen_bpt_io(s, s->tmp2_i32, ot); } -/* same method as Valgrind : we generate jumps to current or next - instruction */ -#define GEN_REPZ(op) \ -static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, \ - target_ulong cur_eip, target_ulong next_eip) \ -{ \ - TCGLabel *l2; \ - gen_update_cc_op(s); \ - l2 = gen_jz_ecx_string(s, next_eip); \ - gen_ ## op(s, ot); \ - gen_op_add_reg_im(s, s->aflag, R_ECX, -1); \ - /* a loop would cause two single step exceptions if ECX = 1 \ - before rep string_insn */ \ - if (s->repz_opt) \ - gen_op_jz_ecx(s, s->aflag, l2); \ - gen_jmp(s, cur_eip); \ +/* Generate jumps to current or next instruction */ +static void gen_repz(DisasContext *s, MemOp ot, + void (*fn)(DisasContext *s, MemOp ot)) +{ + TCGLabel *l2; + gen_update_cc_op(s); + l2 = gen_jz_ecx_string(s); + fn(s, ot); + gen_op_add_reg_im(s, s->aflag, R_ECX, -1); + /* + * A loop would cause two single step exceptions if ECX = 1 + * before rep string_insn + */ + if (s->repz_opt) { + gen_op_jz_ecx(s, s->aflag, l2); + } + gen_jmp(s, s->base.pc_next - s->cs_base); } -#define GEN_REPZ2(op) \ -static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, \ - target_ulong cur_eip, \ - target_ulong next_eip, \ - int nz) \ -{ \ - TCGLabel *l2; \ - gen_update_cc_op(s); \ - l2 = gen_jz_ecx_string(s, next_eip); \ - gen_ ## op(s, ot); \ - gen_op_add_reg_im(s, s->aflag, R_ECX, -1); \ - gen_update_cc_op(s); \ - gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); \ - if (s->repz_opt) \ - gen_op_jz_ecx(s, s->aflag, l2); \ - gen_jmp(s, cur_eip); \ +#define GEN_REPZ(op) \ + static inline void gen_repz_ ## op(DisasContext *s, MemOp ot) \ + { gen_repz(s, ot, gen_##op); } + +static void gen_repz2(DisasContext *s, MemOp ot, int nz, + void (*fn)(DisasContext *s, MemOp ot)) +{ + TCGLabel *l2; + gen_update_cc_op(s); + l2 = gen_jz_ecx_string(s); + fn(s, ot); + gen_op_add_reg_im(s, s->aflag, R_ECX, -1); + gen_update_cc_op(s); + gen_jcc1(s, (JCC_Z << 1) | (nz ^ 1), l2); + if (s->repz_opt) { + gen_op_jz_ecx(s, s->aflag, l2); + } + gen_jmp(s, s->base.pc_next - s->cs_base); } +#define GEN_REPZ2(op) \ + static inline void gen_repz_ ## op(DisasContext *s, MemOp ot, int nz) \ + { gen_repz2(s, ot, nz, gen_##op); } + GEN_REPZ(movs) GEN_REPZ(stos) GEN_REPZ(lods) @@ -6588,8 +6595,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0xa5: ot = mo_b_d(b, dflag); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { - gen_repz_movs(s, ot, s->base.pc_next - s->cs_base, - s->pc - s->cs_base); + gen_repz_movs(s, ot); } else { gen_movs(s, ot); } @@ -6599,8 +6605,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0xab: ot = mo_b_d(b, dflag); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { - gen_repz_stos(s, ot, s->base.pc_next - s->cs_base, - s->pc - s->cs_base); + gen_repz_stos(s, ot); } else { gen_stos(s, ot); } @@ -6609,8 +6614,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0xad: ot = mo_b_d(b, dflag); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { - gen_repz_lods(s, ot, s->base.pc_next - s->cs_base, - s->pc - s->cs_base); + gen_repz_lods(s, ot); } else { gen_lods(s, ot); } @@ -6619,11 +6623,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0xaf: ot = mo_b_d(b, dflag); if (prefixes & PREFIX_REPNZ) { - gen_repz_scas(s, ot, s->base.pc_next - s->cs_base, - s->pc - s->cs_base, 1); + gen_repz_scas(s, ot, 1); } else if (prefixes & PREFIX_REPZ) { - gen_repz_scas(s, ot, s->base.pc_next - s->cs_base, - s->pc - s->cs_base, 0); + gen_repz_scas(s, ot, 0); } else { gen_scas(s, ot); } @@ -6633,11 +6635,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0xa7: ot = mo_b_d(b, dflag); if (prefixes & PREFIX_REPNZ) { - gen_repz_cmps(s, ot, s->base.pc_next - s->cs_base, - s->pc - s->cs_base, 1); + gen_repz_cmps(s, ot, 1); } else if (prefixes & PREFIX_REPZ) { - gen_repz_cmps(s, ot, s->base.pc_next - s->cs_base, - s->pc - s->cs_base, 0); + gen_repz_cmps(s, ot, 0); } else { gen_cmps(s, ot); } @@ -6655,8 +6655,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_io_start(); } if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { - gen_repz_ins(s, ot, s->base.pc_next - s->cs_base, - s->pc - s->cs_base); + gen_repz_ins(s, ot); /* jump generated by gen_repz_ins */ } else { gen_ins(s, ot); @@ -6677,8 +6676,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_io_start(); } if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { - gen_repz_outs(s, ot, s->base.pc_next - s->cs_base, - s->pc - s->cs_base); + gen_repz_outs(s, ot); /* jump generated by gen_repz_outs */ } else { gen_outs(s, ot); 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Remove most of the calls to gen_jr, and use DISAS_JUMP. Remove some unused loads of eip for lcall and ljmp. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index f3c26a9956..1997f8d291 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -135,6 +135,7 @@ typedef struct DisasContext { #define DISAS_EOB_ONLY DISAS_TARGET_0 #define DISAS_EOB_NEXT DISAS_TARGET_1 #define DISAS_EOB_INHIBIT_IRQ DISAS_TARGET_2 +#define DISAS_JUMP DISAS_TARGET_3 /* The environment in which user-only runs is constrained. */ #ifdef CONFIG_USER_ONLY @@ -222,7 +223,7 @@ STUB_HELPER(wrmsr, TCGv_env env) #endif static void gen_eob(DisasContext *s); -static void gen_jr(DisasContext *s, TCGv dest); +static void gen_jr(DisasContext *s); static void gen_jmp(DisasContext *s, target_ulong eip); static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); static void gen_op(DisasContext *s1, int op, MemOp ot, int d); @@ -2360,7 +2361,7 @@ static void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) } else { /* jump to another page */ gen_jmp_im(s, eip); - gen_jr(s, s->tmp0); + gen_jr(s); } } @@ -2729,7 +2730,7 @@ static void gen_eob(DisasContext *s) } /* Jump to register */ -static void gen_jr(DisasContext *s, TCGv dest) +static void gen_jr(DisasContext *s) { do_gen_eob_worker(s, false, false, true); } @@ -5284,7 +5285,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_push_v(s, s->T1); gen_op_jmp_v(s->T0); gen_bnd_jmp(s); - gen_jr(s, s->T0); + s->base.is_jmp = DISAS_JUMP; break; case 3: /* lcall Ev */ if (mod == 3) { @@ -5305,8 +5306,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_const_i32(dflag - 1), tcg_const_i32(s->pc - s->cs_base)); } - tcg_gen_ld_tl(s->tmp4, cpu_env, offsetof(CPUX86State, eip)); - gen_jr(s, s->tmp4); + s->base.is_jmp = DISAS_JUMP; break; case 4: /* jmp Ev */ if (dflag == MO_16) { @@ -5314,7 +5314,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_op_jmp_v(s->T0); gen_bnd_jmp(s); - gen_jr(s, s->T0); + s->base.is_jmp = DISAS_JUMP; break; case 5: /* ljmp Ev */ if (mod == 3) { @@ -5332,8 +5332,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_op_movl_seg_T0_vm(s, R_CS); gen_op_jmp_v(s->T1); } - tcg_gen_ld_tl(s->tmp4, cpu_env, offsetof(CPUX86State, eip)); - gen_jr(s, s->tmp4); + s->base.is_jmp = DISAS_JUMP; break; case 6: /* push Ev */ gen_push_v(s, s->T0); @@ -6773,7 +6772,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) /* Note that gen_pop_T0 uses a zero-extending load. */ gen_op_jmp_v(s->T0); gen_bnd_jmp(s); - gen_jr(s, s->T0); + s->base.is_jmp = DISAS_JUMP; break; case 0xc3: /* ret */ ot = gen_pop_T0(s); @@ -6781,7 +6780,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) /* Note that gen_pop_T0 uses a zero-extending load. */ gen_op_jmp_v(s->T0); gen_bnd_jmp(s); - gen_jr(s, s->T0); + s->base.is_jmp = DISAS_JUMP; break; case 0xca: /* lret im */ val = x86_ldsw_code(env, s); @@ -8811,6 +8810,9 @@ static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) gen_update_eip_cur(dc); gen_eob_inhibit_irq(dc, true); break; + case DISAS_JUMP: + gen_jr(dc); + break; default: g_assert_not_reached(); } From patchwork Tue Sep 6 10:09:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603007 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4424307mae; Tue, 6 Sep 2022 04:09:28 -0700 (PDT) X-Google-Smtp-Source: AA6agR4+n3/kcqOq+3xAJzD3nYA25KhLQ/dLcB1fy9bRPc1VPEceVX6+ttNi7UcGSlNkiH3lKcxe X-Received: by 2002:a05:620a:600f:b0:6bc:612f:a0a6 with SMTP id dw15-20020a05620a600f00b006bc612fa0a6mr35147211qkb.497.1662462568522; Tue, 06 Sep 2022 04:09:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662462568; cv=none; d=google.com; s=arc-20160816; b=Gh87vMvwqTCV1ba41UH7HgYhIQMEGUP8OeseXBKT8TbqmY8pC4cvjz/GAGlU5MywPU Yg2aUxhoTGKD7sy9smXmZEat4HtYEbcSoXoe3Q58x2wDE01NTHjlxo2A+B+F8rEnsVoG d2RCrHZRg6L9QdQY/Oc8RMVn3WUNeKd+aqLsV4e32ulu51fVOnYyvz27IDQ0oxoUWnd4 ykUvFA41Aidpmf/aytYkBK1TqxAMIXLMd96wYMofIn5HixjcKXe2aALi+h3whmrv0s92 VeKmKtsG0VD/nxlt3ef5YHmdtIpk9YlwArF9rXMePJWwaI8n99pVBnDW6DwyplBQE1IG KizQ== ARC-Message-Signature: i=1; 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/helper.h | 2 +- target/i386/tcg/seg_helper.c | 6 ++---- target/i386/tcg/translate.c | 3 ++- 3 files changed, 5 insertions(+), 6 deletions(-) diff --git a/target/i386/helper.h b/target/i386/helper.h index ac3b4d1ee3..39a3c24182 100644 --- a/target/i386/helper.h +++ b/target/i386/helper.h @@ -37,7 +37,7 @@ DEF_HELPER_2(lldt, void, env, int) DEF_HELPER_2(ltr, void, env, int) DEF_HELPER_3(load_seg, void, env, int, int) DEF_HELPER_4(ljmp_protected, void, env, int, tl, tl) -DEF_HELPER_5(lcall_real, void, env, int, tl, int, int) +DEF_HELPER_5(lcall_real, void, env, i32, i32, int, i32) DEF_HELPER_5(lcall_protected, void, env, int, tl, int, tl) DEF_HELPER_2(iret_real, void, env, int) DEF_HELPER_3(iret_protected, void, env, int, int) diff --git a/target/i386/tcg/seg_helper.c b/target/i386/tcg/seg_helper.c index bffd82923f..539189b4d1 100644 --- a/target/i386/tcg/seg_helper.c +++ b/target/i386/tcg/seg_helper.c @@ -1504,14 +1504,12 @@ void helper_ljmp_protected(CPUX86State *env, int new_cs, target_ulong new_eip, } /* real mode call */ -void helper_lcall_real(CPUX86State *env, int new_cs, target_ulong new_eip1, - int shift, int next_eip) +void helper_lcall_real(CPUX86State *env, uint32_t new_cs, uint32_t new_eip, + int shift, uint32_t next_eip) { - int new_eip; uint32_t esp, esp_mask; target_ulong ssp; - new_eip = new_eip1; esp = env->regs[R_ESP]; esp_mask = get_sp_mask(env->segs[R_SS].flags); ssp = env->segs[R_SS].base; diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 1997f8d291..427ee72442 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -5302,7 +5302,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) tcg_const_tl(s->pc - s->cs_base)); } else { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); - gen_helper_lcall_real(cpu_env, s->tmp2_i32, s->T1, + tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); + gen_helper_lcall_real(cpu_env, s->tmp2_i32, s->tmp3_i32, tcg_const_i32(dflag - 1), tcg_const_i32(s->pc - s->cs_base)); } From patchwork Tue Sep 6 10:09:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602996 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4408234mae; Tue, 6 Sep 2022 03:49:26 -0700 (PDT) X-Google-Smtp-Source: AA6agR5Znib6X+0qFKrIbe/BT3Oh9+dROBLmt/KWeizf3Jhc96YQ2lixQUT9mGkN2l8qG6PKI7mv X-Received: by 2002:ac8:5fc1:0:b0:344:53f9:1871 with SMTP id k1-20020ac85fc1000000b0034453f91871mr41937066qta.448.1662461365918; Tue, 06 Sep 2022 03:49:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662461365; cv=none; d=google.com; s=arc-20160816; b=m+SmEzSWfGVOMKOM4Z6uqxws4BUwDDc9WxcpJ+R7pFRTVYpP7wssHaMpS8dkeXYXOJ gMN5YDklz/2a2GIjye63ElXHBrlhzijNYWAlGmjx5q7LzoFofdorC4xLEpvepHuuQKjq O19MQ/N11BguPCFllqoAwAjE6EXJwW/HG/wNGPKMIACvrNGE0WO9uSONcy1lY/HSUK3B wTEmKFTKnEd69bVS6nM2GDP5RsR+pPq3+9Xg+oGigbuMBrNYKm/XND8f5xc2aJncxSEO GGeJzZwVFcFpMNH3jh98TRq17v3ZVqBK/1O7YX1RtBXIDtJro9ka9c8FDU6cd0s9spIk u9Sg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DsiG/W3NC5KvRWq7OQV8rlvT3xeYxHGERpFwH0qGMXk=; b=wzAgoVYeTXujax4EUnq7Eir5f/b3W16saN2WfcpLVK2vS69JF87G4OpGdZ5Hkjf2GW EFuryqTZdzxLoBruT/tW2sT5ZAulWSAnuOFlblaCvt6C9fZyX1zOo8Jj8acZBgHTw1T5 HVJdPwDhns86FQqzBOG0nI6GYK0Bfp0tAnSLWRlsG197LYj8oiVvtUMOzmffOHBHOgpn Xr8iPOQvDu74UkzOudM8imnC6PNp6nTUQ7D2MEeSwywPOPfVKKl3WdT1EG26zS9jx6ap R7ea4F7mo44yEldgncq/FiGfo+PTTZvcirH3tbp8gt37cU+lkdkpHJ5T5grQ2E533rEC zLHQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KlfRgner; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Use tcg_constant_* in adjacent code where convenient. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 44 +++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 21 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 427ee72442..527fb79895 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -541,6 +541,16 @@ static TCGv_i32 cur_insn_len_i32(DisasContext *s) return tcg_constant_i32(cur_insn_len(s)); } +static TCGv_i32 eip_next_i32(DisasContext *s) +{ + return tcg_constant_i32(s->pc - s->cs_base); +} + +static TCGv eip_next_tl(DisasContext *s) +{ + return tcg_constant_tl(s->pc - s->cs_base); +} + /* Compute SEG:REG into A0. SEG is selected from the override segment (OVR_SEG) and the default segment (DEF_SEG). OVR_SEG may be -1 to indicate no override. */ @@ -1213,12 +1223,9 @@ static void gen_bpt_io(DisasContext *s, TCGv_i32 t_port, int ot) /* user-mode cpu should not be in IOBPT mode */ g_assert_not_reached(); #else - TCGv_i32 t_size = tcg_const_i32(1 << ot); - TCGv t_next = tcg_const_tl(s->pc - s->cs_base); - + TCGv_i32 t_size = tcg_constant_i32(1 << ot); + TCGv t_next = eip_next_tl(s); gen_helper_bpt_io(cpu_env, t_port, t_size, t_next); - tcg_temp_free_i32(t_size); - tcg_temp_free(t_next); #endif /* CONFIG_USER_ONLY */ } } @@ -5280,9 +5287,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (dflag == MO_16) { tcg_gen_ext16u_tl(s->T0, s->T0); } - next_eip = s->pc - s->cs_base; - tcg_gen_movi_tl(s->T1, next_eip); - gen_push_v(s, s->T1); + gen_push_v(s, eip_next_tl(s)); gen_op_jmp_v(s->T0); gen_bnd_jmp(s); s->base.is_jmp = DISAS_JUMP; @@ -5298,14 +5303,14 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_lcall_protected(cpu_env, s->tmp2_i32, s->T1, - tcg_const_i32(dflag - 1), - tcg_const_tl(s->pc - s->cs_base)); + tcg_constant_i32(dflag - 1), + eip_next_tl(s)); } else { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_lcall_real(cpu_env, s->tmp2_i32, s->tmp3_i32, - tcg_const_i32(dflag - 1), - tcg_const_i32(s->pc - s->cs_base)); + tcg_constant_i32(dflag - 1), + eip_next_i32(s)); } s->base.is_jmp = DISAS_JUMP; break; @@ -5328,7 +5333,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (PE(s) && !VM86(s)) { tcg_gen_trunc_tl_i32(s->tmp2_i32, s->T0); gen_helper_ljmp_protected(cpu_env, s->tmp2_i32, s->T1, - tcg_const_tl(s->pc - s->cs_base)); + eip_next_tl(s)); } else { gen_op_movl_seg_T0_vm(s, R_CS); gen_op_jmp_v(s->T1); @@ -6819,8 +6824,8 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_helper_iret_real(cpu_env, tcg_const_i32(dflag - 1)); } else { - gen_helper_iret_protected(cpu_env, tcg_const_i32(dflag - 1), - tcg_const_i32(s->pc - s->cs_base)); + gen_helper_iret_protected(cpu_env, tcg_constant_i32(dflag - 1), + eip_next_i32(s)); } set_cc_op(s, CC_OP_EFLAGS); s->base.is_jmp = DISAS_EOB_ONLY; @@ -6832,15 +6837,13 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } else { tval = (int16_t)insn_get(env, s, MO_16); } - next_eip = s->pc - s->cs_base; - tval += next_eip; + tval += s->pc - s->cs_base; if (dflag == MO_16) { tval &= 0xffff; } else if (!CODE64(s)) { tval &= 0xffffffff; } - tcg_gen_movi_tl(s->T0, next_eip); - gen_push_v(s, s->T0); + gen_push_v(s, eip_next_tl(s)); gen_bnd_jmp(s); gen_jmp(s, tval); } @@ -7374,8 +7377,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) TCGLabel *l1, *l2, *l3; tval = (int8_t)insn_get(env, s, MO_8); - next_eip = s->pc - s->cs_base; - tval += next_eip; + tval += s->pc - s->cs_base; if (dflag == MO_16) { tval &= 0xffff; } From patchwork Tue Sep 6 10:09:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603023 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4441047mae; 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Tue, 06 Sep 2022 03:09:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 16/23] target/i386: Use DISAS_TOO_MANY to exit after gen_io_start Date: Tue, 6 Sep 2022 11:09:25 +0100 Message-Id: <20220906100932.343523-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906100932.343523-1-richard.henderson@linaro.org> References: <20220906100932.343523-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We can set is_jmp early, using only one if, and let that be overwritten by gen_repz_* etc. Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 42 +++++++++---------------------------- 1 file changed, 10 insertions(+), 32 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 527fb79895..cedc195837 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -5605,14 +5605,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); + s->base.is_jmp = DISAS_TOO_MANY; } gen_helper_rdrand(s->T0, cpu_env); rm = (modrm & 7) | REX_B(s); gen_op_mov_reg_v(s, dflag, rm, s->T0); set_cc_op(s, CC_OP_EFLAGS); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } break; default: @@ -6658,15 +6656,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); + s->base.is_jmp = DISAS_TOO_MANY; } if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { gen_repz_ins(s, ot); - /* jump generated by gen_repz_ins */ } else { gen_ins(s, ot); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } } break; case 0x6e: /* outsS */ @@ -6679,15 +6674,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); + s->base.is_jmp = DISAS_TOO_MANY; } if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { gen_repz_outs(s, ot); - /* jump generated by gen_repz_outs */ } else { gen_outs(s, ot); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } } break; @@ -6704,13 +6696,11 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); + s->base.is_jmp = DISAS_TOO_MANY; } gen_helper_in_func(ot, s->T1, s->tmp2_i32); gen_op_mov_reg_v(s, ot, R_EAX, s->T1); gen_bpt_io(s, s->tmp2_i32, ot); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } break; case 0xe6: case 0xe7: @@ -6722,14 +6712,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); + s->base.is_jmp = DISAS_TOO_MANY; } gen_op_mov_v_reg(s, ot, s->T1, R_EAX); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32); gen_bpt_io(s, s->tmp2_i32, ot); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } break; case 0xec: case 0xed: @@ -6741,13 +6729,11 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); + s->base.is_jmp = DISAS_TOO_MANY; } gen_helper_in_func(ot, s->T1, s->tmp2_i32); gen_op_mov_reg_v(s, ot, R_EAX, s->T1); gen_bpt_io(s, s->tmp2_i32, ot); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } break; case 0xee: case 0xef: @@ -6759,14 +6745,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); + s->base.is_jmp = DISAS_TOO_MANY; } gen_op_mov_v_reg(s, ot, s->T1, R_EAX); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32); gen_bpt_io(s, s->tmp2_i32, ot); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } break; /************************/ @@ -7432,11 +7416,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_update_eip_cur(s); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); + s->base.is_jmp = DISAS_TOO_MANY; } gen_helper_rdtsc(cpu_env); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } break; case 0x133: /* rdpmc */ gen_update_cc_op(s); @@ -7893,11 +7875,9 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_update_eip_cur(s); if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); + s->base.is_jmp = DISAS_TOO_MANY; } gen_helper_rdtscp(cpu_env); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } break; default: @@ -8261,6 +8241,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { gen_io_start(); + s->base.is_jmp = DISAS_TOO_MANY; } if (b & 2) { gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg); @@ -8271,9 +8252,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) gen_svm_check_intercept(s, SVM_EXIT_READ_CR0 + reg); gen_helper_read_crN(s->T0, cpu_env, tcg_constant_i32(reg)); gen_op_mov_reg_v(s, ot, rm, s->T0); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_jmp(s, s->pc - s->cs_base); - } } break; From patchwork Tue Sep 6 10:09:26 2022 Content-Type: text/plain; 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The jmp jb insn was missing a mask for CODE32. Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 57 ++++++++++++++++++------------------- 1 file changed, 27 insertions(+), 30 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index cedc195837..07c7764649 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -226,6 +226,7 @@ static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s); static void gen_jmp(DisasContext *s, target_ulong eip); static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); +static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num); static void gen_op(DisasContext *s1, int op, MemOp ot, int d); static void gen_exception_gpf(DisasContext *s); @@ -1173,7 +1174,7 @@ static TCGLabel *gen_jz_ecx_string(DisasContext *s) TCGLabel *l2 = gen_new_label(); gen_op_jnz_ecx(s, s->aflag, l1); gen_set_label(l2); - gen_jmp_tb(s, s->pc - s->cs_base, 1); + gen_jmp_rel(s, MO_32, 0, 1); gen_set_label(l1); return l2; } @@ -2756,6 +2757,18 @@ static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num) } } +static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num) +{ + target_ulong dest = s->pc - s->cs_base + diff; + + if (ot == MO_16) { + dest &= 0xffff; + } else if (!CODE64(s)) { + dest &= 0xffffffff; + } + gen_jmp_tb(s, dest, tb_num); +} + static void gen_jmp(DisasContext *s, target_ulong eip) { gen_jmp_tb(s, eip, 0); @@ -6816,20 +6829,12 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; case 0xe8: /* call im */ { - if (dflag != MO_16) { - tval = (int32_t)insn_get(env, s, MO_32); - } else { - tval = (int16_t)insn_get(env, s, MO_16); - } - tval += s->pc - s->cs_base; - if (dflag == MO_16) { - tval &= 0xffff; - } else if (!CODE64(s)) { - tval &= 0xffffffff; - } + int diff = (dflag != MO_16 + ? (int32_t)insn_get(env, s, MO_32) + : (int16_t)insn_get(env, s, MO_16)); gen_push_v(s, eip_next_tl(s)); gen_bnd_jmp(s); - gen_jmp(s, tval); + gen_jmp_rel(s, dflag, diff, 0); } break; case 0x9a: /* lcall im */ @@ -6847,19 +6852,13 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } goto do_lcall; case 0xe9: /* jmp im */ - if (dflag != MO_16) { - tval = (int32_t)insn_get(env, s, MO_32); - } else { - tval = (int16_t)insn_get(env, s, MO_16); + { + int diff = (dflag != MO_16 + ? (int32_t)insn_get(env, s, MO_32) + : (int16_t)insn_get(env, s, MO_16)); + gen_bnd_jmp(s); + gen_jmp_rel(s, dflag, diff, 0); } - tval += s->pc - s->cs_base; - if (dflag == MO_16) { - tval &= 0xffff; - } else if (!CODE64(s)) { - tval &= 0xffffffff; - } - gen_bnd_jmp(s); - gen_jmp(s, tval); break; case 0xea: /* ljmp im */ { @@ -6876,12 +6875,10 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } goto do_ljmp; case 0xeb: /* jmp Jb */ - tval = (int8_t)insn_get(env, s, MO_8); - tval += s->pc - s->cs_base; - if (dflag == MO_16) { - tval &= 0xffff; + { + int diff = (int8_t)insn_get(env, s, MO_8); + gen_jmp_rel(s, dflag, diff, 0); } - gen_jmp(s, tval); break; case 0x70 ... 0x7f: /* jcc Jb */ tval = (int8_t)insn_get(env, s, MO_8); From patchwork Tue Sep 6 10:09:27 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603027 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4449005mae; Tue, 6 Sep 2022 04:45:48 -0700 (PDT) X-Google-Smtp-Source: AA6agR7c1fuRc0QVY1YfAS/Z+SRj+4lMbRN+rqjoE5vRUs+d6P/AXdPjePoqQdQ+fYdnnoNcLmS4 X-Received: by 2002:a05:620a:170c:b0:6bb:208c:d276 with SMTP id az12-20020a05620a170c00b006bb208cd276mr35591391qkb.539.1662464748468; Tue, 06 Sep 2022 04:45:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662464748; cv=none; d=google.com; s=arc-20160816; b=wXWM/QNF89XCVdNT6cd7+CeFuFyvjc8JRhEjYM+Jp05Or6EzpPmhWaVTlH8ToK0gqC gra1ovq+i4RCnEFeEs//BF1YO5qHEnQtojmY4QnJtQjfUADZ/91LDOSfP+Ih4RHsRfk9 IpyN1opL4S8f/lsCsr0gHh7BOg7fiRHpHsS0Eml1Hw418ARe3NDvi14Z284uDj2CcaZd T9pxs2yQwbB6L20rRMPAl0v5+WyJc272eBmID+wgVztKU6AHQjItTmyCox+TeB9P6Msz FoQanQhnx8A69esfNeaEcfgx4cDUQ+wlT5YSd6qaw02ujbWCzcvRdmVaK/23NYi0u2df E6MA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+Nxeige1gsl6QD9Ah+wLZGOyW7/vtIOclomTIADO4Ks=; b=SrOvXh4y6oYtl2YMGm6kYBIL3dmxFMVwPtEmN56tQpJ+Dwr+jG2ehAgRz0VSlg/yRp YJDANFaTbNLfjOL9UrwUAAn27OdX1lQJeBD1MlKXY/FHbO72kdfZOAmeu2BQK8/14CQ3 GsdRn6sy0/6Y3FC3DSr1EA4fJgyMdfbU4GZf1a5n8zJYVkWWPnQhcgmFe+8zI+5B34Dm IYCYQISqPG5hRjKwzg/q5fRkGV15I/56KsLf0BKajwlA0nZUGzrlcwCNf1SQxE4e7gh1 Emt3K7NdpJtRAWdyauzH05ddXBZsqEtlDZF7fkV+q+RR8+XNrQXWNqcEzZsGTE9bze4a aKNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UpR8njbH; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 21 ++++++--------------- 1 file changed, 6 insertions(+), 15 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 07c7764649..fdd17c3cf3 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -7355,24 +7355,18 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0xe2: /* loop */ case 0xe3: /* jecxz */ { - TCGLabel *l1, *l2, *l3; - - tval = (int8_t)insn_get(env, s, MO_8); - tval += s->pc - s->cs_base; - if (dflag == MO_16) { - tval &= 0xffff; - } + TCGLabel *l1, *l2; + int diff = (int8_t)insn_get(env, s, MO_8); l1 = gen_new_label(); l2 = gen_new_label(); - l3 = gen_new_label(); gen_update_cc_op(s); b &= 3; switch(b) { case 0: /* loopnz */ case 1: /* loopz */ gen_op_add_reg_im(s, s->aflag, R_ECX, -1); - gen_op_jz_ecx(s, s->aflag, l3); + gen_op_jz_ecx(s, s->aflag, l2); gen_jcc1(s, (JCC_Z << 1) | (b ^ 1), l1); break; case 2: /* loop */ @@ -7385,14 +7379,11 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) break; } - gen_set_label(l3); - gen_update_eip_next(s); - tcg_gen_br(l2); + gen_set_label(l2); + gen_jmp_rel(s, MO_32, 0, 1); gen_set_label(l1); - gen_jmp_im(s, tval); - gen_set_label(l2); - s->base.is_jmp = DISAS_EOB_ONLY; + gen_jmp_rel(s, dflag, diff, 0); } break; case 0x130: /* wrmsr */ From patchwork Tue Sep 6 10:09:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603004 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4415370mae; Tue, 6 Sep 2022 04:00:34 -0700 (PDT) X-Google-Smtp-Source: AA6agR7yxjsr/NjhTcQnmZkiAyAxNSZ80mOKOrktBRDMIF4OOV3YypOpTUgC9p0deerz8K9twcWG X-Received: by 2002:a05:622a:14cd:b0:344:6cfa:42f9 with SMTP id u13-20020a05622a14cd00b003446cfa42f9mr43256122qtx.147.1662462034852; Tue, 06 Sep 2022 04:00:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662462034; cv=none; d=google.com; s=arc-20160816; b=BI69AsAQzKUymkjb5oIvxHHJg704F2qatUSCzMnairg0qIIOLpQDXUavXsOMRUtvyU NYoV8TadrmzIqURK++y5sRhOmZWQ+DPkLjUZbCCRelZag3lRM/sw58fa/N4QteU4D2Cg zOoNI+DlPR0enPV01Aslj3wLxog9yta4EZZEqz8kVW+BE7jzM+CEtPsYzl732FJsnAlP nvfvt8kron7wJHRgv+ALnv5ReA8sTa9MkdxaXuvr0LDaSDnUaFmo37bPoGt01ADaNv/n q1uylaAcimA+zFYhOukeey8S9fKNNOePe/OhdGZPC1g5OmUqXtyaTWD2pwkyUFKfAYVi wkaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rSER7sme+GIaasRDe61/7EyMKFpjNEQVvBAOzaCcze4=; b=fwgHfIAYJvf9TzJ1JP4QCS3VcBamuwpTdjf+127KQxcIZZXRSikFQb64Wf4OAjZwXI I1zPe6C930+thkjjJuD0n6nZN0Ass74cbEDuMOLLYtbJBK2Hp+VgrxGytneHQyUO/rfv s4qQebH72ZYMwH7ktBd65cMYYiqJOtXCUWtwkbEL94+WalogQGmIb4q3QKpqOuoyRPt9 WxxEpaWEplUAZDWKvHU89CiAJ5BH6k2RfM8MaZHdYDO2HCrQWqcanZp45DVbOyd2qqfA vKVeGr207pcfHUE43+Sl1l/eIy337TUZit7Mwrgfa3uKqAPODahEOZ3L2QbriKSV+9mj 1+BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aNUax3CR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 06 Sep 2022 03:09:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 19/23] target/i386: Use gen_jmp_rel for gen_jcc Date: Tue, 6 Sep 2022 11:09:28 +0100 Message-Id: <20220906100932.343523-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906100932.343523-1-richard.henderson@linaro.org> References: <20220906100932.343523-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 57 ++++++++++++------------------------- 1 file changed, 18 insertions(+), 39 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index fdd17c3cf3..e27f36e4e9 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -2373,32 +2373,14 @@ static void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) } } -static inline void gen_jcc(DisasContext *s, int b, - target_ulong val, target_ulong next_eip) +static void gen_jcc(DisasContext *s, MemOp ot, int b, int diff) { - TCGLabel *l1, *l2; + TCGLabel *l1 = gen_new_label(); - if (s->jmp_opt) { - l1 = gen_new_label(); - gen_jcc1(s, b, l1); - - gen_goto_tb(s, 0, next_eip); - - gen_set_label(l1); - gen_goto_tb(s, 1, val); - } else { - l1 = gen_new_label(); - l2 = gen_new_label(); - gen_jcc1(s, b, l1); - - gen_jmp_im(s, next_eip); - tcg_gen_br(l2); - - gen_set_label(l1); - gen_jmp_im(s, val); - gen_set_label(l2); - gen_eob(s); - } + gen_jcc1(s, b, l1); + gen_jmp_rel(s, ot, 0, 1); + gen_set_label(l1); + gen_jmp_rel(s, ot, diff, 0); } static void gen_cmovcc1(CPUX86State *env, DisasContext *s, MemOp ot, int b, @@ -4721,7 +4703,6 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) int shift; MemOp ot, aflag, dflag; int modrm, reg, rm, mod, op, opreg, val; - target_ulong next_eip, tval; bool orig_cc_op_dirty = s->cc_op_dirty; CCOp orig_cc_op = s->cc_op; @@ -6881,22 +6862,20 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } break; case 0x70 ... 0x7f: /* jcc Jb */ - tval = (int8_t)insn_get(env, s, MO_8); - goto do_jcc; + { + int diff = (int8_t)insn_get(env, s, MO_8); + gen_bnd_jmp(s); + gen_jcc(s, dflag, b, diff); + } + break; case 0x180 ... 0x18f: /* jcc Jv */ - if (dflag != MO_16) { - tval = (int32_t)insn_get(env, s, MO_32); - } else { - tval = (int16_t)insn_get(env, s, MO_16); + { + int diff = (dflag != MO_16 + ? (int32_t)insn_get(env, s, MO_32) + : (int16_t)insn_get(env, s, MO_16)); + gen_bnd_jmp(s); + gen_jcc(s, dflag, b, diff); } - do_jcc: - next_eip = s->pc - s->cs_base; - tval += next_eip; - if (dflag == MO_16) { - tval &= 0xffff; - } - gen_bnd_jmp(s); - gen_jcc(s, b, tval, next_eip); break; case 0x190 ... 0x19f: /* setcc Gv */ From patchwork Tue Sep 6 10:09:29 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603030 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4452946mae; Tue, 6 Sep 2022 04:52:28 -0700 (PDT) X-Google-Smtp-Source: AA6agR46mBTiam5s65pmScXsAMvGhvYW05Sws+PzTEJqM95gjE0XegVNMFC1QDunnSd01fkyv+tI X-Received: by 2002:ad4:5fce:0:b0:4a4:95ad:627a with SMTP id jq14-20020ad45fce000000b004a495ad627amr8567979qvb.28.1662465148258; Tue, 06 Sep 2022 04:52:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662465148; cv=none; d=google.com; s=arc-20160816; b=eActz9wPy6K8w5Ujy0mAS5EcYm8tmQ46KuoA6tbKOuK2Bsy7PjFJLZf0RR/MFkAF2S ENnzsIEqvgN5COAmi5ACAf6SuRoX0tb3Ac4JKMQXiqztRjoEehiFkXX0lLgVuelJYArm AoqNSb6DuAd+BMk0IffkjXJTNp0KIJOOV76NdWIBduaytVtVXX/iu/M0T4LVcwgxvBn2 MZAegmaq8zPMVXiWY/YbOwrtmUGbX2lqCBWrZrhPvBXv4ycLGZAwFRTKL6trofOegtMK hd6aW3P/+fPXZn8RVLoTzf5CYaASPP0Ro1IyGlEZ6TSOSCUOZ4qlO2bPhlUPfchpY1yE 5QhQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=e4npXQ7DLvxtByjVYox+uTI8xWGyZxkDNG6TBVozSlU=; b=YR2Po/4Inl53y4y1AxHo5OMvVPpuj4N2TOYcucgAnPHQhch/zSG4XwXjbM+Ce/fZj9 5a7qr6tp2wMeKd2NMgCvlRg/YDsnXB+0zoX2aKsrKErcvAfW2tFGUt1BJgx8jr6rc0MA xHB5g9+i6Arfv9quPrdlxZQvWQShd6oZ9JTXdl1Z7ZX3pLo4Lk2vHDg11dh8/ve6YwO/ F97PG5WF+leMDy3CrtS6SYp5oWrlsg9+9O7vbLOKIpiz0eZJweEjhZoWeDe3cYxPQdk1 4xUPd/kOFyT8e2xlhx9YHqM61i6hx6SgIVPW4N8Cxq0w7g3uNKlp/7VraArQ+mVLC7Fe igSg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z83udYuj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- target/i386/tcg/translate.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index e27f36e4e9..7a9e533c6e 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -224,7 +224,6 @@ STUB_HELPER(wrmsr, TCGv_env env) static void gen_eob(DisasContext *s); static void gen_jr(DisasContext *s); -static void gen_jmp(DisasContext *s, target_ulong eip); static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num); static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num); static void gen_op(DisasContext *s1, int op, MemOp ot, int d); @@ -1277,7 +1276,7 @@ static void gen_repz(DisasContext *s, MemOp ot, if (s->repz_opt) { gen_op_jz_ecx(s, s->aflag, l2); } - gen_jmp(s, s->base.pc_next - s->cs_base); + gen_jmp_rel(s, MO_32, -cur_insn_len(s), 0); } #define GEN_REPZ(op) \ @@ -1297,7 +1296,7 @@ static void gen_repz2(DisasContext *s, MemOp ot, int nz, if (s->repz_opt) { gen_op_jz_ecx(s, s->aflag, l2); } - gen_jmp(s, s->base.pc_next - s->cs_base); + gen_jmp_rel(s, MO_32, -cur_insn_len(s), 0); } #define GEN_REPZ2(op) \ @@ -2751,11 +2750,6 @@ static void gen_jmp_rel(DisasContext *s, MemOp ot, int diff, int tb_num) gen_jmp_tb(s, dest, tb_num); } -static void gen_jmp(DisasContext *s, target_ulong eip) -{ - gen_jmp_tb(s, eip, 0); -} - static inline void gen_ldq_env_A0(DisasContext *s, int offset) { tcg_gen_qemu_ld_i64(s->tmp1_i64, s->A0, s->mem_index, MO_LEUQ); From patchwork Tue Sep 6 10:09:30 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603000 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4412585mae; Tue, 6 Sep 2022 03:56:40 -0700 (PDT) X-Google-Smtp-Source: AA6agR7Ky6e9LQFjxgDOh503gaKUs1qDd9/guq6M4mYzh4T3DO6tb2EeBmHQ12DfGl5+/tSufSM/ X-Received: by 2002:a05:6214:c2b:b0:476:813a:b173 with SMTP id a11-20020a0562140c2b00b00476813ab173mr43570840qvd.31.1662461800495; Tue, 06 Sep 2022 03:56:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662461800; cv=none; d=google.com; s=arc-20160816; b=moaF8ca6KprgujDg9dN5Mjjnj5mHmrAr4hyBg3/5fsS74mFf9XtbGrXS2MqJMhwhBs q04SXsM66Tp6cxeqQLsSurAJmV7/CRPJjtYrjoMCqG+zWih+UERDAQlpphqs6GZ1ZD9q TKNn98PCewkjbnrgLRK5GZZuMbO3dcrVOdi7thPX3mFRSLtgt3VVd9yCSnOVI9WkyW8w Ur67IOoNpiwkGbyO3eZqnf4CsDAhZYiyzRCNFgWT1SjMLudUFgg3aSw6nSGGiqHURwh5 QiqBL2Qbk54s3QVQ4Bd9Ay7nr2+hE6nIcTKkDq/IQUQOjWuTkgZ82endJcRE7UR3xDUt 4wjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=sStumSItgDeXZaFuVPIAQyYganzdZgHWxSiIZOoEM0E=; b=dbpKHFMeuS/sdGFqYJbCCgwxYC0BtSUwV8nd/NevO//j373yvekvGKsKQBb0q+K4FV aXo6I5lAUfn8qakzc1EYfgHswVUnL9zOdfEhpeHpK1sveBPrx13Z6PSAvAVc1+vm9iDU d3VBlw78zS99A8GRZgKfwthAbd+ALFw/nShXy5aQHrpWD/jWUiwjjRXLiuJdEYZAlJ90 heg00nDhnrDG+e7qcpHhy0+wC9PLfn6YnE9TEnaSM90OcMBxQ3y8DeWUCOWBf5T6ydN2 aD0LsKvuQAInMBAElbhQa3TFOTdHur8PvMfsBSzreBhOATtHqn5qd+yOeKCf2dkP7zum MhkQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Fwy0ioLK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Paolo Bonzini --- target/i386/tcg/translate.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 7a9e533c6e..97a5f7e432 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -8740,6 +8740,9 @@ static void i386_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) case DISAS_NORETURN: break; case DISAS_TOO_MANY: + gen_update_cc_op(dc); + gen_jmp_rel(dc, MO_32, 0, 0); + break; case DISAS_EOB_NEXT: gen_update_cc_op(dc); gen_update_eip_cur(dc); From patchwork Tue Sep 6 10:09:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 603011 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4427160mae; Tue, 6 Sep 2022 04:13:16 -0700 (PDT) X-Google-Smtp-Source: AA6agR6si/LUV+0eWQH6m08nRYKfMNAEHyJA3h5WII1WpzEwHplvH1UDDbYv95jGOYMSYcnPhhI5 X-Received: by 2002:a05:622a:44f:b0:343:499:e77c with SMTP id o15-20020a05622a044f00b003430499e77cmr41865626qtx.129.1662462796377; Tue, 06 Sep 2022 04:13:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662462796; cv=none; d=google.com; s=arc-20160816; b=AzjBOkBc4J988kF1AAFXSVhXpeG1ZFAyJdHc1LKED6UCXZvcrCIcaAZnZqUtSbyhG/ 3TeOn4DZQb4rFS67dbAOWM98RkUOFnm74ttgZo4W0isFHfD3oY7RIFIMsfbpYKm2e1Uk 4edCOP1mDNQ6eJnlseLTbtgBd3vyaMQwljcFYsfwd+F8byZYU+MpG9nopvlEg4XmosWk Kqn3HR6YaTzAXJY0pTslBE3GabTyPoriLb59AGM2j/9oMErKy0JnhG35y1BRaDKu+pim Xn+Dx7Z4TEG1VbRsanECpT3ZwB2C+EcSwPNUiuZ+AerbX+xiPNInqmIc8RFjLrO3FC5d xKJw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nVh1xXH3Saj+Yr5nLG8CgQIGecm00fAvyeGV47OTtj0=; b=L8h6YMtPY5v1khRjoLdMBzva/0sZWw7d6cR/Kt8k1q6u/5NqJBYSfQ5EHquESD1ngc uDuQ94Ae6uZk/WFwE/ugTELDd+sLO0d8jN0sA86oyUO1El0YV7U3Raw8AkFwCmf4Rfps Ys6WA7FJy/D4TZF2ABdLDLZ7u0zTPAXXdhbZexFoDy9Ru2I97U5BL7uEfN2jyajGwwkf vJO8TlM4IhM6CQHcGEfHQizdHXltaEyGIeTvruxzee3hAFLrETmbV7kEuyv2UWmmGTKT htvLsAI20q3mCYg6ncYr8hy1EnIIZdNXoYKrmv1Ec/NuMRMuWCHNjMOej7esGh+eAHZ+ RtYw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XApaAhxu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 06 Sep 2022 03:09:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 22/23] target/i386: Create gen_eip_cur Date: Tue, 6 Sep 2022 11:09:31 +0100 Message-Id: <20220906100932.343523-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906100932.343523-1-richard.henderson@linaro.org> References: <20220906100932.343523-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/i386/tcg/translate.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 97a5f7e432..39bcb7263b 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -516,6 +516,11 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) } } +static TCGv gen_eip_cur(DisasContext *s) +{ + return tcg_constant_tl(s->base.pc_next - s->cs_base); +} + static void gen_jmp_im(DisasContext *s, target_ulong pc) { gen_op_jmp_v(tcg_constant_tl(pc)); @@ -6574,7 +6579,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) offsetof(CPUX86State, segs[R_CS].selector)); tcg_gen_st16_i32(s->tmp2_i32, cpu_env, offsetof(CPUX86State, fpcs)); - tcg_gen_st_tl(tcg_constant_tl(s->base.pc_next - s->cs_base), + tcg_gen_st_tl(gen_eip_cur(s), cpu_env, offsetof(CPUX86State, fpip)); } } From patchwork Tue Sep 6 10:09:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602998 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4411087mae; Tue, 6 Sep 2022 03:54:08 -0700 (PDT) X-Google-Smtp-Source: AA6agR4b2uEcNN+e5akYOKk8vhHSfh95kzWWIpBc88Brw+pg11QPscb25vyIdT7ej6cQ1kd8rLUU X-Received: by 2002:ac8:5e13:0:b0:344:734f:c354 with SMTP id h19-20020ac85e13000000b00344734fc354mr43147245qtx.189.1662461648274; Tue, 06 Sep 2022 03:54:08 -0700 (PDT) ARC-Seal: i=1; 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Tue, 06 Sep 2022 03:09:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: pbonzini@redhat.com Subject: [PATCH v2 23/23] target/i386: Enable TARGET_TB_PCREL Date: Tue, 6 Sep 2022 11:09:32 +0100 Message-Id: <20220906100932.343523-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906100932.343523-1-richard.henderson@linaro.org> References: <20220906100932.343523-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/i386/cpu-param.h | 1 + target/i386/tcg/tcg-cpu.c | 8 ++-- target/i386/tcg/translate.c | 86 ++++++++++++++++++++++++++++++------- 3 files changed, 77 insertions(+), 18 deletions(-) diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h index 9740bd7abd..51a3f153bf 100644 --- a/target/i386/cpu-param.h +++ b/target/i386/cpu-param.h @@ -24,5 +24,6 @@ #endif #define TARGET_PAGE_BITS 12 #define NB_MMU_MODES 3 +#define TARGET_TB_PCREL 1 #endif diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 76989a5a9d..74333247c5 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -49,9 +49,11 @@ static void x86_cpu_exec_exit(CPUState *cs) static void x86_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) { - X86CPU *cpu = X86_CPU(cs); - - cpu->env.eip = tb_pc(tb) - tb->cs_base; + /* The instruction pointer is always up to date with TARGET_TB_PCREL. */ + if (!TARGET_TB_PCREL) { + CPUX86State *env = cs->env_ptr; + env->eip = tb_pc(tb) - tb->cs_base; + } } #ifndef CONFIG_USER_ONLY diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 39bcb7263b..249309ddbc 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -64,6 +64,7 @@ /* global register indexes */ static TCGv cpu_cc_dst, cpu_cc_src, cpu_cc_src2; +static TCGv cpu_eip; static TCGv_i32 cpu_cc_op; static TCGv cpu_regs[CPU_NB_REGS]; static TCGv cpu_seg_base[6]; @@ -77,6 +78,7 @@ typedef struct DisasContext { target_ulong pc; /* pc = eip + cs_base */ target_ulong cs_base; /* base of CS segment */ + target_ulong pc_save; MemOp aflag; MemOp dflag; @@ -481,7 +483,7 @@ static void gen_add_A0_im(DisasContext *s, int val) static inline void gen_op_jmp_v(TCGv dest) { - tcg_gen_st_tl(dest, cpu_env, offsetof(CPUX86State, eip)); + tcg_gen_mov_tl(cpu_eip, dest); } static inline @@ -516,24 +518,36 @@ static inline void gen_op_st_rm_T0_A0(DisasContext *s, int idx, int d) } } -static TCGv gen_eip_cur(DisasContext *s) +static void gen_jmp_im(DisasContext *s, target_ulong eip) { - return tcg_constant_tl(s->base.pc_next - s->cs_base); -} - -static void gen_jmp_im(DisasContext *s, target_ulong pc) -{ - gen_op_jmp_v(tcg_constant_tl(pc)); + if (TARGET_TB_PCREL) { + target_ulong eip_save = s->pc_save - s->cs_base; + tcg_gen_addi_tl(cpu_eip, cpu_eip, eip - eip_save); + } else { + tcg_gen_movi_tl(cpu_eip, eip); + } } static void gen_update_eip_cur(DisasContext *s) { gen_jmp_im(s, s->base.pc_next - s->cs_base); + s->pc_save = s->base.pc_next; } static void gen_update_eip_next(DisasContext *s) { gen_jmp_im(s, s->pc - s->cs_base); + s->pc_save = s->pc; +} + +static TCGv gen_eip_cur(DisasContext *s) +{ + if (TARGET_TB_PCREL) { + gen_update_eip_cur(s); + return cpu_eip; + } else { + return tcg_constant_tl(s->base.pc_next - s->cs_base); + } } static int cur_insn_len(DisasContext *s) @@ -548,12 +562,25 @@ static TCGv_i32 cur_insn_len_i32(DisasContext *s) static TCGv_i32 eip_next_i32(DisasContext *s) { - return tcg_constant_i32(s->pc - s->cs_base); + if (TARGET_TB_PCREL) { + TCGv_i32 ret = tcg_temp_new_i32(); + tcg_gen_trunc_tl_i32(ret, cpu_eip); + tcg_gen_addi_i32(ret, ret, s->pc - s->pc_save); + return ret; + } else { + return tcg_constant_i32(s->pc - s->cs_base); + } } static TCGv eip_next_tl(DisasContext *s) { - return tcg_constant_tl(s->pc - s->cs_base); + if (TARGET_TB_PCREL) { + TCGv ret = tcg_temp_new(); + tcg_gen_addi_tl(ret, cpu_eip, s->pc - s->pc_save); + return ret; + } else { + return tcg_constant_tl(s->pc - s->cs_base); + } } /* Compute SEG:REG into A0. SEG is selected from the override segment @@ -2252,7 +2279,12 @@ static TCGv gen_lea_modrm_1(DisasContext *s, AddressParts a) ea = cpu_regs[a.base]; } if (!ea) { - tcg_gen_movi_tl(s->A0, a.disp); + if (TARGET_TB_PCREL && a.base == -2) { + /* With cpu_eip ~= pc_save, the expression is pc-relative. */ + tcg_gen_addi_tl(s->A0, cpu_eip, a.disp - s->pc_save); + } else { + tcg_gen_movi_tl(s->A0, a.disp); + } ea = s->A0; } else if (a.disp != 0) { tcg_gen_addi_tl(s->A0, ea, a.disp); @@ -2366,8 +2398,13 @@ static void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip) if (translator_use_goto_tb(&s->base, pc)) { /* jump to same page: we can use a direct jump */ - tcg_gen_goto_tb(tb_num); - gen_jmp_im(s, eip); + if (TARGET_TB_PCREL) { + gen_jmp_im(s, eip); + tcg_gen_goto_tb(tb_num); + } else { + tcg_gen_goto_tb(tb_num); + gen_jmp_im(s, eip); + } tcg_gen_exit_tb(s->base.tb, tb_num); s->base.is_jmp = DISAS_NORETURN; } else { @@ -8571,6 +8608,13 @@ void tcg_x86_init(void) [R_EDI] = "edi", [R_EBP] = "ebp", [R_ESP] = "esp", +#endif + }; + static const char eip_name[] = { +#ifdef TARGET_X86_64 + "rip" +#else + "eip" #endif }; static const char seg_base_names[6][8] = { @@ -8597,6 +8641,7 @@ void tcg_x86_init(void) "cc_src"); cpu_cc_src2 = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, cc_src2), "cc_src2"); + cpu_eip = tcg_global_mem_new(cpu_env, offsetof(CPUX86State, eip), eip_name); for (i = 0; i < CPU_NB_REGS; ++i) { cpu_regs[i] = tcg_global_mem_new(cpu_env, @@ -8633,6 +8678,7 @@ static void i386_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cpu) int iopl = (flags >> IOPL_SHIFT) & 3; dc->cs_base = dc->base.tb->cs_base; + dc->pc_save = dc->base.pc_next; dc->flags = flags; #ifndef CONFIG_USER_ONLY dc->cpl = cpl; @@ -8696,9 +8742,14 @@ static void i386_tr_tb_start(DisasContextBase *db, CPUState *cpu) static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) { DisasContext *dc = container_of(dcbase, DisasContext, base); + target_ulong pc_arg = dc->base.pc_next; dc->prev_insn_end = tcg_last_op(); - tcg_gen_insn_start(dc->base.pc_next, dc->cc_op); + if (TARGET_TB_PCREL) { + pc_arg -= dc->cs_base; + pc_arg &= ~TARGET_PAGE_MASK; + } + tcg_gen_insn_start(pc_arg, dc->cc_op); } static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) @@ -8799,7 +8850,12 @@ void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, target_ulong *data) { int cc_op = data[1]; - env->eip = data[0] - tb->cs_base; + + if (TARGET_TB_PCREL) { + env->eip = (env->eip & TARGET_PAGE_MASK) | data[0]; + } else { + env->eip = data[0] - tb->cs_base; + } if (cc_op != CC_OP_DYNAMIC) { env->cc_op = cc_op; }