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[209.51.188.17]) by mx.google.com with ESMTPS id br32-20020a05620a462000b006bb9cfda390si6961388qkb.31.2022.09.06.02.53.21 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 06 Sep 2022 02:53:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dWM4r7tr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:53480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oVVGj-0004G9-Fn for patch@linaro.org; Tue, 06 Sep 2022 05:53:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oVUcJ-0007U4-8C for qemu-devel@nongnu.org; Tue, 06 Sep 2022 05:11:36 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:36733) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oVUcG-0002eX-Ii for qemu-devel@nongnu.org; Tue, 06 Sep 2022 05:11:34 -0400 Received: by mail-wr1-x42c.google.com with SMTP id b17so1087732wrq.3 for ; Tue, 06 Sep 2022 02:11:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date; bh=otYbIH7+XnOzyNNWUPs7TNiTtGs08RctjQezdZ+bWqM=; b=dWM4r7trPT4IwxjICsj5NkvVOKcPxWAjHBdSTS9rudEFqzihHN+O/T9ETra+c7Qko+ lzVUypFevacmG6yutlP+7RgSaoV27wt/k5JOCMfMKOHAuWf53GGqDcq88/NRgQcwhiR0 MSbF+l1jzrNCLv2n+dg5z/pSoHUyDE2EWVt1B+2YMs2fVYQKTSMbK7e6ZER9N/zQKvDw Bab7nfGP1PP1Kte6KcwGnpXiAMVc0gGWIdk75NJpNKZaNwWnXIdfaQMp2nGnZ79UuN7W OIo+IhY246lSQCmIwytzWJd0mwmC2f2nzQuHuVOIU/JONbLMqMbluho7aXyvCEfrrlPj AYoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date; bh=otYbIH7+XnOzyNNWUPs7TNiTtGs08RctjQezdZ+bWqM=; b=MZxvapHtgahD9nXgmKmoI8S8uRkACIkmRA5313Dw9dFw+O3uN//oVSqP/cvQOm5aTX mSK8yDneKnsJhs7vRrNBlUCMI7U0CHLabMjiSui890IUoTnCmhtJ8HXH5osisSDSRkSX cqmog6uJbmQ3Se8E5ABscQpC2AGTUOz8UaRKOuCNj3LJ4y22jy7vRquIwDvWUx+xcAVI GVAZOaoJfM6VE0tMswz3nTS2EVCnQpbe1uhb/zY9cL58x79gf+dd6aBpsUsqYT9L5yIV wJbOp3Py/5oPn6kJijJEjw5OT+B5xyFDjpiU/Ux20HIvTdKyVXHu+Q4dVsbUC/bsgI/p KXgw== X-Gm-Message-State: ACgBeo0Jo3WOvKU/q7BSmmtAQ/oYNba9NkflX1TS9IHMfGfblRY6DOCe AxY6uzf6XG+z4Yp4A/Z9YDb3tgJO1QJQVNAI X-Received: by 2002:a5d:5847:0:b0:227:595f:de89 with SMTP id i7-20020a5d5847000000b00227595fde89mr10829578wrf.236.1662455490855; Tue, 06 Sep 2022 02:11:30 -0700 (PDT) Received: from localhost.localdomain ([2a02:8084:a5c0:5a80:ba98:3a71:8524:e0b1]) by smtp.gmail.com with ESMTPSA id m64-20020a1c2643000000b003a5ee64cc98sm20094193wmm.33.2022.09.06.02.11.29 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 06 Sep 2022 02:11:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 1/7] accel/tcg: Use bool for page_find_alloc Date: Tue, 6 Sep 2022 10:11:20 +0100 Message-Id: <20220906091126.298041-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906091126.298041-1-richard.henderson@linaro.org> References: <20220906091126.298041-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Bool is more appropriate type for the alloc parameter. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Alex Bennée --- accel/tcg/translate-all.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index f5e8592d4a..d2946f8e59 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -472,7 +472,7 @@ void page_init(void) #endif } -static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) +static PageDesc *page_find_alloc(tb_page_addr_t index, bool alloc) { PageDesc *pd; void **lp; @@ -540,11 +540,11 @@ static PageDesc *page_find_alloc(tb_page_addr_t index, int alloc) static inline PageDesc *page_find(tb_page_addr_t index) { - return page_find_alloc(index, 0); + return page_find_alloc(index, false); } static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, - PageDesc **ret_p2, tb_page_addr_t phys2, int alloc); + PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc); /* In user-mode page locks aren't used; mmap_lock is enough */ #ifdef CONFIG_USER_ONLY @@ -658,7 +658,7 @@ static inline void page_unlock(PageDesc *pd) /* lock the page(s) of a TB in the correct acquisition order */ static inline void page_lock_tb(const TranslationBlock *tb) { - page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], 0); + page_lock_pair(NULL, tb->page_addr[0], NULL, tb->page_addr[1], false); } static inline void page_unlock_tb(const TranslationBlock *tb) @@ -847,7 +847,7 @@ void page_collection_unlock(struct page_collection *set) #endif /* !CONFIG_USER_ONLY */ static void page_lock_pair(PageDesc **ret_p1, tb_page_addr_t phys1, - PageDesc **ret_p2, tb_page_addr_t phys2, int alloc) + PageDesc **ret_p2, tb_page_addr_t phys2, bool alloc) { PageDesc *p1, *p2; tb_page_addr_t page1; @@ -1341,7 +1341,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, * Note that inserting into the hash table first isn't an option, since * we can only insert TBs that are fully initialized. */ - page_lock_pair(&p, phys_pc, &p2, phys_page2, 1); + page_lock_pair(&p, phys_pc, &p2, phys_page2, true); tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK); if (p2) { tb_page_add(p2, tb, 1, phys_page2); @@ -2289,7 +2289,7 @@ void page_set_flags(target_ulong start, target_ulong end, int flags) for (addr = start, len = end - start; len != 0; len -= TARGET_PAGE_SIZE, addr += TARGET_PAGE_SIZE) { - PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, 1); + PageDesc *p = page_find_alloc(addr >> TARGET_PAGE_BITS, true); /* If the write protection bit is set, then we invalidate the code inside. */ From patchwork Tue Sep 6 09:11:21 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602972 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4370496mae; Tue, 6 Sep 2022 02:51:03 -0700 (PDT) X-Google-Smtp-Source: AA6agR6q8HRGmnFm6K32EfW2Ll2yDiVbtBpSFEJwL3sx/FTU7jPXpVP53Gp+swdqJR1b+ZJ9KqCx X-Received: by 2002:a05:622a:104:b0:343:7f18:5142 with SMTP id u4-20020a05622a010400b003437f185142mr42388033qtw.210.1662457863711; Tue, 06 Sep 2022 02:51:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662457863; cv=none; d=google.com; s=arc-20160816; b=ujT5KYL0TlGGzm7k8Wc2gEoRO9f9ncMvabghDUUKRPWNhzChpZOSKWBcbunFvDNGgZ +7/1FW7NVtl0tutm7R1RIaLxG+FzhF0U5fDMVfcoTQZMYEPCFKO0b6dUmrhcS8A0p2U7 DiVuvO/RBL8xoYbu0db/0TBX4L6uc6OiEX9k4mB6XME+MSuEadkqJ3wGtx5dKh4t0u35 bYQiZV5XnFxMBCOyQS+jTxvTm5UsTrTpZ5qIRLyK5gIhD3r3646b8C8I8ppl3phH4jAt RmABS8jVrcof2u3v6n3OXViMuN9eZW7FWyhZbI3+Gz2KQWEqwhan2kvCdVsL+nOUzrIK inzA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=oQjXVWydC6/Y9j167mUwZz3YYHjGsA013pbtkQ/vYzs=; b=yzuhjjLnxgjWGO+j24dhh57l158FwBcrLMOi6l+iFTRqKaGFwbmmXH+dfwMaou69uC eL+l6uuIf7ditiZxAIao/8JLxVHGwXWUBjqND24OUy1DfvzQiul9xHcSR5URjkQYXbAD XW1UjEm2a55rCzib6Q26oDUHI3Zsw7I+wvq1/r3iUb7jihfsy//0ASKBrxx/Vms5iSK2 Y0eXH9i4kmfGuuTF3CDu1AEl79uybcmp+zdIxS1byqWhC+wVGr5Q57vE1z7ZvzITr4VC SVnFTHpMAw4Nu/NkvQWT8kXdeVjHTvEaBcz66fruAlJUhKCXQyijkkrd+KOzNvVdDqcE j2rw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rgI+HDN+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Use the cached host_addr rather than re-computing for the first page. We still need a separate lookup for the second page because it won't be computed for DisasContextBase until the translator actually performs a read from the page. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée --- include/exec/plugin-gen.h | 7 ++++--- accel/tcg/plugin-gen.c | 22 +++++++++++----------- accel/tcg/translator.c | 2 +- 3 files changed, 16 insertions(+), 15 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index f92f169739..5004728c61 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -19,7 +19,8 @@ struct DisasContextBase; #ifdef CONFIG_PLUGIN -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool supress); +bool plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, + bool supress); void plugin_gen_tb_end(CPUState *cpu); void plugin_gen_insn_start(CPUState *cpu, const struct DisasContextBase *db); void plugin_gen_insn_end(void); @@ -48,8 +49,8 @@ static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t size) #else /* !CONFIG_PLUGIN */ -static inline -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool supress) +static inline bool +plugin_gen_tb_start(CPUState *cpu, const struct DisasContextBase *db, bool sup) { return false; } diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 3d0b101e34..80dff68934 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -852,7 +852,8 @@ static void plugin_gen_inject(const struct qemu_plugin_tb *plugin_tb) pr_ops(); } -bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool mem_only) +bool plugin_gen_tb_start(CPUState *cpu, const DisasContextBase *db, + bool mem_only) { bool ret = false; @@ -870,9 +871,9 @@ bool plugin_gen_tb_start(CPUState *cpu, const TranslationBlock *tb, bool mem_onl ret = true; - ptb->vaddr = tb->pc; + ptb->vaddr = db->pc_first; ptb->vaddr2 = -1; - get_page_addr_code_hostp(cpu->env_ptr, tb->pc, &ptb->haddr1); + ptb->haddr1 = db->host_addr[0]; ptb->haddr2 = NULL; ptb->mem_only = mem_only; @@ -898,16 +899,15 @@ void plugin_gen_insn_start(CPUState *cpu, const DisasContextBase *db) * Note that we skip this when haddr1 == NULL, e.g. when we're * fetching instructions from a region not backed by RAM. */ - if (likely(ptb->haddr1 != NULL && ptb->vaddr2 == -1) && - unlikely((db->pc_next & TARGET_PAGE_MASK) != - (db->pc_first & TARGET_PAGE_MASK))) { - get_page_addr_code_hostp(cpu->env_ptr, db->pc_next, - &ptb->haddr2); - ptb->vaddr2 = db->pc_next; - } - if (likely(ptb->vaddr2 == -1)) { + if (ptb->haddr1 == NULL) { + pinsn->haddr = NULL; + } else if (is_same_page(db, db->pc_next)) { pinsn->haddr = ptb->haddr1 + pinsn->vaddr - ptb->vaddr; } else { + if (ptb->vaddr2 == -1) { + ptb->vaddr2 = TARGET_PAGE_ALIGN(db->pc_first); + get_page_addr_code_hostp(cpu->env_ptr, ptb->vaddr2, &ptb->haddr2); + } pinsn->haddr = ptb->haddr2 + pinsn->vaddr - ptb->vaddr2; } } diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index ca8a5f2d83..8e78fd7a9c 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -75,7 +75,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int max_insns, ops->tb_start(db, cpu); tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ - plugin_enabled = plugin_gen_tb_start(cpu, tb, cflags & CF_MEMI_ONLY); + plugin_enabled = plugin_gen_tb_start(cpu, db, cflags & CF_MEMI_ONLY); while (true) { db->num_insns++; From patchwork Tue Sep 6 09:11:22 2022 Content-Type: text/plain; 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We need to recover this value anyway at various points, and it is easier to discard the page offset when it's not needed, which happens naturally via the existing find_page shift. Signed-off-by: Richard Henderson --- accel/tcg/cpu-exec.c | 16 ++++++++-------- accel/tcg/cputlb.c | 3 ++- accel/tcg/translate-all.c | 9 +++++---- 3 files changed, 15 insertions(+), 13 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 5f43b9769a..dd58a144a8 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -174,7 +174,7 @@ struct tb_desc { target_ulong pc; target_ulong cs_base; CPUArchState *env; - tb_page_addr_t phys_page1; + tb_page_addr_t page_addr0; uint32_t flags; uint32_t cflags; uint32_t trace_vcpu_dstate; @@ -186,7 +186,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const struct tb_desc *desc = d; if (tb->pc == desc->pc && - tb->page_addr[0] == desc->phys_page1 && + tb->page_addr[0] == desc->page_addr0 && tb->cs_base == desc->cs_base && tb->flags == desc->flags && tb->trace_vcpu_dstate == desc->trace_vcpu_dstate && @@ -195,8 +195,8 @@ static bool tb_lookup_cmp(const void *p, const void *d) if (tb->page_addr[1] == -1) { return true; } else { - tb_page_addr_t phys_page2; - target_ulong virt_page2; + tb_page_addr_t phys_page1; + target_ulong virt_page1; /* * We know that the first page matched, and an otherwise valid TB @@ -207,9 +207,9 @@ static bool tb_lookup_cmp(const void *p, const void *d) * is different for the new TB. Therefore any exception raised * here by the faulting lookup is not premature. */ - virt_page2 = TARGET_PAGE_ALIGN(desc->pc); - phys_page2 = get_page_addr_code(desc->env, virt_page2); - if (tb->page_addr[1] == phys_page2) { + virt_page1 = TARGET_PAGE_ALIGN(desc->pc); + phys_page1 = get_page_addr_code(desc->env, virt_page1); + if (tb->page_addr[1] == phys_page1) { return true; } } @@ -235,7 +235,7 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, if (phys_pc == -1) { return NULL; } - desc.phys_page1 = phys_pc & TARGET_PAGE_MASK; + desc.page_addr0 = phys_pc; h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3a3549ad4a..ac4442ee8d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -951,7 +951,8 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, can be detected */ void tlb_protect_code(ram_addr_t ram_addr) { - cpu_physical_memory_test_and_clear_dirty(ram_addr, TARGET_PAGE_SIZE, + cpu_physical_memory_test_and_clear_dirty(ram_addr & TARGET_PAGE_MASK, + TARGET_PAGE_SIZE, DIRTY_MEMORY_CODE); } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d2946f8e59..d1f478d836 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1186,7 +1186,7 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) qemu_spin_unlock(&tb->jmp_lock); /* remove the TB from the hash list */ - phys_pc = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); + phys_pc = tb->page_addr[0]; h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { @@ -1342,7 +1342,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, * we can only insert TBs that are fully initialized. */ page_lock_pair(&p, phys_pc, &p2, phys_page2, true); - tb_page_add(p, tb, 0, phys_pc & TARGET_PAGE_MASK); + tb_page_add(p, tb, 0, phys_pc); if (p2) { tb_page_add(p2, tb, 1, phys_page2); } else { @@ -1697,11 +1697,12 @@ tb_invalidate_phys_page_range__locked(struct page_collection *pages, if (n == 0) { /* NOTE: tb_end may be after the end of the page, but it is not a problem */ - tb_start = tb->page_addr[0] + (tb->pc & ~TARGET_PAGE_MASK); + tb_start = tb->page_addr[0]; tb_end = tb_start + tb->size; } else { tb_start = tb->page_addr[1]; - tb_end = tb_start + ((tb->pc + tb->size) & ~TARGET_PAGE_MASK); + tb_end = tb_start + ((tb->page_addr[0] + tb->size) + & ~TARGET_PAGE_MASK); } if (!(tb_end <= start || tb_start >= end)) { #ifdef TARGET_HAS_PRECISE_SMC From patchwork Tue Sep 6 09:11:23 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602974 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4374037mae; Tue, 6 Sep 2022 02:57:11 -0700 (PDT) X-Google-Smtp-Source: AA6agR73IvRTrv3/VgrXbkwmStcXrkyTxF8huHq45tClC4B00MdOnw8bbFtZTVjwvSJrxksBcwIQ X-Received: by 2002:ac8:584b:0:b0:343:6f4a:d04e with SMTP id h11-20020ac8584b000000b003436f4ad04emr42994498qth.425.1662458231043; Tue, 06 Sep 2022 02:57:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662458231; cv=none; d=google.com; s=arc-20160816; b=b7DOyfhBIxOVlplfO0oGBAWjncIPEQJaO03L10TvE/qeGZWsvoGtopPsKQoFRsbzUT rNnG6O60lHfiChwXMo8wFf6ekHyggNXtYA3ZalMh5w14xCobYQ+GQmJH6+YZMsrD0jtT XndowaOUIUdtFTaO6F2mWY7wGdF2vt/SmS8Wu37LP57tmlxZcou7Rc9fp4Zxb24yFwNt kx/KQx+Hiopu/fSYMszYXqLqxhct88A3ktqgdT3Sr+wu4bZ5BkFTkUmdLPqMmPJGlyRr opu83SwbIFjx5OMd9K6HCAbJUsZHikcii/gG4WJZ8jgs64ctoJxvl4agrcKIe65sVsCy qoeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=M1x+zyGC28K7Q+U3nSiQK9bIwX4RNio1iwL+SZjxtfU=; b=v4PRso7FYjdpXdwmuWYNyqfwUAQZOI0qvD/3yjMm3JNU2L8NUSHWymipJDCVObjRyP n+87d4CfVvn/eCrGmdaCRIHAOjMmUqRg2DfTlLqi6SizsLu1NziJym9OGZlqwRl4d1gA TaNfRbgL3OvoFCJz7Q+N687CGufUNNgF6wymBftmVygo3dVFDg+EFQYLf1HB0Hob6Kyq B8KvvfOzWVU1SH555Bl01R/OQO4O6OY7SHTW1g98HKhw4lGjvBFEH7vg5y3AKp9PPlDN HqpciIwdbmM810x9JHwI9kYrjOwDSRoS0J1Z7Mx/kej4wmpMknWi7jNo7Zk0TkYBNutT hZew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hHj2XxbS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/hw/core/cpu.h | 8 ++++++-- accel/tcg/cpu-exec.c | 9 ++++++--- accel/tcg/cputlb.c | 2 +- accel/tcg/translate-all.c | 4 ++-- 4 files changed, 15 insertions(+), 8 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 9e47184513..ee5b75dea0 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -232,6 +232,10 @@ struct hvf_vcpu_state; #define TB_JMP_CACHE_BITS 12 #define TB_JMP_CACHE_SIZE (1 << TB_JMP_CACHE_BITS) +typedef struct { + TranslationBlock *tb; +} CPUJumpCache; + /* work queue */ /* The union type allows passing of 64 bit target pointers on 32 bit @@ -361,7 +365,7 @@ struct CPUState { IcountDecr *icount_decr_ptr; /* Accessed in parallel; all accesses must be atomic */ - TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; + CPUJumpCache tb_jmp_cache[TB_JMP_CACHE_SIZE]; struct GDBRegisterState *gdb_regs; int gdb_num_regs; @@ -452,7 +456,7 @@ static inline void cpu_tb_jmp_cache_clear(CPUState *cpu) unsigned int i; for (i = 0; i < TB_JMP_CACHE_SIZE; i++) { - qatomic_set(&cpu->tb_jmp_cache[i], NULL); + qatomic_set(&cpu->tb_jmp_cache[i].tb, NULL); } } diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index dd58a144a8..c6283d5798 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -252,7 +252,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, tcg_debug_assert(!(cflags & CF_INVALID)); hash = tb_jmp_cache_hash_func(pc); - tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash]); + tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash].tb); if (likely(tb && tb->pc == pc && @@ -266,7 +266,7 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, if (tb == NULL) { return NULL; } - qatomic_set(&cpu->tb_jmp_cache[hash], tb); + qatomic_set(&cpu->tb_jmp_cache[hash].tb, tb); return tb; } @@ -987,6 +987,8 @@ int cpu_exec(CPUState *cpu) tb = tb_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { + uint32_t h; + mmap_lock(); tb = tb_gen_code(cpu, pc, cs_base, flags, cflags); mmap_unlock(); @@ -994,7 +996,8 @@ int cpu_exec(CPUState *cpu) * We add the TB in the virtual pc hash table * for the fast lookup */ - qatomic_set(&cpu->tb_jmp_cache[tb_jmp_cache_hash_func(pc)], tb); + h = tb_jmp_cache_hash_func(pc); + qatomic_set(&cpu->tb_jmp_cache[h].tb, tb); } #ifndef CONFIG_USER_ONLY diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index ac4442ee8d..371d7f1440 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -103,7 +103,7 @@ static void tb_jmp_cache_clear_page(CPUState *cpu, target_ulong page_addr) unsigned int i, i0 = tb_jmp_cache_hash_page(page_addr); for (i = 0; i < TB_JMP_PAGE_SIZE; i++) { - qatomic_set(&cpu->tb_jmp_cache[i0 + i], NULL); + qatomic_set(&cpu->tb_jmp_cache[i0 + i].tb, NULL); } } diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d1f478d836..324a71317c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -1208,8 +1208,8 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) /* remove the TB from the hash list */ h = tb_jmp_cache_hash_func(tb->pc); CPU_FOREACH(cpu) { - if (qatomic_read(&cpu->tb_jmp_cache[h]) == tb) { - qatomic_set(&cpu->tb_jmp_cache[h], NULL); + if (qatomic_read(&cpu->tb_jmp_cache[h].tb) == tb) { + qatomic_set(&cpu->tb_jmp_cache[h].tb, NULL); } } From patchwork Tue Sep 6 09:11:24 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602977 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4377037mae; Tue, 6 Sep 2022 03:01:50 -0700 (PDT) X-Google-Smtp-Source: AA6agR7b3fjLJdfnAE61f9FKjW8TzD8plWgC7KIMHCHOujhrRNxprhNtyB6ilag8gWs89nEZgSBD X-Received: by 2002:ae9:ea13:0:b0:6bc:2056:100c with SMTP id f19-20020ae9ea13000000b006bc2056100cmr35176133qkg.100.1662458509948; Tue, 06 Sep 2022 03:01:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662458509; cv=none; d=google.com; s=arc-20160816; b=h9Sh/bFaCj5JOOQW9lNRYlRKD5VGFKBf6qH5yywplo9F4nig3hF7MCKQieOp1ZIugY Q0GtR7TnwhUdTtIMmwFprd60XCfx5/NMC124hSru2bcjFdm0QtYYBP0Q1e7bFcofI/uS qGsus8dd/VijieYgkbI1FSKaXvkfVdlJAqQpK1h2Y6bmXYn4W450yoiZ873P41prBNHS 7f1OuLuiMhci8+H6u9wTt8mLBDn3/+Plru++DUNVeBAQ5RW52HntOH/aMhA+VDpl3sfK fVpRKFtegwZD1BDRBozh5ETWJ5Azd2qq3HNlcyEDgm/0+RtqyxPAbK/CYpfIykDrcoHx R3tQ== ARC-Message-Signature: i=1; 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Introduce accessor functions to minimize ifdefs. Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 12 ++++++++++ accel/tcg/cpu-exec.c | 20 ++++++++--------- accel/tcg/translate-all.c | 29 +++++++++++++------------ target/arm/cpu.c | 4 ++-- target/avr/cpu.c | 2 +- target/hexagon/cpu.c | 2 +- target/hppa/cpu.c | 4 ++-- target/i386/tcg/tcg-cpu.c | 2 +- target/loongarch/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/tcg/exception.c | 2 +- target/mips/tcg/sysemu/special_helper.c | 2 +- target/openrisc/cpu.c | 2 +- target/riscv/cpu.c | 4 ++-- target/rx/cpu.c | 2 +- target/sh4/cpu.c | 4 ++-- target/sparc/cpu.c | 2 +- target/tricore/cpu.c | 2 +- tcg/tcg.c | 6 ++--- 19 files changed, 59 insertions(+), 46 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 1a30c857f4..9eeb8eb790 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -566,6 +566,18 @@ struct TranslationBlock { uintptr_t jmp_dest[2]; }; +/* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ +static inline target_ulong tb_pc(const TranslationBlock *tb) +{ + return tb->pc; +} + +/* Similarly, but for logs. */ +static inline target_ulong tb_pc_log(const TranslationBlock *tb) +{ + return tb->pc; +} + /* Hide the qatomic_read to make code a little easier on the eyes */ static inline uint32_t tb_cflags(const TranslationBlock *tb) { diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c6283d5798..2cf84952e1 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -185,7 +185,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const TranslationBlock *tb = p; const struct tb_desc *desc = d; - if (tb->pc == desc->pc && + if (tb_pc(tb) == desc->pc && tb->page_addr[0] == desc->page_addr0 && tb->cs_base == desc->cs_base && tb->flags == desc->flags && @@ -422,7 +422,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) TranslationBlock *last_tb; const void *tb_ptr = itb->tc.ptr; - log_cpu_exec(itb->pc, cpu, itb); + log_cpu_exec(tb_pc_log(itb), cpu, itb); qemu_thread_jit_execute(); ret = tcg_qemu_tb_exec(env, tb_ptr); @@ -446,16 +446,16 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) * of the start of the TB. */ CPUClass *cc = CPU_GET_CLASS(cpu); - qemu_log_mask_and_addr(CPU_LOG_EXEC, last_tb->pc, + qemu_log_mask_and_addr(CPU_LOG_EXEC, tb_pc_log(last_tb), "Stopped execution of TB chain before %p [" TARGET_FMT_lx "] %s\n", - last_tb->tc.ptr, last_tb->pc, - lookup_symbol(last_tb->pc)); + last_tb->tc.ptr, tb_pc_log(last_tb), + lookup_symbol(tb_pc_log(last_tb))); if (cc->tcg_ops->synchronize_from_tb) { cc->tcg_ops->synchronize_from_tb(cpu, last_tb); } else { assert(cc->set_pc); - cc->set_pc(cpu, last_tb->pc); + cc->set_pc(cpu, tb_pc(last_tb)); } } @@ -597,11 +597,11 @@ static inline void tb_add_jump(TranslationBlock *tb, int n, qemu_spin_unlock(&tb_next->jmp_lock); - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, + qemu_log_mask_and_addr(CPU_LOG_EXEC, tb_pc_log(tb), "Linking TBs %p [" TARGET_FMT_lx "] index %d -> %p [" TARGET_FMT_lx "]\n", - tb->tc.ptr, tb->pc, n, - tb_next->tc.ptr, tb_next->pc); + tb->tc.ptr, tb_pc_log(tb), n, + tb_next->tc.ptr, tb_pc_log(tb_next)); return; out_unlock_next: @@ -851,7 +851,7 @@ static inline void cpu_loop_exec_tb(CPUState *cpu, TranslationBlock *tb, { int32_t insns_left; - trace_exec_tb(tb, tb->pc); + trace_exec_tb(tb, tb_pc_log(tb)); tb = cpu_tb_exec(cpu, tb, tb_exit); if (*tb_exit != TB_EXIT_REQUESTED) { *last_tb = tb; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 324a71317c..36e34496c5 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -305,7 +305,7 @@ static int encode_search(TranslationBlock *tb, uint8_t *block) for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { if (i == 0) { - prev = (j == 0 ? tb->pc : 0); + prev = (j == 0 ? tb_pc(tb) : 0); } else { prev = tcg_ctx->gen_insn_data[i - 1][j]; } @@ -333,7 +333,7 @@ static int encode_search(TranslationBlock *tb, uint8_t *block) static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc, bool reset_icount) { - target_ulong data[TARGET_INSN_START_WORDS] = { tb->pc }; + target_ulong data[TARGET_INSN_START_WORDS] = { tb_pc(tb) }; uintptr_t host_pc = (uintptr_t)tb->tc.ptr; CPUArchState *env = cpu->env_ptr; const uint8_t *p = tb->tc.ptr + tb->tc.size; @@ -891,7 +891,7 @@ static bool tb_cmp(const void *ap, const void *bp) const TranslationBlock *a = ap; const TranslationBlock *b = bp; - return a->pc == b->pc && + return tb_pc(a) == tb_pc(b) && a->cs_base == b->cs_base && a->flags == b->flags && (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) && @@ -1031,9 +1031,10 @@ static void do_tb_invalidate_check(void *p, uint32_t hash, void *userp) TranslationBlock *tb = p; target_ulong addr = *(target_ulong *)userp; - if (!(addr + TARGET_PAGE_SIZE <= tb->pc || addr >= tb->pc + tb->size)) { + if (!(addr + TARGET_PAGE_SIZE <= tb_pc(tb) || + addr >= tb_pc(tb) + tb->size)) { printf("ERROR invalidate: address=" TARGET_FMT_lx - " PC=%08lx size=%04x\n", addr, (long)tb->pc, tb->size); + " PC=%08lx size=%04x\n", addr, (long)tb_pc(tb), tb->size); } } @@ -1052,11 +1053,11 @@ static void do_tb_page_check(void *p, uint32_t hash, void *userp) TranslationBlock *tb = p; int flags1, flags2; - flags1 = page_get_flags(tb->pc); - flags2 = page_get_flags(tb->pc + tb->size - 1); + flags1 = page_get_flags(tb_pc(tb)); + flags2 = page_get_flags(tb_pc(tb) + tb->size - 1); if ((flags1 & PAGE_WRITE) || (flags2 & PAGE_WRITE)) { printf("ERROR page flags: PC=%08lx size=%04x f1=%x f2=%x\n", - (long)tb->pc, tb->size, flags1, flags2); + (long)tb_pc(tb), tb->size, flags1, flags2); } } @@ -1187,7 +1188,7 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) /* remove the TB from the hash list */ phys_pc = tb->page_addr[0]; - h = tb_hash_func(phys_pc, tb->pc, tb->flags, orig_cflags, + h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; @@ -1350,7 +1351,7 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, } /* add in the hash table */ - h = tb_hash_func(phys_pc, tb->pc, tb->flags, tb->cflags, + h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, tb->trace_vcpu_dstate); qht_insert(&tb_ctx.htable, tb, h, &existing_tb); @@ -1452,7 +1453,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->cpu = NULL; max_insns = tb->icount; - trace_translate_block(tb, tb->pc, tb->tc.ptr); + trace_translate_block(tb, tb_pc_log(tb), tb->tc.ptr); /* generate machine code */ tb->jmp_reset_offset[0] = TB_JMP_RESET_OFFSET_INVALID; @@ -1529,7 +1530,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, #ifdef DEBUG_DISAS if (qemu_loglevel_mask(CPU_LOG_TB_OUT_ASM) && - qemu_log_in_addr_range(tb->pc)) { + qemu_log_in_addr_range(tb_pc_log(tb))) { FILE *logfile = qemu_log_trylock(); if (logfile) { int code_size, data_size; @@ -1986,9 +1987,9 @@ void cpu_io_recompile(CPUState *cpu, uintptr_t retaddr) */ cpu->cflags_next_tb = curr_cflags(cpu) | CF_MEMI_ONLY | CF_LAST_IO | n; - qemu_log_mask_and_addr(CPU_LOG_EXEC, tb->pc, + qemu_log_mask_and_addr(CPU_LOG_EXEC, tb_pc_log(tb), "cpu_io_recompile: rewound execution of TB to " - TARGET_FMT_lx "\n", tb->pc); + TARGET_FMT_lx "\n", tb_pc_log(tb)); cpu_loop_exit_noexc(cpu); } diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7ec3281da9..047bf3f4ab 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -72,9 +72,9 @@ void arm_cpu_synchronize_from_tb(CPUState *cs, * never possible for an AArch64 TB to chain to an AArch32 TB. */ if (is_a64(env)) { - env->pc = tb->pc; + env->pc = tb_pc(tb); } else { - env->regs[15] = tb->pc; + env->regs[15] = tb_pc(tb); } } #endif /* CONFIG_TCG */ diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 05b992ff73..6ebef62b4c 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -47,7 +47,7 @@ static void avr_cpu_synchronize_from_tb(CPUState *cs, AVRCPU *cpu = AVR_CPU(cs); CPUAVRState *env = &cpu->env; - env->pc_w = tb->pc / 2; /* internally PC points to words */ + env->pc_w = tb_pc(tb) / 2; /* internally PC points to words */ } static void avr_cpu_reset(DeviceState *ds) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index fa9bd702d6..6289a6e64a 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -256,7 +256,7 @@ static void hexagon_cpu_synchronize_from_tb(CPUState *cs, { HexagonCPU *cpu = HEXAGON_CPU(cs); CPUHexagonState *env = &cpu->env; - env->gpr[HEX_REG_PC] = tb->pc; + env->gpr[HEX_REG_PC] = tb_pc(tb); } static bool hexagon_cpu_has_work(CPUState *cs) diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index a6f52caf14..fc9d43f620 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -42,7 +42,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, HPPACPU *cpu = HPPA_CPU(cs); #ifdef CONFIG_USER_ONLY - cpu->env.iaoq_f = tb->pc; + cpu->env.iaoq_f = tb_pc(tb); cpu->env.iaoq_b = tb->cs_base; #else /* Recover the IAOQ values from the GVA + PRIV. */ @@ -52,7 +52,7 @@ static void hppa_cpu_synchronize_from_tb(CPUState *cs, int32_t diff = cs_base; cpu->env.iasq_f = iasq_f; - cpu->env.iaoq_f = (tb->pc & ~iasq_f) + priv; + cpu->env.iaoq_f = (tb_pc(tb) & ~iasq_f) + priv; if (diff) { cpu->env.iaoq_b = cpu->env.iaoq_f + diff; } diff --git a/target/i386/tcg/tcg-cpu.c b/target/i386/tcg/tcg-cpu.c index 6fdfdf9598..76989a5a9d 100644 --- a/target/i386/tcg/tcg-cpu.c +++ b/target/i386/tcg/tcg-cpu.c @@ -51,7 +51,7 @@ static void x86_cpu_synchronize_from_tb(CPUState *cs, { X86CPU *cpu = X86_CPU(cs); - cpu->env.eip = tb->pc - tb->cs_base; + cpu->env.eip = tb_pc(tb) - tb->cs_base; } #ifndef CONFIG_USER_ONLY diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 941e2772bc..262ddfb51c 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -309,7 +309,7 @@ static void loongarch_cpu_synchronize_from_tb(CPUState *cs, LoongArchCPU *cpu = LOONGARCH_CPU(cs); CPULoongArchState *env = &cpu->env; - env->pc = tb->pc; + env->pc = tb_pc(tb); } #endif /* CONFIG_TCG */ diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index aed200dcff..5a642db285 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -89,7 +89,7 @@ static void mb_cpu_synchronize_from_tb(CPUState *cs, { MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); - cpu->env.pc = tb->pc; + cpu->env.pc = tb_pc(tb); cpu->env.iflags = tb->flags & IFLAGS_TB_MASK; } diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c index 2bd77a61de..96e61170e6 100644 --- a/target/mips/tcg/exception.c +++ b/target/mips/tcg/exception.c @@ -82,7 +82,7 @@ void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; - env->active_tc.PC = tb->pc; + env->active_tc.PC = tb_pc(tb); env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= tb->flags & MIPS_HFLAG_BMASK; } diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c index f4f8fe8afc..3c5f35c759 100644 --- a/target/mips/tcg/sysemu/special_helper.c +++ b/target/mips/tcg/sysemu/special_helper.c @@ -94,7 +94,7 @@ bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) CPUMIPSState *env = &cpu->env; if ((env->hflags & MIPS_HFLAG_BMASK) != 0 - && env->active_tc.PC != tb->pc) { + && env->active_tc.PC != tb_pc(tb)) { env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); env->hflags &= ~MIPS_HFLAG_BMASK; return true; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index cb9f35f408..7bba181420 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -36,7 +36,7 @@ static void openrisc_cpu_synchronize_from_tb(CPUState *cs, { OpenRISCCPU *cpu = OPENRISC_CPU(cs); - cpu->env.pc = tb->pc; + cpu->env.pc = tb_pc(tb); } diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ac6f82ebd0..8cb9428a80 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -397,9 +397,9 @@ static void riscv_cpu_synchronize_from_tb(CPUState *cs, RISCVMXL xl = FIELD_EX32(tb->flags, TB_FLAGS, XL); if (xl == MXL_RV32) { - env->pc = (int32_t)tb->pc; + env->pc = (int32_t)tb_pc(tb); } else { - env->pc = tb->pc; + env->pc = tb_pc(tb); } } diff --git a/target/rx/cpu.c b/target/rx/cpu.c index fb30080ac4..f1e0008e04 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -37,7 +37,7 @@ static void rx_cpu_synchronize_from_tb(CPUState *cs, { RXCPU *cpu = RX_CPU(cs); - cpu->env.pc = tb->pc; + cpu->env.pc = tb_pc(tb); } static bool rx_cpu_has_work(CPUState *cs) diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 06b2691dc4..6948c8fa33 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -39,7 +39,7 @@ static void superh_cpu_synchronize_from_tb(CPUState *cs, { SuperHCPU *cpu = SUPERH_CPU(cs); - cpu->env.pc = tb->pc; + cpu->env.pc = tb_pc(tb); cpu->env.flags = tb->flags & TB_FLAG_ENVFLAGS_MASK; } @@ -51,7 +51,7 @@ static bool superh_io_recompile_replay_branch(CPUState *cs, CPUSH4State *env = &cpu->env; if ((env->flags & ((DELAY_SLOT | DELAY_SLOT_CONDITIONAL))) != 0 - && env->pc != tb->pc) { + && env->pc != tb_pc(tb)) { env->pc -= 2; env->flags &= ~(DELAY_SLOT | DELAY_SLOT_CONDITIONAL); return true; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 55268ed2a1..0471c2fe5a 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -698,7 +698,7 @@ static void sparc_cpu_synchronize_from_tb(CPUState *cs, { SPARCCPU *cpu = SPARC_CPU(cs); - cpu->env.pc = tb->pc; + cpu->env.pc = tb_pc(tb); cpu->env.npc = tb->cs_base; } diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index b95682b7f0..35f3347add 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -47,7 +47,7 @@ static void tricore_cpu_synchronize_from_tb(CPUState *cs, TriCoreCPU *cpu = TRICORE_CPU(cs); CPUTriCoreState *env = &cpu->env; - env->PC = tb->pc; + env->PC = tb_pc(tb); } static void tricore_cpu_reset(DeviceState *dev) diff --git a/tcg/tcg.c b/tcg/tcg.c index 0f9cfe96f2..11bdb96dd1 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -4218,7 +4218,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(tb_pc_log(tb)))) { FILE *logfile = qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP:\n"); @@ -4265,7 +4265,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) if (s->nb_indirects > 0) { #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_IND) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(tb_pc_log(tb)))) { FILE *logfile = qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP before indirect lowering:\n"); @@ -4288,7 +4288,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) #ifdef DEBUG_DISAS if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT) - && qemu_log_in_addr_range(tb->pc))) { + && qemu_log_in_addr_range(tb_pc_log(tb)))) { FILE *logfile = qemu_log_trylock(); if (logfile) { fprintf(logfile, "OP after optimization and liveness analysis:\n"); From patchwork Tue Sep 6 09:11:25 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602976 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4375501mae; Tue, 6 Sep 2022 03:00:00 -0700 (PDT) X-Google-Smtp-Source: AA6agR5gYdz/rfw77laoYNai1dpyLiua/wYnwuktQuzQt7qsMG/XfjJ4HlhVjvEBa12yzYeDxyeZ X-Received: by 2002:a37:755:0:b0:6ba:fcb7:1949 with SMTP id 82-20020a370755000000b006bafcb71949mr35001153qkh.590.1662458400636; Tue, 06 Sep 2022 03:00:00 -0700 (PDT) ARC-Seal: i=1; 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Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 3 +++ include/exec/exec-all.h | 41 ++++++++++++++++++++++++++--- include/hw/core/cpu.h | 1 + accel/tcg/cpu-exec.c | 55 ++++++++++++++++++++++++++++++--------- accel/tcg/translate-all.c | 48 ++++++++++++++++++++++------------ 5 files changed, 115 insertions(+), 33 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 67239b4e5e..21309cf567 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -54,6 +54,9 @@ # error TARGET_PAGE_BITS must be defined in cpu-param.h # endif #endif +#ifndef TARGET_TB_PCREL +# define TARGET_TB_PCREL 0 +#endif #define TARGET_LONG_SIZE (TARGET_LONG_BITS / 8) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 9eeb8eb790..ab64ed19af 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -492,8 +492,32 @@ struct tb_tc { }; struct TranslationBlock { - target_ulong pc; /* simulated PC corresponding to this block (EIP + CS base) */ - target_ulong cs_base; /* CS base for this block */ +#if !TARGET_TB_PCREL + /* + * Guest PC corresponding to this block. This must be the true + * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and + * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or + * privilege, must store those bits elsewhere. + * + * If TARGET_TB_PCREL, the opcodes for the TranslationBlock are + * written such that the TB is associated only with the physical + * page and may be run in any virtual address context. In this case, + * PC must always be taken from ENV in a target-specific manner. + * Unwind information is taken as offsets from the page, to be + * deposited into the "current" PC. + */ + target_ulong pc; +#endif + + /* + * Target-specific data associated with the TranslationBlock, e.g.: + * x86: the original user, the Code Segment virtual base, + * arm: an extension of tb->flags, + * s390x: instruction data for EXECUTE, + * sparc: the next pc of the instruction queue (for delay slots). + */ + target_ulong cs_base; + uint32_t flags; /* flags defining in which context the code was generated */ uint32_t cflags; /* compile flags */ @@ -569,13 +593,24 @@ struct TranslationBlock { /* Hide the read to avoid ifdefs for TARGET_TB_PCREL. */ static inline target_ulong tb_pc(const TranslationBlock *tb) { +#if TARGET_TB_PCREL + qemu_build_not_reached(); +#else return tb->pc; +#endif } -/* Similarly, but for logs. */ +/* + * Similarly, but for logs. In this case, when the virtual pc + * is not available, use the physical address. + */ static inline target_ulong tb_pc_log(const TranslationBlock *tb) { +#if TARGET_TB_PCREL + return tb->page_addr[0]; +#else return tb->pc; +#endif } /* Hide the qatomic_read to make code a little easier on the eyes */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index ee5b75dea0..b73dd31495 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -234,6 +234,7 @@ struct hvf_vcpu_state; typedef struct { TranslationBlock *tb; + vaddr pc; } CPUJumpCache; /* work queue */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 2cf84952e1..7fe42269ea 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -185,7 +185,7 @@ static bool tb_lookup_cmp(const void *p, const void *d) const TranslationBlock *tb = p; const struct tb_desc *desc = d; - if (tb_pc(tb) == desc->pc && + if ((TARGET_TB_PCREL || tb_pc(tb) == desc->pc) && tb->page_addr[0] == desc->page_addr0 && tb->cs_base == desc->cs_base && tb->flags == desc->flags && @@ -236,7 +236,8 @@ static TranslationBlock *tb_htable_lookup(CPUState *cpu, target_ulong pc, return NULL; } desc.page_addr0 = phys_pc; - h = tb_hash_func(phys_pc, pc, flags, cflags, *cpu->trace_dstate); + h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : pc), + flags, cflags, *cpu->trace_dstate); return qht_lookup_custom(&tb_ctx.htable, &desc, h, tb_lookup_cmp); } @@ -252,21 +253,42 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, tcg_debug_assert(!(cflags & CF_INVALID)); hash = tb_jmp_cache_hash_func(pc); - tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash].tb); - - if (likely(tb && - tb->pc == pc && - tb->cs_base == cs_base && - tb->flags == flags && - tb->trace_vcpu_dstate == *cpu->trace_dstate && - tb_cflags(tb) == cflags)) { - return tb; + if (TARGET_TB_PCREL) { + /* Use acquire to ensure current load of pc from tb_jmp_cache[]. */ + tb = qatomic_load_acquire(&cpu->tb_jmp_cache[hash].tb); + } else { + /* Use rcu_read to ensure current load of pc from *tb. */ + tb = qatomic_rcu_read(&cpu->tb_jmp_cache[hash].tb); } + if (likely(tb)) { + target_ulong jmp_pc; + + if (TARGET_TB_PCREL) { + jmp_pc = cpu->tb_jmp_cache[hash].pc; + } else { + jmp_pc = tb_pc(tb); + } + if (jmp_pc == pc && + tb->cs_base == cs_base && + tb->flags == flags && + tb->trace_vcpu_dstate == *cpu->trace_dstate && + tb_cflags(tb) == cflags) { + return tb; + } + } + tb = tb_htable_lookup(cpu, pc, cs_base, flags, cflags); if (tb == NULL) { return NULL; } - qatomic_set(&cpu->tb_jmp_cache[hash].tb, tb); + + if (TARGET_TB_PCREL) { + cpu->tb_jmp_cache[hash].pc = pc; + /* Use store_release on tb to ensure pc is current. */ + qatomic_store_release(&cpu->tb_jmp_cache[hash].tb, tb); + } else { + qatomic_set(&cpu->tb_jmp_cache[hash].tb, tb); + } return tb; } @@ -454,6 +476,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) if (cc->tcg_ops->synchronize_from_tb) { cc->tcg_ops->synchronize_from_tb(cpu, last_tb); } else { + assert(!TARGET_TB_PCREL); assert(cc->set_pc); cc->set_pc(cpu, tb_pc(last_tb)); } @@ -997,7 +1020,13 @@ int cpu_exec(CPUState *cpu) * for the fast lookup */ h = tb_jmp_cache_hash_func(pc); - qatomic_set(&cpu->tb_jmp_cache[h].tb, tb); + if (TARGET_TB_PCREL) { + cpu->tb_jmp_cache[h].pc = pc; + /* Use store_release on tb to ensure pc is current. */ + qatomic_store_release(&cpu->tb_jmp_cache[h].tb, tb); + } else { + qatomic_set(&cpu->tb_jmp_cache[h].tb, tb); + } } #ifndef CONFIG_USER_ONLY diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 36e34496c5..c521e29df4 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -305,7 +305,7 @@ static int encode_search(TranslationBlock *tb, uint8_t *block) for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { if (i == 0) { - prev = (j == 0 ? tb_pc(tb) : 0); + prev = (!TARGET_TB_PCREL && j == 0 ? tb_pc(tb) : 0); } else { prev = tcg_ctx->gen_insn_data[i - 1][j]; } @@ -333,7 +333,7 @@ static int encode_search(TranslationBlock *tb, uint8_t *block) static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, uintptr_t searched_pc, bool reset_icount) { - target_ulong data[TARGET_INSN_START_WORDS] = { tb_pc(tb) }; + target_ulong data[TARGET_INSN_START_WORDS]; uintptr_t host_pc = (uintptr_t)tb->tc.ptr; CPUArchState *env = cpu->env_ptr; const uint8_t *p = tb->tc.ptr + tb->tc.size; @@ -349,6 +349,11 @@ static int cpu_restore_state_from_tb(CPUState *cpu, TranslationBlock *tb, return -1; } + memset(data, 0, sizeof(data)); + if (!TARGET_TB_PCREL) { + data[0] = tb_pc(tb); + } + /* Reconstruct the stored insn data while looking for the point at which the end of the insn exceeds the searched_pc. */ for (i = 0; i < num_insns; ++i) { @@ -891,13 +896,13 @@ static bool tb_cmp(const void *ap, const void *bp) const TranslationBlock *a = ap; const TranslationBlock *b = bp; - return tb_pc(a) == tb_pc(b) && - a->cs_base == b->cs_base && - a->flags == b->flags && - (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) && - a->trace_vcpu_dstate == b->trace_vcpu_dstate && - a->page_addr[0] == b->page_addr[0] && - a->page_addr[1] == b->page_addr[1]; + return ((TARGET_TB_PCREL || tb_pc(a) == tb_pc(b)) && + a->cs_base == b->cs_base && + a->flags == b->flags && + (tb_cflags(a) & ~CF_INVALID) == (tb_cflags(b) & ~CF_INVALID) && + a->trace_vcpu_dstate == b->trace_vcpu_dstate && + a->page_addr[0] == b->page_addr[0] && + a->page_addr[1] == b->page_addr[1]); } void tb_htable_init(void) @@ -1188,8 +1193,8 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) /* remove the TB from the hash list */ phys_pc = tb->page_addr[0]; - h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, orig_cflags, - tb->trace_vcpu_dstate); + h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), + tb->flags, orig_cflags, tb->trace_vcpu_dstate); if (!qht_remove(&tb_ctx.htable, tb, h)) { return; } @@ -1207,10 +1212,17 @@ static void do_tb_phys_invalidate(TranslationBlock *tb, bool rm_from_page_list) } /* remove the TB from the hash list */ - h = tb_jmp_cache_hash_func(tb->pc); - CPU_FOREACH(cpu) { - if (qatomic_read(&cpu->tb_jmp_cache[h].tb) == tb) { - qatomic_set(&cpu->tb_jmp_cache[h].tb, NULL); + if (TARGET_TB_PCREL) { + /* Any TB may be at any virtual address */ + CPU_FOREACH(cpu) { + cpu_tb_jmp_cache_clear(cpu); + } + } else { + h = tb_jmp_cache_hash_func(tb_pc(tb)); + CPU_FOREACH(cpu) { + if (qatomic_read(&cpu->tb_jmp_cache[h].tb) == tb) { + qatomic_set(&cpu->tb_jmp_cache[h].tb, NULL); + } } } @@ -1351,8 +1363,8 @@ tb_link_page(TranslationBlock *tb, tb_page_addr_t phys_pc, } /* add in the hash table */ - h = tb_hash_func(phys_pc, tb_pc(tb), tb->flags, tb->cflags, - tb->trace_vcpu_dstate); + h = tb_hash_func(phys_pc, (TARGET_TB_PCREL ? 0 : tb_pc(tb)), + tb->flags, tb->cflags, tb->trace_vcpu_dstate); qht_insert(&tb_ctx.htable, tb, h, &existing_tb); /* remove TB from the page(s) if we couldn't insert it */ @@ -1424,7 +1436,9 @@ TranslationBlock *tb_gen_code(CPUState *cpu, gen_code_buf = tcg_ctx->code_gen_ptr; tb->tc.ptr = tcg_splitwx_to_rx(gen_code_buf); +#if !TARGET_TB_PCREL tb->pc = pc; +#endif tb->cs_base = cs_base; tb->flags = flags; tb->cflags = cflags; From patchwork Tue Sep 6 09:11:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 602978 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp4381276mae; Tue, 6 Sep 2022 03:07:20 -0700 (PDT) X-Google-Smtp-Source: AA6agR5u60/4hKplTQJYLH/NbBZ6VVz+4cSBhhzbu3qbdF3qFHGwApip0gSAFCqk54mwtNaIPklV X-Received: by 2002:a05:622a:205:b0:343:282:3d0e with SMTP id b5-20020a05622a020500b0034302823d0emr42543421qtx.436.1662458840451; Tue, 06 Sep 2022 03:07:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1662458840; cv=none; d=google.com; s=arc-20160816; b=R9h36FUcCCNteg2JdbEm8jzNc90fKg32pMGl/8XtIUa12wOHiGGJHbG3FYgkUdK7GN 7p6ynVLuFNBGVbOErmfzp+Jfo/+OsTojrTNjuMV5qgWzA3VKluEWGeqEXfboyXHzNgNb xV1kqt6A5xJk98/X+vLCEg6fG7PwHdxb1Yn/FUHj5KheCRZncVSD9EAPfj56q1AYpDVP Q+wKAbw9xXRzRQC0iStVWtVKR4zcpL19GUHh318us4svFo5PBasdg7vjRIepviWI9LHY cFeO8V2Gx++3uN8Zf1XvK180P/LdaBN6jrlaZLwrQOexpOTBbEo5l2NoU5tMCqjfZV6P YoMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=SRY4FrKihbAdLBlGm0zlu+Vf4IcbXDY8j/QZi/7lz70=; b=qxhsFa7ZlovB/Z7O1FeAQFZVRynigbpuqylbrN/kd6vlLVBPmTKTcrZBBzQQQ2e2cr ZSJfRWY3GXP0p2EzSD3MaJzkxM4w8pbyfvUyIWy5pqyrajQh40OKmMq2rTEKxitiISDs v3qJnmov8qYwthcrkFK0rACpxZ2qGSQXm8Hh7rcIQsrWGQl2sYIL0i36uG8NNL1lqOSf O3KvnFHa1XvelwmdcXs3gUqlxE5gWf2eixjCinMV2mvnAFOqizf+Z8uUuymyI3az8i1B dH1r8ygAulUNSutSE0uNBvqQwSsWQgTpk4DDUPVVaPEivDY7170mVVi/oRlICU+nq3Ag Y/Kg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=djKDvi0Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 06 Sep 2022 02:11:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 7/7] accel/tcg: Split log_cpu_exec into inline and slow path Date: Tue, 6 Sep 2022 10:11:26 +0100 Message-Id: <20220906091126.298041-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220906091126.298041-1-richard.henderson@linaro.org> References: <20220906091126.298041-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- accel/tcg/cpu-exec.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 7fe42269ea..ac8eec7f54 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -292,12 +292,11 @@ static inline TranslationBlock *tb_lookup(CPUState *cpu, target_ulong pc, return tb; } -static inline void log_cpu_exec(target_ulong pc, CPUState *cpu, - const TranslationBlock *tb) +static void log_cpu_exec1(CPUState *cpu, const TranslationBlock *tb) { - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC)) - && qemu_log_in_addr_range(pc)) { + target_ulong pc = tb_pc_log(tb); + if (qemu_log_in_addr_range(pc)) { qemu_log_mask(CPU_LOG_EXEC, "Trace %d: %p [" TARGET_FMT_lx "/" TARGET_FMT_lx "/%08x/%08x] %s\n", @@ -324,6 +323,13 @@ static inline void log_cpu_exec(target_ulong pc, CPUState *cpu, } } +static inline void log_cpu_exec(CPUState *cpu, const TranslationBlock *tb) +{ + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_CPU | CPU_LOG_EXEC))) { + log_cpu_exec1(cpu, tb); + } +} + static bool check_for_breakpoints(CPUState *cpu, target_ulong pc, uint32_t *cflags) { @@ -421,7 +427,7 @@ const void *HELPER(lookup_tb_ptr)(CPUArchState *env) return tcg_code_gen_epilogue; } - log_cpu_exec(pc, cpu, tb); + log_cpu_exec(cpu, tb); return tb->tc.ptr; } @@ -444,7 +450,7 @@ cpu_tb_exec(CPUState *cpu, TranslationBlock *itb, int *tb_exit) TranslationBlock *last_tb; const void *tb_ptr = itb->tc.ptr; - log_cpu_exec(tb_pc_log(itb), cpu, itb); + log_cpu_exec(cpu, itb); qemu_thread_jit_execute(); ret = tcg_qemu_tb_exec(env, tb_ptr);