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Miller" , Russell King , Heiner Kallweit , Andrew Lunn , Krzysztof Kozlowski , Rob Herring , Lee Jones , katie.morris@in-advantage.com Subject: [RESEND PATCH v16 mfd 3/8] pinctrl: ocelot: add ability to be used in a non-mmio configuration Date: Mon, 5 Sep 2022 09:21:27 -0700 Message-Id: <20220905162132.2943088-4-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220905162132.2943088-1-colin.foster@in-advantage.com> References: <20220905162132.2943088-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR04CA0263.namprd04.prod.outlook.com (2603:10b6:303:88::28) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 4bd45423-6b15-4f37-38fe-08da8f5abdde X-MS-TrafficTypeDiagnostic: PH0PR10MB5848:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: CvrouJWHnYvyV3iHkBO73x/KE7oi7UfoZWS8wx/9HazRWSVZ7XBrNA+OyeVsjhUc9TQ75nQNW7M8yCz705MXGQoLtpRFWGGX5gcnFm8NpooSlqv61ht1sCfbLF8b0qwekyy7pSz5iDeMG7dF1DXA1GdKubG2FwxbBhFV+huLAZNF0d6BXhcgZjGhSlTv4ky43DKFcWASy0ghao2kxvSpbW2h4CNGbKFKtF5zK+jx6joHqUh6Urv4013dVIpmLU/yWGPFZUCdBpZVzCO8NMw0LkJHvGLw+VCMNBcNG28SOu1CMLIWKxa9VUw/VKvsOuO6wcHBamu4uNQJfJ/qTapm7NRPq9vdXAhelE+TvGcnjdIaAf0xtrUw1wcSGxmwRo3L5WOMiOKz46TSaVdlCD0ERRdNakdRgma8xokhZqWIpVbRABgrPMopuAtIScLyr7hW4M37tntYuBAegGycH87qv2/sNPuvp0+C6xfJv6Gs1J2JhEw679dHFKVwmrDndBjAoruZRAQNJcmO8KgWMDMMheCk24tHbwavjwQ4g42dUtstXasYYWD10Pjs9mM3pultwXkzWcONXcrG788ThODvbzcTjQutwHa2uQWVnr3h4m/mWk6xCI9kvrCWebF9mbFFT5IdJfqM0lXVXhFHx3fYHhwq9CMDHtYhW04RZn0CXpn3sbMZjKB8VJCAmX/LkKf1NvItjW9zY3ctByMtMV3+rBOLVKIi9pT+AtvhJe2hhss45oKrZiQhlfKbXtUGFe/HgEGDt/feMPclTRcWllkhug== X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MWHPR1001MB2351.namprd10.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(396003)(346002)(376002)(39830400003)(136003)(366004)(66946007)(5660300002)(8936002)(66556008)(54906003)(6486002)(41300700001)(6666004)(107886003)(52116002)(186003)(2906002)(1076003)(7416002)(2616005)(44832011)(6512007)(36756003)(6506007)(316002)(83380400001)(26005)(38350700002)(38100700002)(4326008)(86362001)(66476007)(8676002)(478600001); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jufrvM/znJd2HAgHAkscTXPYwObU2D5cTBhwzWF3t/UjXsQ+S0DYnQHNLV6N4pO47wY1P+UeL++vHGhCeXCvs7brRyO/swtVDJ57/sLK241KpBPryzBmwfSEQmmaljjy2oR6i8UJvXrWxnkDgeCJylkPrj9rn0CEvTqv+HDvwHDljyXTGg3XEvKdF5G5IUMI11/xdLEPvu/vPX13CJu1CwfAPW6nO8J8D+yDAUZo/eIFy3PlmQDmbq2o2SOG5+ySz77fJbzzLafXPOWRAP/K7sHbRCyoa+R3ji1+xpxx60S3KWdvTpPB1k0kg7hMFR071x6H3M5MvGnE6n2GVjcdJkKqT+anSotnAuRNfLzo89gFXhl9y7J/foY5zK/pmgSfxqP4FIh4XghawvojpR5TCdFZsFm0xi/YYXl3uYrMxN3fcJKfFjUs0jLCZAVMjzKBPgiuSWJztXb9BaKt3N/pTrMhALD9R/SiXmscHiFZkIyaArNOWCycwQz54ljFGgVP3QM31Ds8ihNrNLrF26dqsi0+hELekEHXC3NInRhrDX+2NC9bwJElvKt++ICnkmFXpsjrMGaKl7ur2rfpAElvzTUwK7egSplO3r/+01Ak5Gu5NFqR983H2Yr3j3xJPdVhETL7fyD0kaJFgzNomuNWdCK1A9AciiZW+k9ILCh1ZBr8T5dwzpyp8MQGMeZ9nIhzJOL73rTyt+HxARu9gpT0LjfkgbHVQFz8DSVBwMZbL29zhz/wo08TWoR1/m9V6/69i0vPLPDx3/ycyHL3Frc60ZbJ/zJFgzdc2HBCOuqNL/N+xPJ57RIL91Dkswl08HuIpimHm9x3lpyNsgMYI4PAE9uFRU3ETnkax3A/mcz0uBdt5LvhEZdCVu+Bp4QgZ2IyV+1Bau8Tq5LvO9fa34vF7lq7TFCo9bfMph45jRbW0DsulroUPyIAsAPgN2tHGD1qTJXjywAzp9kJY4EHhpK98hT34px0RRtc0/1jAr7YwArcK9DGS+vVvW++UhdYd/jSotyBHYUOZRbzjhFEEqLL+JlHkJV7vmp1MW3gClaMQyjuU0Hydsa4YMD8SpkvQ3Pw9clK6hODA/hjQezN1d2HN1oVBdWlbBcWcaVKa524MjOsBSm0lkR35LxvMcFYZuK3goy/7PBc0NobvRJpsDg56FcbtExaGJAZ5BO4rVGUerYTEsld3jnZruA85Rwbq5ZgD0ZHrbNcthTYTJbZk2Z7LauV4P+xXZALkixdWgSbaQT1Q652Le1GavbSze5zf1Hkw3Y22IkTVVIqBlrT9/NEAFrT4KVzVnW3weHPDbwv0kdAlvDXTSXxyZ6xyaRiinTaIoBp+9M+b2ITev9DTf9p8sN4GCMDef1iMOcPy0HmwDEeCjDuT/D2HiWyMha0rMJktoWqcH5QLeoOZHGQvBQEOdgq6lOkzcHC94GQPeREWDUNM2LDEhFT/XrTvlhKOdu0lErq17CBMHCYHyXQHgutS5juM3uCEp4+5qLIjnCDzIrfX9tpIqNTYd6CVDs91s7pRikEZGxA4Yu1DEs4Wlt3pjo0DedT78RyKR+FrQnM7VSxVAD6lbFtLTRSDFUWzM1OHwveUGEjSpJ388EnCAdqdQ== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 4bd45423-6b15-4f37-38fe-08da8f5abdde X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2022 16:21:52.3351 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: quvUqnbFyqp2TU1/IKQSO6cFR6Me+bJ88LR/VVhql1fi9CXTlPG47BTTRcrTbCeC0NTE1wOCMehrDs6MTE1Nh0VIE2+me8vgYZJOHUSItcg= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB5848 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org There are a few Ocelot chips that contain pinctrl logic, but can be controlled externally. Specifically the VSC7511, 7512, 7513 and 7514. In the externally controlled configurations these registers are not memory-mapped. Add support for these non-memory-mapped configurations. Signed-off-by: Colin Foster Reviewed-by: Vladimir Oltean Reviewed-by: Andy Shevchenko Acked-by: Linus Walleij --- v16 * Add Andy Reviewed-by tag v15 * No changes v14 * Add Reviewed and Acked tags --- drivers/pinctrl/pinctrl-ocelot.c | 16 +++++----------- 1 file changed, 5 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index c5fd154990c8..340ca2373429 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include #include @@ -1975,7 +1976,6 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) struct ocelot_pinctrl *info; struct reset_control *reset; struct regmap *pincfg; - void __iomem *base; int ret; struct regmap_config regmap_config = { .reg_bits = 32, @@ -2004,20 +2004,14 @@ static int ocelot_pinctrl_probe(struct platform_device *pdev) "Failed to get reset\n"); reset_control_reset(reset); - base = devm_ioremap_resource(dev, - platform_get_resource(pdev, IORESOURCE_MEM, 0)); - if (IS_ERR(base)) - return PTR_ERR(base); - info->stride = 1 + (info->desc->npins - 1) / 32; regmap_config.max_register = OCELOT_GPIO_SD_MAP * info->stride + 15 * 4; - info->map = devm_regmap_init_mmio(dev, base, ®map_config); - if (IS_ERR(info->map)) { - dev_err(dev, "Failed to create regmap\n"); - return PTR_ERR(info->map); - } + info->map = ocelot_regmap_from_resource(pdev, 0, ®map_config); + if (IS_ERR(info->map)) + return dev_err_probe(dev, PTR_ERR(info->map), + "Failed to create regmap\n"); dev_set_drvdata(dev, info->map); info->dev = dev; From patchwork Mon Sep 5 16:21:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 602823 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83CE3C6FA8D for ; Mon, 5 Sep 2022 16:22:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237401AbiIEQWK (ORCPT ); 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Miller" , Russell King , Heiner Kallweit , Andrew Lunn , Krzysztof Kozlowski , Rob Herring , Lee Jones , katie.morris@in-advantage.com, Florian Fainelli Subject: [RESEND PATCH v16 mfd 4/8] pinctrl: microchip-sgpio: allow sgpio driver to be used as a module Date: Mon, 5 Sep 2022 09:21:28 -0700 Message-Id: <20220905162132.2943088-5-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220905162132.2943088-1-colin.foster@in-advantage.com> References: <20220905162132.2943088-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR04CA0263.namprd04.prod.outlook.com (2603:10b6:303:88::28) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 7e0f9bbb-de08-44af-1e9f-08da8f5abe47 X-MS-TrafficTypeDiagnostic: PH0PR10MB5848:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: nIfGt3v2+ylqeZ9izDQHzHaiIrCOXtk5rdur6claQXHVJ8yW3hCRA3qx8WGsZ5TKzTy8UklnvGjFKZkq11ZSNr/85E7FVZKar4Ndx99IetYKb0Jlz68qxBFDo3CXzA7ltBsyqpMbj/Y+H3mnKxdMcX6aD4I9hoa4pPZaVfj7MBkseElTMNwC6rM8jAdbIsAFKYNLa1WXv07Ok99K3NLn4AU3khQYRfb4KBMXvOYva6+/8Q3rfk8pZkvDB29qKXZZNwdGYUJhfEsNa/lkJKUFNJsDboHlc/s+zm+JylKGmseaeBrBhOsLL41vU+qaWhtC4tl4fxgYUyoFGC5pHH9eGaoQXG9BOvyPzLyzPaE6L5J4QQ4eCdg2/DxR2Ss2Gv58PqrlcJzUBW/VFaLBcAAhFpSlbh/zfqdZBQk2+le4OhyORyUjXU7+BqIcND2OPGkyZFfZYltEWHnMXPuG48db3bXKinSl1LD/taEoQpyOCBdWk9eP27AzZ+DsvnkjFpXQ2rjNr003X/q3C/o2RlK/i3qZ6btGWKK/AZwaxtCVfYetEh6VLfrIs30RtVsXyffawAGxyv2v2B2dh9pRfTtt9M+QUP2YkrEalecG94tW+oYgpCQlLacvtljJJIWnzsZ98zT2nlG0Y+ElLEKz+zGDUxXIJ+R1FMBXLjKZ8g3hggZipSuGjKjjFcjOaZt27LwX91NJixP3/gWE24CTfIzCyF00ODkUDBZS2I4Mv4GQGI54xNpQWDvRkiykYh7s/9OR X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MWHPR1001MB2351.namprd10.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(396003)(346002)(376002)(39830400003)(136003)(366004)(66946007)(5660300002)(8936002)(66556008)(54906003)(6486002)(41300700001)(6666004)(52116002)(186003)(2906002)(1076003)(7416002)(2616005)(44832011)(6512007)(36756003)(6506007)(316002)(83380400001)(26005)(38350700002)(38100700002)(4326008)(86362001)(66476007)(8676002)(478600001); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: KXWebID8Zsm0EBU7U5EhUPnQ1SPvle7Ei78vas6nsubC18fINTkjL8EaZtm5+4jsBLz7ZSvg/GFoyYMZufFkGnb1LE1jB7WPnv2/Fefl29+/Mx0VYdhE6UmwtoDAZsYxxd7BYkZ/E7a8UI9MnVQWq0YB8h4xL4IL6lKC+nM8JWdDqavUydDbAB8pOnuRuS6ATydXYQD93IyHqjIjf5nYN1TqKHvzBvBdPp9MjjSiM13yEsio679GwI2KWN4GvClchAjF71zOxf5ydtImNOyyM31ADGZmwajXKqFrgZejRMA+dai+HqTELUQRYX8u9ccWQ/SdsmZpP5WIzK78Xq+iARN75Zc/U/zYQc7W8vc9EjPJR2TRKZD755cshOfdhHtqD2+jKQS8GZj7260OM0VtIGs7UN0mrJ3ikFZ2FEyz0DoFx4hb+kLWj1ZETHtTNNKC+LEoL6D7YKtZx1+6WFlJJv5Xr03BXC1pujWzxvbf64qsNgr1aSHKdGHCwqTdH29XordqAiGR7pKjT5ANNpaiBs/a99/fV9PVTmh8FWmP07zbmgBm1uTv1Y9K2RklDr67b7f/RRYrpIWinFFe04m7O+dnuz2a4nyH39iiTcyFZMlYy7tpDLaHq3UQvntOuhD0qnL2WHS+hj8A3dgpIetEXTNWWCMq9fUrDICzpVGzu9q9JlKZNL+GM+q00bUFNG7mRe9PaTxUaSqsVhdA3swq7/p3oxRHZKwyrELHalKBjFUZNtfuKiA/hdaYDXKFjbdxrwhUmOJJg11qCTqjarHhtP6Q84pBmpkjehX3aOGWV2qlwBrYVAq8Hfpmb06+EwfiB5pSflx5tLw0xdHoGVOz/87tAWWDLSKWPytkGBn1KrA5zrcp1Pfn6jT8xue/K62+YWZWMznPR/M3v871klawRr/F720v3BWgj7M0lQqF3GbyGYfklWlAS9t8kmH4PNOS3Gon965ckpkT3STIsr/IeBTirrGk0o1Ts2vZ7D0NEHXFQLWvtr11OcBjxJW4xDeYeqAajHUmhy0MSAjQTv4s2QdfRuIAEvc40xkZtH8GILJxqaGUzCsbUsRmV1IYW9Va6K9dVZULfiMcMKUW7vExyT9uRIuCK50IZwDVlBRQY073h5FIURzxYdbIaKbjqKgC60P9ef1/NOdaqTUFbbzrYydALgutLA3FyH4AAHC5SayX/BAhoA5jFdcNEmNmS9SLWIomBDIqffLu3ZfrcKolzBzpZKZmehT/yaXFRMtJlNPa12secBG8vNqGErfNSx61bvMgceATMArnqS6XRMOYRpZ/HPdmeRA9AGUOMq7VVxqOxX7BDKUi1PQCHoAtScjK7mK79DCh156W2h/Fuuoj3gnNpzQBs8KjN5QWunCx3TMI6fnPKOqXMEiNWHLl3M+DdPuoK7bhK26CUe78XG4CXtOYn2+dbZiStohCwi4fslQSg4IboG2Y1ISUs+nniG/p6ZyQv4aslK7dx2azL3k00xZao1ASvFhxTe5Agajm0sgwUTxfzoBoA9C5esspyA9Zwxo4aYHOta/qnBZOF7fMrPx/m8YjT05r1xvj77fgFk/UtLKla2UP9uB5gBzFmliUBbVnOZwz8qPx/twZ1/i0Yg== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: 7e0f9bbb-de08-44af-1e9f-08da8f5abe47 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2022 16:21:52.9913 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: DxMwj5GgKsquFZmDZk8vPAnxkuIsDXFzgbmEQNYtqEDNUfJLjFqDw4tVGrgTX/rv4Cx/bDwa75bPjv0uGYspkg2pfuWjsdxzK8JyeJxOmIw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB5848 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org As the commit message suggests, this simply adds the ability to select SGPIO pinctrl as a module. This becomes more practical when the SGPIO hardware exists on an external chip, controlled indirectly by I2C or SPI. This commit enables that level of control. Signed-off-by: Colin Foster Reviewed-by: Linus Walleij Reviewed-by: Florian Fainelli Reviewed-by: Vladimir Oltean Reviewed-by: Andy Shevchenko --- v16 * Add Andy Reviewed-by tag v14,15 * No changes --- drivers/pinctrl/Kconfig | 5 ++++- drivers/pinctrl/pinctrl-microchip-sgpio.c | 6 +++++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 1cf74b0c42e5..d768dcf75cf1 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -292,7 +292,7 @@ config PINCTRL_MCP23S08 corresponding interrupt-controller. config PINCTRL_MICROCHIP_SGPIO - bool "Pinctrl driver for Microsemi/Microchip Serial GPIO" + tristate "Pinctrl driver for Microsemi/Microchip Serial GPIO" depends on OF depends on HAS_IOMEM select GPIOLIB @@ -310,6 +310,9 @@ config PINCTRL_MICROCHIP_SGPIO connect control signals from SFP modules and to act as an LED controller. + If compiled as a module, the module name will be + pinctrl-microchip-sgpio. + config PINCTRL_OCELOT tristate "Pinctrl driver for the Microsemi Ocelot and Jaguar2 SoCs" depends on OF diff --git a/drivers/pinctrl/pinctrl-microchip-sgpio.c b/drivers/pinctrl/pinctrl-microchip-sgpio.c index 6f55bf7d5e05..e56074b7e659 100644 --- a/drivers/pinctrl/pinctrl-microchip-sgpio.c +++ b/drivers/pinctrl/pinctrl-microchip-sgpio.c @@ -999,6 +999,7 @@ static const struct of_device_id microchip_sgpio_gpio_of_match[] = { /* sentinel */ } }; +MODULE_DEVICE_TABLE(of, microchip_sgpio_gpio_of_match); static struct platform_driver microchip_sgpio_pinctrl_driver = { .driver = { @@ -1008,4 +1009,7 @@ static struct platform_driver microchip_sgpio_pinctrl_driver = { }, .probe = microchip_sgpio_probe, }; -builtin_platform_driver(microchip_sgpio_pinctrl_driver); +module_platform_driver(microchip_sgpio_pinctrl_driver); + +MODULE_DESCRIPTION("Microchip SGPIO Pinctrl Driver"); +MODULE_LICENSE("GPL"); From patchwork Mon Sep 5 16:21:31 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 602824 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 14F40ECAAD3 for ; Mon, 5 Sep 2022 16:22:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S237142AbiIEQWH (ORCPT ); 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Signed-off-by: Colin Foster Reviewed-by: Rob Herring Reviewed-by: Vladimir Oltean --- (No changes since v14) v14 * Add Vladimir Reviewed tag --- .../devicetree/bindings/mfd/mscc,ocelot.yaml | 160 ++++++++++++++++++ MAINTAINERS | 1 + 2 files changed, 161 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml diff --git a/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml new file mode 100644 index 000000000000..8bf45a5673a4 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml @@ -0,0 +1,160 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/mscc,ocelot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Ocelot Externally-Controlled Ethernet Switch + +maintainers: + - Colin Foster + +description: | + The Ocelot ethernet switch family contains chips that have an internal CPU + (VSC7513, VSC7514) and chips that don't (VSC7511, VSC7512). All switches have + the option to be controlled externally, which is the purpose of this driver. + + The switch family is a multi-port networking switch that supports many + interfaces. Additionally, the device can perform pin control, MDIO buses, and + external GPIO expanders. + +properties: + compatible: + enum: + - mscc,vsc7512 + + reg: + maxItems: 1 + + "#address-cells": + const: 1 + + "#size-cells": + const: 1 + + spi-max-frequency: + maxItems: 1 + +patternProperties: + "^pinctrl@[0-9a-f]+$": + type: object + $ref: /schemas/pinctrl/mscc,ocelot-pinctrl.yaml + + "^gpio@[0-9a-f]+$": + type: object + $ref: /schemas/pinctrl/microchip,sparx5-sgpio.yaml + properties: + compatible: + enum: + - mscc,ocelot-sgpio + + "^mdio@[0-9a-f]+$": + type: object + $ref: /schemas/net/mscc,miim.yaml + properties: + compatible: + enum: + - mscc,ocelot-miim + +required: + - compatible + - reg + - '#address-cells' + - '#size-cells' + - spi-max-frequency + +additionalProperties: false + +examples: + - | + ocelot_clock: ocelot-clock { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + + soc@0 { + compatible = "mscc,vsc7512"; + spi-max-frequency = <2500000>; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + + mdio@7107009c { + compatible = "mscc,ocelot-miim"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7107009c 0x24>; + + sw_phy0: ethernet-phy@0 { + reg = <0x0>; + }; + }; + + mdio@710700c0 { + compatible = "mscc,ocelot-miim"; + pinctrl-names = "default"; + pinctrl-0 = <&miim1_pins>; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x710700c0 0x24>; + + sw_phy4: ethernet-phy@4 { + reg = <0x4>; + }; + }; + + gpio: pinctrl@71070034 { + compatible = "mscc,ocelot-pinctrl"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&gpio 0 0 22>; + reg = <0x71070034 0x6c>; + + sgpio_pins: sgpio-pins { + pins = "GPIO_0", "GPIO_1", "GPIO_2", "GPIO_3"; + function = "sg0"; + }; + + miim1_pins: miim1-pins { + pins = "GPIO_14", "GPIO_15"; + function = "miim"; + }; + }; + + gpio@710700f8 { + compatible = "mscc,ocelot-sgpio"; + #address-cells = <1>; + #size-cells = <0>; + bus-frequency = <12500000>; + clocks = <&ocelot_clock>; + microchip,sgpio-port-ranges = <0 15>; + pinctrl-names = "default"; + pinctrl-0 = <&sgpio_pins>; + reg = <0x710700f8 0x100>; + + sgpio_in0: gpio@0 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <0>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <64>; + }; + + sgpio_out1: gpio@1 { + compatible = "microchip,sparx5-sgpio-bank"; + reg = <1>; + gpio-controller; + #gpio-cells = <3>; + ngpios = <64>; + }; + }; + }; + }; + +... + diff --git a/MAINTAINERS b/MAINTAINERS index e0732e9f9090..a5df3b0b9601 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14744,6 +14744,7 @@ F: tools/testing/selftests/drivers/net/ocelot/* OCELOT EXTERNAL SWITCH CONTROL M: Colin Foster S: Supported +F: Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml F: include/linux/mfd/ocelot.h OCXL (Open Coherent Accelerator Processor Interface OpenCAPI) DRIVER From patchwork Mon Sep 5 16:21:32 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Colin Foster X-Patchwork-Id: 602822 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72A83C6FA83 for ; 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Miller" , Russell King , Heiner Kallweit , Andrew Lunn , Krzysztof Kozlowski , Rob Herring , Lee Jones , katie.morris@in-advantage.com Subject: [RESEND PATCH v16 mfd 8/8] mfd: ocelot: add support for the vsc7512 chip via spi Date: Mon, 5 Sep 2022 09:21:32 -0700 Message-Id: <20220905162132.2943088-9-colin.foster@in-advantage.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220905162132.2943088-1-colin.foster@in-advantage.com> References: <20220905162132.2943088-1-colin.foster@in-advantage.com> X-ClientProxiedBy: MW4PR04CA0263.namprd04.prod.outlook.com (2603:10b6:303:88::28) To MWHPR1001MB2351.namprd10.prod.outlook.com (2603:10b6:301:35::37) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: f84f4755-003a-41a0-8c1e-08da8f5ac002 X-MS-TrafficTypeDiagnostic: PH0PR10MB5848:EE_ X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: miNQOexZu5k9HVXK3s/SKUD3vQf56nzoGOayFdu0TeqyxUnuhTqF/4cOlJU+FIAXvFpnVHcxLRJudvxtzGAc10y/3SpLMSlvDg/xO/72JFfXFytTSbqhdXErVG0YcEDjLGDtUebQgo4ASPI3nR86PE/7ucgdUNK40Js9nDFaZ8Tg7bP3sJVWbYe/3kZl8tU72F7o/2ctm6G1+uCYNzi1HpRyHtl+drSHWFack4VAWgKmTNiXZI7v8w2R5F1y2sYzdgWNaeYp8nbLeN3tmVY5llFp43mWo4HmAOnxpSfbIavguwxaScuR0WMHl3pdDIv2UR3PncS2JWcSN/wKmeVoUlKnsP9IqqQbxewpWOz938sx8I+DIoXEuNx6wi3DeiO4xRJO8KpAH9NnYgLu0VPPH7/hFwwYPeTbBkAuLcff9w5+OkmoR5MD4fQRCethAq4BUUsTs0WmkSLb4mFKY1ZxP7ZnnCvCPeUdhey8aml7qob8sfXZpDRGTiItlK8n9wWKAJy9t/2R8Rz9tmiYDbq+oQTqaxTDprtNdvw9NmeosB5VO/83ihp4WTPKz/Px07z1KSC22criv7QtVVJ3U0/RdXxmHDt+PuUa5T1tfMuJqvmU9Z1ssnBOEAiMC9uPLRK9MhyDQL1gYMPIm3LpJIUQ1aleG0meFS5F7oAHKmGOD9VHVaByMtQYInnWgSe2B/a6QI7uC9uoFBRRwNuLJ8+L5/kg34Xv/IxP7ExTc1CNkmDt73vSYzpX5tYpLDNfEX4B X-Forefront-Antispam-Report: CIP:255.255.255.255; CTRY:; LANG:en; SCL:1; SRV:; IPV:NLI; SFV:NSPM; H:MWHPR1001MB2351.namprd10.prod.outlook.com; PTR:; CAT:NONE; SFS:(13230016)(396003)(346002)(376002)(39830400003)(136003)(366004)(66946007)(5660300002)(8936002)(66556008)(54906003)(6486002)(41300700001)(6666004)(107886003)(52116002)(30864003)(186003)(2906002)(1076003)(7416002)(2616005)(44832011)(6512007)(36756003)(6506007)(316002)(83380400001)(26005)(38350700002)(38100700002)(4326008)(86362001)(66476007)(8676002)(478600001); DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: hYzcvizrOvQrewjkZrmo8nLBc0ZM3EHGWmaN80fuyEoYi4iec5RNpNGLrQjuENpZYNI9nQiLoI63yVTohUZVIaLeszrtrQDIo1eH7YW35bmNjAK0LpOYQ3dJHBOOuyJbRZYlmGzwCjxKyCeauGgGewhDE+2aRRIeKp0mK2ChFru/FYkL7ZIZY332S6jO4/FNuRCLLsVPK/yxm1eEA0EIv6Z3OftAcDJx1N7za+OnEro1ERW6shD0ueMbIahC1tpJrXjSs2N9jmOeHh1lAwASgftzijIRjC9Gnqa06iTfLc0zFTxc9JJHlCO1kC6Z/iUpRw8mHD2KX7RgbNAvpgyrTKoF1bljJzk16geJzL6/Zwc+aEfttxMgvsntrfT8RdR87DToEfFQoDCsxJEfCci5QFy2kGgHCa6BpIXVK93nHdDjfMSoHspTyfwY9qMLXFD9JliSRS7bfJqMimLBpT4H0OVYcOKv+FMSmdBobi3M9rESdJj2iwXxvi1mXDafbz9K2CjZWCibxRWJeaFkPlsMRt+zm2/GHV/i3+LRFw44WmSIgK0uMCSdAxUHApvQiPmaHl1EckSaPFSUeD+C6WgJzvqyl66nTt66AO+H2j9M8KgkCWNH6wm24JLAEgeUO2PS8+2qjVoa7/orYghOT5Jzq5wOf3Disb+7LUzM5ModiK8IlfXGpm434SlvwFR1JPVHWUO3Pn9qPAlI3N812VXai2acmOVRKJr5r/HbdOp9hF/Fxz8xgcBlx0Th6UzbVQEidIoXc6mpRHC8RSWohzEIl++FIILi3dUSTMuTIltu054q5njaG6v7XgTYJnDQ4NkVlw318k+lLrqzFWSFBXX4lIg4f79CJ7+MSriygUFKbslEjqfcrexp1bqo5mlB8FaDlkVfv3vSgG/leAjExWMbNP8pZbpLNc5M49JRplLTg3nfNvn0ztvnM2I5YA+dabk9DqcBBih4AORjmaDWD2ytuagTIM6ry6ll57sHIG4QS2HuR7iHPeURWsy7o/DK0CG03btD7o9n2+C5uqFyvQSmgbPASusB21pwuMvLhe4h+QXTjoifYyrjN+EG10atpxKGDVVB+Pu0oGlDs0NAG5vhLIHU4w+7ArSjyXN3lTDZZSJ+6FqakLwTZxv3CK17j/DtnQNKX9rQSJvPKSLm0hfZzTcKMD9ELc0F9WTAhXc+DaSFPE83kDOFDT+WBgqEQ9A7anh5bxAZqHyTXnxEpBUrOMFOuHZM9xzN17VF/bVijykCkqSa9uAPQUiDZfNvbX0FnWPW3EtKQchrjBJQYCdnUbt+9OzlE1CNVIyVG6K7IHgFBcOKE9VIMcs+xPVlS9Kczwi/BuEs5zlLnJrKd/xvLNmhf0dPUdabLKDEezRX1c6xKalePsZzkKjhNYwRC+wIRFoSA3JlvENQlQkqzpCwS1EfnR/0dETdnxW4PVowLQXDFe2xYebLGfTrAOP8z+xFHuYoHXSFsbC2LtXm5ZPX5xoKl/5JjYOzmhJSEweI47tS41W7un6xhygPK65d29cmFxsN8L8wrdFt1chf50XyYjOxRNB7DHvimq8jpxhaI9XcFKJIcuokdflCfdGbkmtwbQcDuLYtQwqi4ucxkgnWzQ== X-OriginatorOrg: in-advantage.com X-MS-Exchange-CrossTenant-Network-Message-Id: f84f4755-003a-41a0-8c1e-08da8f5ac002 X-MS-Exchange-CrossTenant-AuthSource: MWHPR1001MB2351.namprd10.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Sep 2022 16:21:55.9754 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 48e842ca-fbd8-4633-a79d-0c955a7d3aae X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 65XStQiSuhHoAfX0r8r79pmuSe3GQ97Q7Z/d3drcBHwWMEAW914Ol1z8Dwli4lP63BrMcOA6zn0bN57FCDxFqvxo2uwGn5wZ1w9tKNa2yh4= X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR10MB5848 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The VSC7512 is a networking chip that contains several peripherals. Many of these peripherals are currently supported by the VSC7513 and VSC7514 chips, but those run on an internal CPU. The VSC7512 lacks this CPU, and must be controlled externally. Utilize the existing drivers by referencing the chip as an MFD. Add support for the two MDIO buses, the internal phys, pinctrl, and serial GPIO. Signed-off-by: Colin Foster Reviewed-by: Vladimir Oltean --- v16 * Includes fixups: * ocelot-core.c add includes device.h, export.h, iopoll.h, ioport,h * ocelot-spi.c add includes device.h, err.h, errno.h, export.h, mod_devicetable.h, types.h * Move kconfig.h from ocelot-spi.c to ocelot.h * Remove unnecessary byteorder.h * Utilize resource_size() function v15 * Add missed include bits.h * Clean _SIZE macros to make them all the same width (e.g. 0x004) * Remove unnecessary ret = ...; return ret; calls * Utilize spi_message_init_with_transfers() instead of spi_message_add_tail() calls in the bus_read routine * Utilize HZ_PER_MHZ from units.h instead of a magic number * Remove unnecessary err < 0 checks * Fix typos in comments v14 * Add Reviewed tag * Copyright ranges are now "2021-2022" * 100-char width applied instead of 80 * Remove invalid dev_err_probe return * Remove "spi" and "dev" elements from ocelot_ddata struct. Since "dev" is available throughout, determine "ddata" and "spi" from there instead of keeping separate references. * Add header guard in drivers/mfd/ocelot.h * Document ocelot_ddata struct --- MAINTAINERS | 1 + drivers/mfd/Kconfig | 21 +++ drivers/mfd/Makefile | 3 + drivers/mfd/ocelot-core.c | 161 ++++++++++++++++++++ drivers/mfd/ocelot-spi.c | 299 ++++++++++++++++++++++++++++++++++++++ drivers/mfd/ocelot.h | 49 +++++++ 6 files changed, 534 insertions(+) create mode 100644 drivers/mfd/ocelot-core.c create mode 100644 drivers/mfd/ocelot-spi.c create mode 100644 drivers/mfd/ocelot.h diff --git a/MAINTAINERS b/MAINTAINERS index a5df3b0b9601..90a873dd04b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14745,6 +14745,7 @@ OCELOT EXTERNAL SWITCH CONTROL M: Colin Foster S: Supported F: Documentation/devicetree/bindings/mfd/mscc,ocelot.yaml +F: drivers/mfd/ocelot* F: include/linux/mfd/ocelot.h OCXL (Open Coherent Accelerator Processor Interface OpenCAPI) DRIVER diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index abb58ab1a1a4..c3dd1fe8d8c9 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -963,6 +963,27 @@ config MFD_MENF21BMC This driver can also be built as a module. If so the module will be called menf21bmc. +config MFD_OCELOT + tristate "Microsemi Ocelot External Control Support" + depends on SPI_MASTER + select MFD_CORE + select REGMAP_SPI + help + Ocelot is a family of networking chips that support multiple ethernet + and fibre interfaces. In addition to networking, they contain several + other functions, including pinctrl, MDIO, and communication with + external chips. While some chips have an internal processor capable of + running an OS, others don't. All chips can be controlled externally + through different interfaces, including SPI, I2C, and PCIe. + + Say yes here to add support for Ocelot chips (VSC7511, VSC7512, + VSC7513, VSC7514) controlled externally. + + To compile this driver as a module, choose M here: the module will be + called ocelot-soc. + + If unsure, say N. + config EZX_PCAP bool "Motorola EZXPCAP Support" depends on SPI_MASTER diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 858cacf659d6..0004b7e86220 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -120,6 +120,9 @@ obj-$(CONFIG_MFD_MC13XXX_I2C) += mc13xxx-i2c.o obj-$(CONFIG_MFD_CORE) += mfd-core.o +ocelot-soc-objs := ocelot-core.o ocelot-spi.o +obj-$(CONFIG_MFD_OCELOT) += ocelot-soc.o + obj-$(CONFIG_EZX_PCAP) += ezx-pcap.o obj-$(CONFIG_MFD_CPCAP) += motorola-cpcap.o diff --git a/drivers/mfd/ocelot-core.c b/drivers/mfd/ocelot-core.c new file mode 100644 index 000000000000..1816d52c65c5 --- /dev/null +++ b/drivers/mfd/ocelot-core.c @@ -0,0 +1,161 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Core driver for the Ocelot chip family. + * + * The VSC7511, 7512, 7513, and 7514 can be controlled internally via an + * on-chip MIPS processor, or externally via SPI, I2C, PCIe. This core driver is + * intended to be the bus-agnostic glue between, for example, the SPI bus and + * the child devices. + * + * Copyright 2021-2022 Innovative Advantage Inc. + * + * Author: Colin Foster + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +#include "ocelot.h" + +#define REG_GCB_SOFT_RST 0x0008 + +#define BIT_SOFT_CHIP_RST BIT(0) + +#define VSC7512_MIIM0_RES_START 0x7107009c +#define VSC7512_MIIM1_RES_START 0x710700c0 +#define VSC7512_MIIM_RES_SIZE 0x024 + +#define VSC7512_PHY_RES_START 0x710700f0 +#define VSC7512_PHY_RES_SIZE 0x004 + +#define VSC7512_GPIO_RES_START 0x71070034 +#define VSC7512_GPIO_RES_SIZE 0x06c + +#define VSC7512_SIO_CTRL_RES_START 0x710700f8 +#define VSC7512_SIO_CTRL_RES_SIZE 0x100 + +#define VSC7512_GCB_RST_SLEEP_US 100 +#define VSC7512_GCB_RST_TIMEOUT_US 100000 + +static int ocelot_gcb_chip_rst_status(struct ocelot_ddata *ddata) +{ + int val, err; + + err = regmap_read(ddata->gcb_regmap, REG_GCB_SOFT_RST, &val); + if (err) + return err; + + return val; +} + +int ocelot_chip_reset(struct device *dev) +{ + struct ocelot_ddata *ddata = dev_get_drvdata(dev); + int ret, val; + + /* + * Reset the entire chip here to put it into a completely known state. + * Other drivers may want to reset their own subsystems. The register + * self-clears, so one write is all that is needed and wait for it to + * clear. + */ + ret = regmap_write(ddata->gcb_regmap, REG_GCB_SOFT_RST, BIT_SOFT_CHIP_RST); + if (ret) + return ret; + + return readx_poll_timeout(ocelot_gcb_chip_rst_status, ddata, val, !val, + VSC7512_GCB_RST_SLEEP_US, VSC7512_GCB_RST_TIMEOUT_US); +} +EXPORT_SYMBOL_NS(ocelot_chip_reset, MFD_OCELOT); + +static const struct resource vsc7512_miim0_resources[] = { + DEFINE_RES_REG_NAMED(VSC7512_MIIM0_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim0"), + DEFINE_RES_REG_NAMED(VSC7512_PHY_RES_START, VSC7512_PHY_RES_SIZE, "gcb_phy"), +}; + +static const struct resource vsc7512_miim1_resources[] = { + DEFINE_RES_REG_NAMED(VSC7512_MIIM1_RES_START, VSC7512_MIIM_RES_SIZE, "gcb_miim1"), +}; + +static const struct resource vsc7512_pinctrl_resources[] = { + DEFINE_RES_REG_NAMED(VSC7512_GPIO_RES_START, VSC7512_GPIO_RES_SIZE, "gcb_gpio"), +}; + +static const struct resource vsc7512_sgpio_resources[] = { + DEFINE_RES_REG_NAMED(VSC7512_SIO_CTRL_RES_START, VSC7512_SIO_CTRL_RES_SIZE, "gcb_sio"), +}; + +static const struct mfd_cell vsc7512_devs[] = { + { + .name = "ocelot-pinctrl", + .of_compatible = "mscc,ocelot-pinctrl", + .num_resources = ARRAY_SIZE(vsc7512_pinctrl_resources), + .resources = vsc7512_pinctrl_resources, + }, { + .name = "ocelot-sgpio", + .of_compatible = "mscc,ocelot-sgpio", + .num_resources = ARRAY_SIZE(vsc7512_sgpio_resources), + .resources = vsc7512_sgpio_resources, + }, { + .name = "ocelot-miim0", + .of_compatible = "mscc,ocelot-miim", + .of_reg = VSC7512_MIIM0_RES_START, + .use_of_reg = true, + .num_resources = ARRAY_SIZE(vsc7512_miim0_resources), + .resources = vsc7512_miim0_resources, + }, { + .name = "ocelot-miim1", + .of_compatible = "mscc,ocelot-miim", + .of_reg = VSC7512_MIIM1_RES_START, + .use_of_reg = true, + .num_resources = ARRAY_SIZE(vsc7512_miim1_resources), + .resources = vsc7512_miim1_resources, + }, +}; + +static void ocelot_core_try_add_regmap(struct device *dev, + const struct resource *res) +{ + if (dev_get_regmap(dev, res->name)) + return; + + ocelot_spi_init_regmap(dev, res); +} + +static void ocelot_core_try_add_regmaps(struct device *dev, + const struct mfd_cell *cell) +{ + int i; + + for (i = 0; i < cell->num_resources; i++) + ocelot_core_try_add_regmap(dev, &cell->resources[i]); +} + +int ocelot_core_init(struct device *dev) +{ + int i, ndevs; + + ndevs = ARRAY_SIZE(vsc7512_devs); + + for (i = 0; i < ndevs; i++) + ocelot_core_try_add_regmaps(dev, &vsc7512_devs[i]); + + return devm_mfd_add_devices(dev, PLATFORM_DEVID_AUTO, vsc7512_devs, ndevs, NULL, 0, NULL); +} +EXPORT_SYMBOL_NS(ocelot_core_init, MFD_OCELOT); + +MODULE_DESCRIPTION("Externally Controlled Ocelot Chip Driver"); +MODULE_AUTHOR("Colin Foster "); +MODULE_LICENSE("GPL"); +MODULE_IMPORT_NS(MFD_OCELOT_SPI); diff --git a/drivers/mfd/ocelot-spi.c b/drivers/mfd/ocelot-spi.c new file mode 100644 index 000000000000..0f097f4829d1 --- /dev/null +++ b/drivers/mfd/ocelot-spi.c @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * SPI core driver for the Ocelot chip family. + * + * This driver will handle everything necessary to allow for communication over + * SPI to the VSC7511, VSC7512, VSC7513 and VSC7514 chips. The main functions + * are to prepare the chip's SPI interface for a specific bus speed, and a host + * processor's endianness. This will create and distribute regmaps for any + * children. + * + * Copyright 2021-2022 Innovative Advantage Inc. + * + * Author: Colin Foster + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ocelot.h" + +#define REG_DEV_CPUORG_IF_CTRL 0x0000 +#define REG_DEV_CPUORG_IF_CFGSTAT 0x0004 + +#define CFGSTAT_IF_NUM_VCORE (0 << 24) +#define CFGSTAT_IF_NUM_VRAP (1 << 24) +#define CFGSTAT_IF_NUM_SI (2 << 24) +#define CFGSTAT_IF_NUM_MIIM (3 << 24) + +#define VSC7512_DEVCPU_ORG_RES_START 0x71000000 +#define VSC7512_DEVCPU_ORG_RES_SIZE 0x38 + +#define VSC7512_CHIP_REGS_RES_START 0x71070000 +#define VSC7512_CHIP_REGS_RES_SIZE 0x14 + +static const struct resource vsc7512_dev_cpuorg_resource = + DEFINE_RES_REG_NAMED(VSC7512_DEVCPU_ORG_RES_START, + VSC7512_DEVCPU_ORG_RES_SIZE, + "devcpu_org"); + +static const struct resource vsc7512_gcb_resource = + DEFINE_RES_REG_NAMED(VSC7512_CHIP_REGS_RES_START, + VSC7512_CHIP_REGS_RES_SIZE, + "devcpu_gcb_chip_regs"); + +static int ocelot_spi_initialize(struct device *dev) +{ + struct ocelot_ddata *ddata = dev_get_drvdata(dev); + u32 val, check; + int err; + + val = OCELOT_SPI_BYTE_ORDER; + + /* + * The SPI address must be big-endian, but we want the payload to match + * our CPU. These are two bits (0 and 1) but they're repeated such that + * the write from any configuration will be valid. The four + * configurations are: + * + * 0b00: little-endian, MSB first + * | 111111 | 22221111 | 33222222 | + * | 76543210 | 54321098 | 32109876 | 10987654 | + * + * 0b01: big-endian, MSB first + * | 33222222 | 22221111 | 111111 | | + * | 10987654 | 32109876 | 54321098 | 76543210 | + * + * 0b10: little-endian, LSB first + * | 111111 | 11112222 | 22222233 | + * | 01234567 | 89012345 | 67890123 | 45678901 | + * + * 0b11: big-endian, LSB first + * | 22222233 | 11112222 | 111111 | | + * | 45678901 | 67890123 | 89012345 | 01234567 | + */ + err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CTRL, val); + if (err) + return err; + + /* + * Apply the number of padding bytes between a read request and the data + * payload. Some registers have access times of up to 1us, so if the + * first payload bit is shifted out too quickly, the read will fail. + */ + val = ddata->spi_padding_bytes; + err = regmap_write(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, val); + if (err) + return err; + + /* + * After we write the interface configuration, read it back here. This + * will verify several different things. The first is that the number of + * padding bytes actually got written correctly. These are found in bits + * 0:3. + * + * The second is that bit 16 is cleared. Bit 16 is IF_CFGSTAT:IF_STAT, + * and will be set if the register access is too fast. This would be in + * the condition that the number of padding bytes is insufficient for + * the SPI bus frequency. + * + * The last check is for bits 31:24, which define the interface by which + * the registers are being accessed. Since we're accessing them via the + * serial interface, it must return IF_NUM_SI. + */ + check = val | CFGSTAT_IF_NUM_SI; + + err = regmap_read(ddata->cpuorg_regmap, REG_DEV_CPUORG_IF_CFGSTAT, &val); + if (err) + return err; + + if (check != val) + return -ENODEV; + + return 0; +} + +static const struct regmap_config ocelot_spi_regmap_config = { + .reg_bits = 24, + .reg_stride = 4, + .reg_downshift = 2, + .val_bits = 32, + + .write_flag_mask = 0x80, + + .use_single_write = true, + .can_multi_write = false, + + .reg_format_endian = REGMAP_ENDIAN_BIG, + .val_format_endian = REGMAP_ENDIAN_NATIVE, +}; + +static int ocelot_spi_regmap_bus_read(void *context, const void *reg, size_t reg_size, + void *val, size_t val_size) +{ + struct spi_transfer xfers[3] = {0}; + struct device *dev = context; + struct ocelot_ddata *ddata; + struct spi_device *spi; + struct spi_message msg; + unsigned int index = 0; + + ddata = dev_get_drvdata(dev); + spi = to_spi_device(dev); + + xfers[index].tx_buf = reg; + xfers[index].len = reg_size; + index++; + + if (ddata->spi_padding_bytes) { + xfers[index].len = ddata->spi_padding_bytes; + xfers[index].tx_buf = ddata->dummy_buf; + xfers[index].dummy_data = 1; + index++; + } + + xfers[index].rx_buf = val; + xfers[index].len = val_size; + index++; + + spi_message_init_with_transfers(&msg, xfers, index); + + return spi_sync(spi, &msg); +} + +static int ocelot_spi_regmap_bus_write(void *context, const void *data, size_t count) +{ + struct device *dev = context; + struct spi_device *spi = to_spi_device(dev); + + return spi_write(spi, data, count); +} + +static const struct regmap_bus ocelot_spi_regmap_bus = { + .write = ocelot_spi_regmap_bus_write, + .read = ocelot_spi_regmap_bus_read, +}; + +struct regmap *ocelot_spi_init_regmap(struct device *dev, const struct resource *res) +{ + struct regmap_config regmap_config; + + memcpy(®map_config, &ocelot_spi_regmap_config, sizeof(regmap_config)); + + regmap_config.name = res->name; + regmap_config.max_register = resource_size(res) - 1; + regmap_config.reg_base = res->start; + + return devm_regmap_init(dev, &ocelot_spi_regmap_bus, dev, ®map_config); +} +EXPORT_SYMBOL_NS(ocelot_spi_init_regmap, MFD_OCELOT_SPI); + +static int ocelot_spi_probe(struct spi_device *spi) +{ + struct device *dev = &spi->dev; + struct ocelot_ddata *ddata; + struct regmap *r; + int err; + + ddata = devm_kzalloc(dev, sizeof(*ddata), GFP_KERNEL); + if (!ddata) + return -ENOMEM; + + spi_set_drvdata(spi, ddata); + + if (spi->max_speed_hz <= 500000) { + ddata->spi_padding_bytes = 0; + } else { + /* + * Calculation taken from the manual for IF_CFGSTAT:IF_CFG. + * Register access time is 1us, so we need to configure and send + * out enough padding bytes between the read request and data + * transmission that lasts at least 1 microsecond. + */ + ddata->spi_padding_bytes = 1 + (spi->max_speed_hz / HZ_PER_MHZ + 2) / 8; + + ddata->dummy_buf = devm_kzalloc(dev, ddata->spi_padding_bytes, GFP_KERNEL); + if (!ddata->dummy_buf) + return -ENOMEM; + } + + spi->bits_per_word = 8; + + err = spi_setup(spi); + if (err) + return dev_err_probe(&spi->dev, err, "Error performing SPI setup\n"); + + r = ocelot_spi_init_regmap(dev, &vsc7512_dev_cpuorg_resource); + if (IS_ERR(r)) + return PTR_ERR(r); + + ddata->cpuorg_regmap = r; + + r = ocelot_spi_init_regmap(dev, &vsc7512_gcb_resource); + if (IS_ERR(r)) + return PTR_ERR(r); + + ddata->gcb_regmap = r; + + /* + * The chip must be set up for SPI before it gets initialized and reset. + * This must be done before calling init, and after a chip reset is + * performed. + */ + err = ocelot_spi_initialize(dev); + if (err) + return dev_err_probe(dev, err, "Error initializing SPI bus\n"); + + err = ocelot_chip_reset(dev); + if (err) + return dev_err_probe(dev, err, "Error resetting device\n"); + + /* + * A chip reset will clear the SPI configuration, so it needs to be done + * again before we can access any registers. + */ + err = ocelot_spi_initialize(dev); + if (err) + return dev_err_probe(dev, err, "Error initializing SPI bus after reset\n"); + + err = ocelot_core_init(dev); + if (err) + return dev_err_probe(dev, err, "Error initializing Ocelot core\n"); + + return 0; +} + +static const struct spi_device_id ocelot_spi_ids[] = { + { "vsc7512", 0 }, + { } +}; + +static const struct of_device_id ocelot_spi_of_match[] = { + { .compatible = "mscc,vsc7512" }, + { } +}; +MODULE_DEVICE_TABLE(of, ocelot_spi_of_match); + +static struct spi_driver ocelot_spi_driver = { + .driver = { + .name = "ocelot-soc", + .of_match_table = ocelot_spi_of_match, + }, + .id_table = ocelot_spi_ids, + .probe = ocelot_spi_probe, +}; +module_spi_driver(ocelot_spi_driver); + +MODULE_DESCRIPTION("SPI Controlled Ocelot Chip Driver"); +MODULE_AUTHOR("Colin Foster "); +MODULE_LICENSE("Dual MIT/GPL"); +MODULE_IMPORT_NS(MFD_OCELOT); diff --git a/drivers/mfd/ocelot.h b/drivers/mfd/ocelot.h new file mode 100644 index 000000000000..b8bc2f1486e2 --- /dev/null +++ b/drivers/mfd/ocelot.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0 OR MIT */ +/* Copyright 2021, 2022 Innovative Advantage Inc. */ + +#ifndef _MFD_OCELOT_H +#define _MFD_OCELOT_H + +#include + +struct device; +struct regmap; +struct resource; + +/** + * struct ocelot_ddata - Private data for an external Ocelot chip + * @gcb_regmap: General Configuration Block regmap. Used for + * operations like chip reset. + * @cpuorg_regmap: CPU Device Origin Block regmap. Used for operations + * like SPI bus configuration. + * @spi_padding_bytes: Number of padding bytes that must be thrown out before + * read data gets returned. This is calculated during + * initialization based on bus speed. + * @dummy_buf: Zero-filled buffer of spi_padding_bytes size. The dummy + * bytes that will be sent out between the address and + * data of a SPI read operation. + */ +struct ocelot_ddata { + struct regmap *gcb_regmap; + struct regmap *cpuorg_regmap; + int spi_padding_bytes; + void *dummy_buf; +}; + +int ocelot_chip_reset(struct device *dev); +int ocelot_core_init(struct device *dev); + +/* SPI-specific routines that won't be necessary for other interfaces */ +struct regmap *ocelot_spi_init_regmap(struct device *dev, + const struct resource *res); + +#define OCELOT_SPI_BYTE_ORDER_LE 0x00000000 +#define OCELOT_SPI_BYTE_ORDER_BE 0x81818181 + +#ifdef __LITTLE_ENDIAN +#define OCELOT_SPI_BYTE_ORDER OCELOT_SPI_BYTE_ORDER_LE +#else +#define OCELOT_SPI_BYTE_ORDER OCELOT_SPI_BYTE_ORDER_BE +#endif + +#endif