From patchwork Thu Sep 1 10:54:11 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 602465 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 788A8ECAAD3 for ; Thu, 1 Sep 2022 10:54:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234165AbiIAKyp (ORCPT ); Thu, 1 Sep 2022 06:54:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51310 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234154AbiIAKym (ORCPT ); Thu, 1 Sep 2022 06:54:42 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 577D31321C4 for ; Thu, 1 Sep 2022 03:54:34 -0700 (PDT) Received: by mail-pf1-x42a.google.com with SMTP id t129so17111474pfb.6 for ; Thu, 01 Sep 2022 03:54:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=JUQCoAsOqHp/dubozy2ybfyMmZNRsIHeStZD6k/cN8k=; b=pEHoyzdBfl05pa53IbQHgeW5T2Pk8XlmAmTFxk2pg4HL/nrmtoC975q8j2ZDRANdNv Co4fEWnThatHt8+F6pTwPDv4/sLtMi2cDLupK0G6zsFZd9Z2SPyy8ZAhJEwwU8Hl9ZYh msAX2J4/xLFzGPNKgh2znuo8frcPgb8APsDbgcF3G347i2VqUN/GZccYTTb9GDnawbhq 77WMY/iP53dNcAo6iSvT8BVwsox8r2g/4P70wJrbQRCQG6DrzyYew63m1jl/GIGoNkWy RhFpHtLewIltZoSklyakFdiBYNwYUa2jlrHAfy0GKdiaIFB//dMH9xfkE2814WdTL06F RFyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=JUQCoAsOqHp/dubozy2ybfyMmZNRsIHeStZD6k/cN8k=; b=ZV+k5H21c01oN7SFbtTcOYp7TbOTjxgBoPVO+UVqg9B+dbVwAq11aMl4O80zA/lzd7 THAbGn7IJrhUXk6XOLvtl5SivgTujHC0HZ9l1xB3D7H4eFDUJjsuBkOP82VbNNFeSQ1c hRR1RjzkRBZnztWBeXCzFTK+QRNFzDuBj2JHkYbYvAgFM6H2GND7rqCpX8vtRLC0xWLs h4Er/mB4QuH/GuIJVY3VVZYkiuYXI7WKwM9LQszqEFnC4sl5q7ow4VtLQ+konoqhYUEr FjIT4YphZwTSNpLnYq0JfVQ9t5rqZRnf3AGBqJlooejetUy/DL5jVza4Odz/lEGtZH6v V8Uw== X-Gm-Message-State: ACgBeo2wg5DqEakphdqOZr0O+jRhC7RQ8bd2gWTGnzu+I6vllbdJ/uPl PQdfgwax38AtSzjniG0uI3Afgg== X-Google-Smtp-Source: AA6agR42SHfyY0313yjJ+yTynSdioV4ONB04qGKCcLNFL7OWBmLXKp2Mj65GLrNmOCcD22FWobLf/Q== X-Received: by 2002:a62:1ac5:0:b0:538:3332:d531 with SMTP id a188-20020a621ac5000000b005383332d531mr19601658pfa.46.1662029673282; Thu, 01 Sep 2022 03:54:33 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:5362:8069:f46:34af:eb19]) by smtp.gmail.com with ESMTPSA id ij13-20020a170902ab4d00b0016c57657977sm13508910plb.41.2022.09.01.03.54.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 03:54:33 -0700 (PDT) From: Bhupesh Sharma To: linux-pm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, linux-arm-msm@vger.kernel.org, daniel.lezcano@linaro.org, robh+dt@kernel.org, rafael@kernel.org, Amit Kucheria , Thara Gopinath Subject: [PATCH v4 1/4] firmware: qcom: scm: Add support for tsens reinit workaround Date: Thu, 1 Sep 2022 16:24:11 +0530 Message-Id: <20220901105414.1171813-2-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220901105414.1171813-1-bhupesh.sharma@linaro.org> References: <20220901105414.1171813-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some versions of Qualcomm tsens controller might enter a 'bad state' while running stability tests causing sensor temperatures/interrupts status to be in an 'invalid' state. It is recommended to re-initialize the tsens controller via trustzone (secure registers) using scm call(s) when that happens. Add support for the same in the qcom_scm driver. Cc: Amit Kucheria Cc: Thara Gopinath Cc: linux-pm@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Bhupesh Sharma --- drivers/firmware/qcom_scm.c | 15 +++++++++++++++ drivers/firmware/qcom_scm.h | 4 ++++ include/linux/qcom_scm.h | 2 ++ 3 files changed, 21 insertions(+) diff --git a/drivers/firmware/qcom_scm.c b/drivers/firmware/qcom_scm.c index cdbfe54c8146..93adcc046a62 100644 --- a/drivers/firmware/qcom_scm.c +++ b/drivers/firmware/qcom_scm.c @@ -858,6 +858,21 @@ int qcom_scm_mem_protect_video_var(u32 cp_start, u32 cp_size, } EXPORT_SYMBOL(qcom_scm_mem_protect_video_var); +int qcom_scm_tsens_reinit(void) +{ + int ret; + const struct qcom_scm_desc desc = { + .svc = QCOM_SCM_SVC_TSENS, + .cmd = QCOM_SCM_TSENS_INIT_ID, + }; + struct qcom_scm_res res; + + ret = qcom_scm_call(__scm->dev, &desc, &res); + + return ret ? : res.result[0]; +} +EXPORT_SYMBOL(qcom_scm_tsens_reinit); + static int __qcom_scm_assign_mem(struct device *dev, phys_addr_t mem_region, size_t mem_sz, phys_addr_t src, size_t src_sz, phys_addr_t dest, size_t dest_sz) diff --git a/drivers/firmware/qcom_scm.h b/drivers/firmware/qcom_scm.h index 0d51eef2472f..5762f02dde7c 100644 --- a/drivers/firmware/qcom_scm.h +++ b/drivers/firmware/qcom_scm.h @@ -94,6 +94,10 @@ extern int scm_legacy_call(struct device *dev, const struct qcom_scm_desc *desc, #define QCOM_SCM_PIL_PAS_IS_SUPPORTED 0x07 #define QCOM_SCM_PIL_PAS_MSS_RESET 0x0a +/* TSENS Services and Function IDs */ +#define QCOM_SCM_SVC_TSENS 0x1e +#define QCOM_SCM_TSENS_INIT_ID 0x5 + #define QCOM_SCM_SVC_IO 0x05 #define QCOM_SCM_IO_READ 0x01 #define QCOM_SCM_IO_WRITE 0x02 diff --git a/include/linux/qcom_scm.h b/include/linux/qcom_scm.h index f8335644a01a..5c37e1658cef 100644 --- a/include/linux/qcom_scm.h +++ b/include/linux/qcom_scm.h @@ -124,4 +124,6 @@ extern int qcom_scm_lmh_dcvsh(u32 payload_fn, u32 payload_reg, u32 payload_val, extern int qcom_scm_lmh_profile_change(u32 profile_id); extern bool qcom_scm_lmh_dcvsh_available(void); +extern int qcom_scm_tsens_reinit(void); + #endif From patchwork Thu Sep 1 10:54:12 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 601839 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70D61ECAAD3 for ; Thu, 1 Sep 2022 10:55:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234356AbiIAKzE (ORCPT ); Thu, 1 Sep 2022 06:55:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51528 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234260AbiIAKyq (ORCPT ); Thu, 1 Sep 2022 06:54:46 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1119013286E for ; Thu, 1 Sep 2022 03:54:38 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id y29so13047902pfq.0 for ; Thu, 01 Sep 2022 03:54:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=/E3bLVpztjFs44eA5Xz7SMeGWJRyaaTq3Re2Dj7/T3M=; b=spXh+pJT5SqG5t6NTOSkq6QW5VYWjZoE8iJPYmc1RP/pmPGs6/qNdz3rukAwbyj7GG EfULhk5RoJaAZrdjybCxYfGJlIqaq9VuvINyTAPaXk3ybmZru570YQGIVMnrmtnlQF+i toclcMfr42m5YHGSC8iGfSEwVzOrMGFByIsRNdBy8bXkbSy1NpZgEMG6C4a9/HrXoUXK 2S41rL/ahfqJqfdkV7dXQhoFDUGaK4JP5MmoebYhZttM+Fj7KM66i4jrB40EhptXIpcF TzuJ6dA6BI0mXcQopbx46lDHGcQhRaxZoxZgdMn52b9G7TvcJ+dOuEgNmY7ljvsy9hur c61g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=/E3bLVpztjFs44eA5Xz7SMeGWJRyaaTq3Re2Dj7/T3M=; b=srhkkwJhIcQWs4MHmcVF29S3ULvV6QeC2LA9oQ3Tw4xWNIo2GBk7sei2aL2+C8IKU/ GWF7CjbVVk9SV2l0QDMD+ESdLZuL8bmZV1lKN5GzFOjBm/psXYKTatGdbEIjGFvKFZiO Es6NsyLh1CjOwm6JGc3sSNf50KRSws8mwBzfnxIFCjzK/nYmENAy6FTF3yXrOD0wQj49 BDrlpnnfqYETCoitNYz5E9eDTn2u+T7Hv0rCjPGhx1adOVUB5NlayEAwxY6qCllXaymN QRh7ioO9Mwj/YkwQpsyFhZU4W6iBuuLzYgYm5ZvJUMLPMyc8d2d0dbQ0cxiVla1sNugO A1XA== X-Gm-Message-State: ACgBeo2CufYiricOf04dwS1mzwMJBG76mo67AMA/wuyoMcbND4z9kOwa eNWZxsGdV1zBkc51tCSES+iopw== X-Google-Smtp-Source: AA6agR550SywU0WxvQxOEqmZLAsYRGMp1aaY9hKI+xKj95WtXCrsyB/gNQQab7KaawgAFWjFNma7fQ== X-Received: by 2002:a05:6a00:c8e:b0:52e:af2:3d4b with SMTP id a14-20020a056a000c8e00b0052e0af23d4bmr30813724pfv.76.1662029677555; Thu, 01 Sep 2022 03:54:37 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:5362:8069:f46:34af:eb19]) by smtp.gmail.com with ESMTPSA id ij13-20020a170902ab4d00b0016c57657977sm13508910plb.41.2022.09.01.03.54.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 03:54:37 -0700 (PDT) From: Bhupesh Sharma To: linux-pm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, linux-arm-msm@vger.kernel.org, daniel.lezcano@linaro.org, robh+dt@kernel.org, rafael@kernel.org, Amit Kucheria , Thara Gopinath Subject: [PATCH v4 2/4] thermal: qcom: tsens: Add hooks for supplying platform specific reinit quirks Date: Thu, 1 Sep 2022 16:24:12 +0530 Message-Id: <20220901105414.1171813-3-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220901105414.1171813-1-bhupesh.sharma@linaro.org> References: <20220901105414.1171813-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add hooks inside platform specific data which can be used by Qualcomm tsens controller(s) which might need reinitialization via trustzone. Cc: Bjorn Andersson Cc: Amit Kucheria Cc: Thara Gopinath Cc: linux-pm@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Bhupesh Sharma --- drivers/thermal/qcom/tsens.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index ba05c8233356..92787017c6ab 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -513,6 +513,7 @@ struct tsens_features { * @num_sensors: Number of sensors supported by platform * @ops: operations the tsens instance supports * @hw_ids: Subset of sensors ids supported by platform, if not the first n + * @needs_reinit_wa: tsens controller might need reinit via trustzone * @feat: features of the IP * @fields: bitfield locations */ @@ -520,6 +521,7 @@ struct tsens_plat_data { const u32 num_sensors; const struct tsens_ops *ops; unsigned int *hw_ids; + bool needs_reinit_wa; struct tsens_features *feat; const struct reg_field *fields; }; @@ -542,6 +544,7 @@ struct tsens_context { * @srot_map: pointer to SROT register address space * @tm_offset: deal with old device trees that don't address TM and SROT * address space separately + * @needs_reinit_wa: tsens controller might need reinit via trustzone * @ul_lock: lock while processing upper/lower threshold interrupts * @crit_lock: lock while processing critical threshold interrupts * @rf: array of regmap_fields used to store value of the field @@ -559,6 +562,7 @@ struct tsens_priv { struct regmap *tm_map; struct regmap *srot_map; u32 tm_offset; + bool needs_reinit_wa; /* lock for upper/lower threshold interrupts */ spinlock_t ul_lock; From patchwork Thu Sep 1 10:54:13 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 602464 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8314EECAAD3 for ; Thu, 1 Sep 2022 10:55:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234371AbiIAKzK (ORCPT ); Thu, 1 Sep 2022 06:55:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52066 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234297AbiIAKyz (ORCPT ); Thu, 1 Sep 2022 06:54:55 -0400 Received: from mail-pl1-x636.google.com (mail-pl1-x636.google.com [IPv6:2607:f8b0:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40FEC1321FA for ; Thu, 1 Sep 2022 03:54:42 -0700 (PDT) Received: by mail-pl1-x636.google.com with SMTP id d12so16722740plr.6 for ; Thu, 01 Sep 2022 03:54:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=0SHo6OixBYLl5f1CcBGhyTfpbNp9C9ObDkRBknfANgo=; b=a/Kqe3liSeaVfqTXOyiqV0v3O8IMto/n4wptEy1A99SajwLYVRNNItD1B0jwChJ7Ff AxrjJf/a715pHaDo0Oe86gZUAc6Hb5z2W3kHIsX+KVsYTo81eZ7O2jn2Gs2r4GB91A+a cEda7Ee8BOn/cQT6LkJef1wm29155Q5pIJlKIwnO+H19XUzdo8hUee0iCutE1Gj5F4s9 qqAoKXd8CMbukHfD8UPE+mH3ledgAZlndcsxt9iXLduBuTfMJSVXvSa6wZMjwVEC0OGr Y/knRMcypS+XGLe/YZD6mXqRpLEsrSGKmubeox+k6/vGm68QMJDFkArMj91G8Yy/VOsV cp6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=0SHo6OixBYLl5f1CcBGhyTfpbNp9C9ObDkRBknfANgo=; b=nnMgcocl0OzcDcXdZtjB6e8WhfunCd1xK5b/u17AmycMMHWxtix9ZWQYGI9dno3dtC EQ+AVJ8qKtCBR7HyH9eop2zTc5VD+RuNeqs2LSfCFZ0DDj3mRuCTiCBwfTS7cH6QFDLg WbghEouPtfhHNmp45DcTALXm3Yt/nLHqUW8bxq0Rsloa10duZ4EUFVPdyMNV6W9eCGe3 u9NOEtq84PVEzXsf1p0q3bMq9gRGab34eawaIJeLDcvLZjFKXooSuBlq43IEyJvrqG+l 9i+3JgJOnT7dGt3GeOQvAc0mk8xR3Vrv6S6EAaWC5jIDLXHwPqTtMcSvRWDT8KTXWUwx R2ZQ== X-Gm-Message-State: ACgBeo3uuaPV4tMWYv9b1PhXNNaQPP7eJ2jyHEkwNEKXLw2tgXy2iG// HC7fcibc+oPAn55GDtK4UDfVTg== X-Google-Smtp-Source: AA6agR5Td9OaLIjW5v+rGoMJ54Jxx+IAKemsK7IOKn71sway8bd2Xjszf7wFOOKp1PYIoGxKNRnzow== X-Received: by 2002:a17:902:6b42:b0:174:4308:ce52 with SMTP id g2-20020a1709026b4200b001744308ce52mr27682121plt.81.1662029681584; Thu, 01 Sep 2022 03:54:41 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:5362:8069:f46:34af:eb19]) by smtp.gmail.com with ESMTPSA id ij13-20020a170902ab4d00b0016c57657977sm13508910plb.41.2022.09.01.03.54.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 03:54:41 -0700 (PDT) From: Bhupesh Sharma To: linux-pm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, linux-arm-msm@vger.kernel.org, daniel.lezcano@linaro.org, robh+dt@kernel.org, rafael@kernel.org, Amit Kucheria , Thara Gopinath Subject: [PATCH v4 3/4] thermal: qcom: tsens: Add driver support for re-initialization quirk Date: Thu, 1 Sep 2022 16:24:13 +0530 Message-Id: <20220901105414.1171813-4-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220901105414.1171813-1-bhupesh.sharma@linaro.org> References: <20220901105414.1171813-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Since for some Qualcomm tsens controllers, its suggested to monitor the controller health periodically and in case an issue is detected, to re-initialize the tsens controller via trustzone, add the support for the same in the qcom tsens driver. Note that once the tsens controller is reset using scm call, all SROT and TM region registers will enter the reset mode. While all the SROT registers will be re-programmed and re-enabled in trustzone prior to the scm call exit, the TM region registers will not re-initialized in trustzone and thus need to be handled by the tsens driver. Cc: Bjorn Andersson Cc: Amit Kucheria Cc: Thara Gopinath Cc: linux-pm@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org Signed-off-by: Bhupesh Sharma --- drivers/thermal/qcom/tsens-v2.c | 3 + drivers/thermal/qcom/tsens.c | 190 ++++++++++++++++++++++++++++++++ drivers/thermal/qcom/tsens.h | 12 ++ 3 files changed, 205 insertions(+) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index b293ed32174b..f521e4479cc5 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -88,6 +88,9 @@ static const struct reg_field tsens_v2_regfields[MAX_REGFIELDS] = { /* TRDY: 1=ready, 0=in progress */ [TRDY] = REG_FIELD(TM_TRDY_OFF, 0, 0), + + /* FIRST_ROUND_COMPLETE: 1=complete, 0=not complete */ + [FIRST_ROUND_COMPLETE] = REG_FIELD(TM_TRDY_OFF, 3, 3), }; static const struct tsens_ops ops_generic_v2 = { diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index b1b10005fb28..ecf544683e73 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -594,6 +595,107 @@ static void tsens_disable_irq(struct tsens_priv *priv) regmap_field_write(priv->rf[INT_EN], 0); } +static void tsens_reenable_hw_after_scm(struct tsens_priv *priv) +{ + /* + * Re-enable watchdog, unmask the bark and + * disable cycle completion monitoring. + */ + regmap_field_write(priv->rf[WDOG_BARK_CLEAR], 1); + regmap_field_write(priv->rf[WDOG_BARK_CLEAR], 0); + regmap_field_write(priv->rf[WDOG_BARK_MASK], 0); + regmap_field_write(priv->rf[CC_MON_MASK], 1); + + /* Re-enable interrupts */ + tsens_enable_irq(priv); +} + +static int tsens_health_check_and_reinit(struct tsens_priv *priv, + int hw_id) +{ + int ret, trdy, first_round, sw_reg; + unsigned long timeout; + + /* Check early if the mutex is in locked state */ + WARN_ON(!mutex_is_locked(&priv->reinit_mutex)); + + /* First check if TRDY is SET */ + ret = regmap_field_read(priv->rf[TRDY], &trdy); + if (ret) + goto err; + + if (trdy) + return 0; /* success */ + + ret = regmap_field_read(priv->rf[FIRST_ROUND_COMPLETE], &first_round); + if (ret) + goto err; + + if (first_round) + return 0; /* success */ + + /* Wait for 2 ms for tsens controller to recover */ + ret = regmap_field_read_poll_timeout(priv->rf[FIRST_ROUND_COMPLETE], + first_round, first_round, 100, + RESET_TIMEOUT_MS * USEC_PER_MSEC); + if (ret == 0) { + dev_dbg(priv->dev, "tsens controller recovered\n"); + return 0; /* success */ + } + + if (ret) + goto err; + + spin_lock(&priv->reinit_lock); + + /* + * Invoke SCM call only if SW register write is reflecting in controller. + * Try it for 2 ms. In case that fails mark the tsens controller as + * unrecoverable. + */ + timeout = jiffies + msecs_to_jiffies(RESET_TIMEOUT_MS); + do { + ret = regmap_field_write(priv->rf[INT_EN], CRITICAL_INT_EN); + if (ret) + goto err_unlock; + + ret = regmap_field_read(priv->rf[INT_EN], &sw_reg); + if (ret) + goto err_unlock; + } while ((sw_reg & CRITICAL_INT_EN) && (time_before(jiffies, timeout))); + + if (!(sw_reg & CRITICAL_INT_EN)) { + ret = -ENOTRECOVERABLE; + goto err_unlock; + } + + /* tsens controller did not recover, proceed with SCM call to re-init it. */ + ret = qcom_scm_tsens_reinit(); + if (ret) { + dev_err(priv->dev, "tsens reinit scm call failed (%d)\n", ret); + goto err_unlock; + } + + /* + * After the SCM call, we need to re-enable the interrupts and also set + * active threshold for each sensor. + */ + tsens_reenable_hw_after_scm(priv); + + /* Notify reinit wa worker */ + queue_work(system_highpri_wq, &priv->reinit_wa_notify); + + spin_unlock(&priv->reinit_lock); + + return 0; /* success */ + +err_unlock: + spin_unlock(&priv->reinit_lock); + +err: + return ret; +} + int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp) { struct tsens_priv *priv = s->priv; @@ -607,6 +709,20 @@ int get_temp_tsens_valid(const struct tsens_sensor *s, int *temp) if (tsens_version(priv) == VER_0) goto get_temp; + /* + * For some tsens controllers, its suggested to monitor the controller + * health periodically and in case an issue is detected to reinit tsens + * controller via trustzone. + */ + if (priv->needs_reinit_wa) { + mutex_lock(&priv->reinit_mutex); + ret = tsens_health_check_and_reinit(priv, hw_id); + mutex_unlock(&priv->reinit_mutex); + + if (ret) + return ret; + } + /* Valid bit is 0 for 6 AHB clock cycles. * At 19.2MHz, 1 AHB clock is ~60ns. * We should enter this loop very, very rarely. @@ -739,6 +855,40 @@ static const struct regmap_config tsens_srot_config = { .reg_stride = 4, }; +static void __tsens_reinit_worker(struct tsens_priv *priv) +{ + int ret, temp; + unsigned int i; + struct tsens_irq_data d; + + for (i = 0; i < priv->num_sensors; i++) { + const struct tsens_sensor *s = &priv->sensor[i]; + u32 hw_id = s->hw_id; + + if (!s->tzd) + continue; + if (!tsens_threshold_violated(priv, hw_id, &d)) + continue; + + ret = get_temp_tsens_valid(s, &temp); + if (ret) { + dev_err(priv->dev, "[%u] error reading sensor during reinit\n", hw_id); + continue; + } + + tsens_read_irq_state(priv, hw_id, s, &d); + + if ((d.up_thresh < temp) || (d.low_thresh > temp)) { + dev_dbg(priv->dev, "[%u] TZ update trigger during reinit (%d mC)\n", + hw_id, temp); + thermal_zone_device_update(s->tzd, THERMAL_EVENT_UNSPECIFIED); + } else { + dev_dbg(priv->dev, "[%u] no violation during reinit (%d)\n", + hw_id, temp); + } + } +} + int __init init_common(struct tsens_priv *priv) { void __iomem *tm_base, *srot_base; @@ -860,6 +1010,14 @@ int __init init_common(struct tsens_priv *priv) goto err_put_device; } + priv->rf[FIRST_ROUND_COMPLETE] = devm_regmap_field_alloc(dev, + priv->tm_map, + priv->fields[FIRST_ROUND_COMPLETE]); + if (IS_ERR(priv->rf[FIRST_ROUND_COMPLETE])) { + ret = PTR_ERR(priv->rf[FIRST_ROUND_COMPLETE]); + goto err_put_device; + } + /* This loop might need changes if enum regfield_ids is reordered */ for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) { for (i = 0; i < priv->feat->max_sensors; i++) { @@ -1082,6 +1240,14 @@ static int tsens_register(struct tsens_priv *priv) return ret; } +static void tsens_reinit_worker_notify(struct work_struct *work) +{ + struct tsens_priv *priv = container_of(work, struct tsens_priv, + reinit_wa_notify); + + __tsens_reinit_worker(priv); +} + static int tsens_probe(struct platform_device *pdev) { int ret, i; @@ -1123,6 +1289,11 @@ static int tsens_probe(struct platform_device *pdev) priv->dev = dev; priv->num_sensors = num_sensors; + priv->needs_reinit_wa = data->needs_reinit_wa; + + if (priv->needs_reinit_wa && !qcom_scm_is_available()) + return -EPROBE_DEFER; + priv->ops = data->ops; for (i = 0; i < priv->num_sensors; i++) { if (data->hw_ids) @@ -1138,6 +1309,25 @@ static int tsens_probe(struct platform_device *pdev) if (!priv->ops || !priv->ops->init || !priv->ops->get_temp) return -EINVAL; + /* + * Reinitialization workaround is currently supported only for + * tsens controller versions v2. + * + * If incorrect platform data is passed to this effect, ignore + * the requested setting and move forward. + */ + if (priv->needs_reinit_wa && (tsens_version(priv) < VER_2_X)) { + dev_warn(dev, + "%s: Reinit quirk available only for tsens v2\n", __func__); + priv->needs_reinit_wa = false; + } + + mutex_init(&priv->reinit_mutex); + spin_lock_init(&priv->reinit_lock); + + if (priv->needs_reinit_wa) + INIT_WORK(&priv->reinit_wa_notify, tsens_reinit_worker_notify); + ret = priv->ops->init(priv); if (ret < 0) { dev_err(dev, "%s: init failed\n", __func__); diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 92787017c6ab..900d2a74d25e 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -14,9 +14,12 @@ #define SLOPE_FACTOR 1000 #define SLOPE_DEFAULT 3200 #define TIMEOUT_US 100 +#define RESET_TIMEOUT_MS 2 #define THRESHOLD_MAX_ADC_CODE 0x3ff #define THRESHOLD_MIN_ADC_CODE 0x0 +#define CRITICAL_INT_EN (BIT(2)) + #include #include #include @@ -165,6 +168,7 @@ enum regfield_ids { /* ----- TM ------ */ /* TRDY */ TRDY, + FIRST_ROUND_COMPLETE, /* INTERRUPT ENABLE */ INT_EN, /* v2+ has separate enables for crit, upper and lower irq */ /* STATUS */ @@ -564,6 +568,14 @@ struct tsens_priv { u32 tm_offset; bool needs_reinit_wa; + struct work_struct reinit_wa_notify; + + /* protects reinit related serialization */ + struct mutex reinit_mutex; + + /* lock for reinit workaround */ + spinlock_t reinit_lock; + /* lock for upper/lower threshold interrupts */ spinlock_t ul_lock; From patchwork Thu Sep 1 10:54:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bhupesh Sharma X-Patchwork-Id: 601838 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3C875ECAAD1 for ; Thu, 1 Sep 2022 10:55:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234416AbiIAKzZ (ORCPT ); Thu, 1 Sep 2022 06:55:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51556 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234339AbiIAKzD (ORCPT ); Thu, 1 Sep 2022 06:55:03 -0400 Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BB273A19F for ; Thu, 1 Sep 2022 03:54:47 -0700 (PDT) Received: by mail-pg1-x531.google.com with SMTP id 202so16019336pgc.8 for ; Thu, 01 Sep 2022 03:54:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date; bh=9Rgza/BFhiKgz5qbn9tPTsIEssmmxYhCqKqdcg+i9QY=; b=gSPF6cYdqAKPZBIfnj0ykq8qkjlihGmDcLYbY1JGovRpm98ByZ/r58JoGphkqYmn/W saR5sAJ8dhx80eN8CLs3yhUzH9aDWx+57vnNlj/pkgxDik3jNmDPd7cGoIQr0qgHJ27L z2KajvrNb9oAMZRVwKPWmlX732/E8MZVcdG4AknCEWmPfw9jvlQcXErOvqlFg3YBjrb0 T7pj/36wWglz35CHTiYG+M3Q+85w31cf9KKJUKNatDPlGuwuWz0Jzrs717RzwYtl0Jlz Robmj4WKGtZJqBchIgsSeXXc7CQ2tbc85Yk0QdH157dsOMDbKlIqtPcTbiMi6Ta/gtNv R0rw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date; bh=9Rgza/BFhiKgz5qbn9tPTsIEssmmxYhCqKqdcg+i9QY=; b=ClVO90Ryfg69ARfh2K7hli+a1t3s3dcwlCHxc7ObepHDkr5OtJVEc5sa4NuFXWPllM T3fzYtGE5SNLrF3XewLT4JyPLug5C63uSCdd8PR62iGPjYgCN24xDt/eoudUBGqjFbUJ DcUJeNaiRFiQCGZAa2qV7vSfLEbBjqagvm9QcdU859ARkkXSoAxbelLDCwZGzKDorqTi z0pcLryPBD2EYRt0p+StFzSB67bUqW18Ru/p87axKLpk0Qr44pIYfVzK9WfdMMZa6HxG +z3IIQrG0wCjnnT6jQKp28zw8HuZJVbbi2u9KV+1DJBfK7dhjr+PhdNDZj9ni93Dd0ai Hw1Q== X-Gm-Message-State: ACgBeo0mMAM0TuRzAUvG/k7wmL1SdW6Mo4q5za62biLBWnrh/zciWCeA 50+pAEUbNfo6HE53IHxQPHAigA== X-Google-Smtp-Source: AA6agR5tOEba8IL4Jg1YiwEsoVUeCfd8Ux+DLPb4woSbhcyyLTvyIkvIYPlLjgqQvWYomSPtBhYbFg== X-Received: by 2002:a63:4503:0:b0:430:48ac:6046 with SMTP id s3-20020a634503000000b0043048ac6046mr4910890pga.74.1662029685943; Thu, 01 Sep 2022 03:54:45 -0700 (PDT) Received: from localhost.localdomain ([2401:4900:1c60:5362:8069:f46:34af:eb19]) by smtp.gmail.com with ESMTPSA id ij13-20020a170902ab4d00b0016c57657977sm13508910plb.41.2022.09.01.03.54.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 01 Sep 2022 03:54:45 -0700 (PDT) From: Bhupesh Sharma To: linux-pm@vger.kernel.org Cc: bhupesh.sharma@linaro.org, bhupesh.linux@gmail.com, linux-kernel@vger.kernel.org, andersson@kernel.org, konrad.dybcio@somainline.org, linux-arm-msm@vger.kernel.org, daniel.lezcano@linaro.org, robh+dt@kernel.org, rafael@kernel.org, Amit Kucheria , Thara Gopinath Subject: [PATCH v4 4/4] thermal: qcom: tsens: Add reinit quirk support for tsens v2 controllers Date: Thu, 1 Sep 2022 16:24:14 +0530 Message-Id: <20220901105414.1171813-5-bhupesh.sharma@linaro.org> X-Mailer: git-send-email 2.37.1 In-Reply-To: <20220901105414.1171813-1-bhupesh.sharma@linaro.org> References: <20220901105414.1171813-1-bhupesh.sharma@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some Qualcomm tsens v2 controllers like those present on sm8150 SoC might require re-initialization via trustzone [via scm call(s)] when it enters a 'bad state' causing sensor temperatures/interrupts status to be in an 'invalid' state. Add hooks for the same in the qcom tsens driver. Devices requiring the same can pass the relevant compatible string in dt and the driver hook can be used accordingly. Cc: Amit Kucheria Cc: Thara Gopinath Cc: linux-pm@vger.kernel.org Cc: linux-arm-msm@vger.kernel.org Reviewed-by: Bjorn Andersson Signed-off-by: Bhupesh Sharma --- drivers/thermal/qcom/tsens-v2.c | 12 ++++++++++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 16 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index f521e4479cc5..431f17f99d34 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -104,6 +104,18 @@ struct tsens_plat_data data_tsens_v2 = { .fields = tsens_v2_regfields, }; +/* + * For some tsens v2 controllers, its suggested to monitor the + * controller health periodically and in case an issue is detected + * to reinit tsens controller via trustzone. + */ +struct tsens_plat_data data_tsens_v2_reinit = { + .ops = &ops_generic_v2, + .feat = &tsens_v2_feat, + .needs_reinit_wa = true, + .fields = tsens_v2_regfields, +}; + /* Kept around for backward compatibility with old msm8996.dtsi */ struct tsens_plat_data data_8996 = { .num_sensors = 13, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index ecf544683e73..ab8561ddedb2 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -1138,6 +1138,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,msm8996-tsens", .data = &data_8996, + }, { + .compatible = "qcom,sm8150-tsens", + .data = &data_tsens_v2_reinit, }, { .compatible = "qcom,tsens-v1", .data = &data_tsens_v1, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index 900d2a74d25e..03cc3a790972 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -607,6 +607,6 @@ extern struct tsens_plat_data data_8916, data_8939, data_8974, data_9607; extern struct tsens_plat_data data_tsens_v1, data_8976; /* TSENS v2 targets */ -extern struct tsens_plat_data data_8996, data_tsens_v2; +extern struct tsens_plat_data data_8996, data_tsens_v2_reinit, data_tsens_v2; #endif /* __QCOM_TSENS_H__ */