From patchwork Wed Aug 31 05:18:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akhil P Oommen X-Patchwork-Id: 601599 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 70BF2C0502A for ; Wed, 31 Aug 2022 05:20:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232263AbiHaFTy (ORCPT ); Wed, 31 Aug 2022 01:19:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54738 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232136AbiHaFTn (ORCPT ); Wed, 31 Aug 2022 01:19:43 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6C636B6D69; Tue, 30 Aug 2022 22:19:39 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.5/8.17.1.5) with ESMTP id 27V2Z9QN022685; Wed, 31 Aug 2022 05:19:31 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=SP4Y9BgfE42D6Oc8eIt8Kgqn2zuvP2VZ7va2Ala/Aqg=; b=U+W9sNmkGtSX6sJnf+NTLjOlqRL0UmxFQIBpsBVgC8FsHWh7p6AGV4l+W8cYNZZ5uuA7 2vzFX7y0Iyt3xNngBNT5FymNOFe0jf5fnI9hbzobqbrHoCW9aMZ28hsdfI+rkDdV9fJR gXt8OTJkuA4/Tq437ZqmvfPdWXINwEBO6KNkI7VtsP+7J4MudNRCzTrwSz2tFOSOwlEa Sz5/GD3LQkEAsR2su2mkvC8UMzDbNAgVEjS6eq6OdSV0x1rxSecqEtsnx7cLiCKqLCof 9gqhaxSoAFk1vZpfHj1H5kURqJKFuEqbfAy9eacvYse6jvzB78NdV52Um+ziqlIHG8VI Ag== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3j9jm4jy6e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 Aug 2022 05:19:30 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 27V5JTu9029657 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 31 Aug 2022 05:19:29 GMT Received: from hyd-lnxbld559.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.29; Tue, 30 Aug 2022 22:19:24 -0700 From: Akhil P Oommen To: freedreno , , , Rob Clark , Bjorn Andersson , "Stephen Boyd" , Dmitry Baryshkov , Philipp Zabel CC: Douglas Anderson , , Akhil P Oommen , Abhinav Kumar , Daniel Vetter , David Airlie , Krzysztof Kozlowski , Rob Herring , "Sean Paul" , , Subject: [PATCH v6 5/6] dt-bindings: drm/msm/gpu: Add optional resets Date: Wed, 31 Aug 2022 10:48:26 +0530 Message-ID: <20220831104741.v6.5.Ieffadd08a071a233213ced4406bf84bb5922ab9a@changeid> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1661923108-789-1-git-send-email-quic_akhilpo@quicinc.com> References: <1661923108-789-1-git-send-email-quic_akhilpo@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: qlI-h7IN-tzgvuhSARwuiqQFfjTP5XM3 X-Proofpoint-GUID: qlI-h7IN-tzgvuhSARwuiqQFfjTP5XM3 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.895,Hydra:6.0.517,FMLib:17.11.122.1 definitions=2022-08-31_03,2022-08-30_01,2022-06-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 malwarescore=0 priorityscore=1501 lowpriorityscore=0 phishscore=0 clxscore=1015 suspectscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2207270000 definitions=main-2208310025 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add an optional reference to GPUCC reset which can be used to ensure cx gdsc collapse during gpu recovery. Signed-off-by: Akhil P Oommen Acked-by: Rob Herring Acked-by: Krzysztof Kozlowski --- (no changes since v5) Changes in v5: - Nit: Remove a duplicate blank line (Krzysztof) Changes in v4: - New patch in v4 Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 3397bc3..408ed97 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -109,6 +109,12 @@ properties: For GMU attached devices a phandle to the GMU device that will control the power for the GPU. + resets: + maxItems: 1 + + reset-names: + items: + - const: cx_collapse required: - compatible