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[60.250.192.107]) by smtp.gmail.com with ESMTPSA id c78-20020a621c51000000b00536531536adsm7916841pfc.47.2022.08.29.19.22.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 29 Aug 2022 19:23:01 -0700 (PDT) From: Marvin Lin To: linux-edac@vger.kernel.org, rric@kernel.org, james.morse@arm.com, tony.luck@intel.com, mchehab@kernel.org, bp@alien8.de, robh+dt@kernel.org, linux-kernel@vger.kernel.org Cc: devicetree@vger.kernel.org, openbmc@lists.ozlabs.org, benjaminfair@google.com, yuenn@google.com, venture@google.com, KWLIU@nuvoton.com, YSCHU@nuvoton.com, JJLIU0@nuvoton.com, KFTING@nuvoton.com, avifishman70@gmail.com, tmaimon77@gmail.com, tali.perry1@gmail.com, ctcchien@nuvoton.com, kflin@nuvoton.com, Marvin Lin Subject: [PATCH v14 2/3] dt-bindings: edac: nuvoton: Add document for NPCM memory controller Date: Tue, 30 Aug 2022 10:22:37 +0800 Message-Id: <20220830022238.28379-3-milkfafa@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220830022238.28379-1-milkfafa@gmail.com> References: <20220830022238.28379-1-milkfafa@gmail.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add dt-bindings document for Nuvoton NPCM memory controller. Signed-off-by: Marvin Lin Reviewed-by: Rob Herring --- .../edac/nuvoton,npcm-memory-controller.yaml | 54 +++++++++++++++++++ 1 file changed, 54 insertions(+) create mode 100644 Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml diff --git a/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml new file mode 100644 index 000000000000..d5ef7e7a65f9 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/nuvoton,npcm-memory-controller.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/nuvoton,npcm-memory-controller.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Memory Controller Device Tree Bindings + +maintainers: + - Marvin Lin + - Stanley Chu + +description: | + The Nuvoton BMC SoC supports DDR4 memory with and without ECC (error + correction check). + + The memory controller supports single bit error correction, double bit + error detection (in-line ECC in which a section (1/8th) of the memory + device used to store data is used for ECC storage). + + Note, the bootloader must configure ECC mode for the memory controller. + +properties: + compatible: + enum: + - nuvoton,npcm750-memory-controller + - nuvoton,npcm845-memory-controller + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include + ahb { + #address-cells = <1>; + #size-cells = <1>; + mc: memory-controller@f0824000 { + compatible = "nuvoton,npcm750-memory-controller"; + reg = <0xf0824000 0x1000>; + interrupts = ; + }; + };