From patchwork Tue Aug 30 10:17:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 601673 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95E63ECAAA1 for ; Tue, 30 Aug 2022 10:20:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229768AbiH3KT6 (ORCPT ); Tue, 30 Aug 2022 06:19:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56282 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229832AbiH3KTf (ORCPT ); Tue, 30 Aug 2022 06:19:35 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4AA9D19C0B; Tue, 30 Aug 2022 03:18:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661854713; x=1693390713; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jmjzFPLTzirPRRdjytSXcGvB/NkyTEAOoOOffWQqE6s=; b=NRZ8pY7dWFjAVOZl1dAHk/ktqrD2g+p77OAnJ0k6jxsGGqC8cJ1oisZz 1RxYez0a5kOFSBTisuAeXPD7vBuBDpbzR6JYNnhXmTroqF841xZXKclSX P/umemBQtIwBJTTJGJzPpWk7wkRQ+oaAQ1DnZLasTcblPdvpE/MpQtr2R abSQkKSfV+cAztrRDDOQm40mC+yMn+SXeVzFQcQhPVj4ILGJCqEGtuqJx mvOhxjs4UHYGxcSOASpxLfjU897tQ1WOaT6frbX71A4uoVkcCQBKwA78l eLZAJyj8I4Vb/tsbDoBdvRAYgx3eQKvzgvHdkG4KUx9tFXaKWjALkG6cH g==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="174786760" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:18:32 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:18:31 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:18:28 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , , Krzysztof Kozlowski Subject: [PATCH v2 1/9] dt-bindings: riscv: microchip: document icicle reference design Date: Tue, 30 Aug 2022 11:17:56 +0100 Message-ID: <20220830101803.1456180-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830101803.1456180-1-conor.dooley@microchip.com> References: <20220830101803.1456180-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The icicle kit reference design's v2022.09 release,made some changes to the memory map - including adding the ability to read the fabric clock controllers via the system controller bus & making the PCI controller work with upstream Linux. While the PCI was not working in the v2022.03 design, so nothing is broken there in terms of backwards compatibility, the fabric clocks used in the v2022.03 design were chosen by the individual run of the synthesis tool. In the v2022.09 reference design, the clocks are fixed to use the "north west" fabric Clock Conditioning Circuitry. Make use of a new compatible to denote that this is not backwards compatible. Acked-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- .../devicetree/bindings/riscv/microchip.yaml | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 1aa7336a9672..485981fbfb4b 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -17,12 +17,18 @@ properties: $nodename: const: '/' compatible: - items: - - enum: - - microchip,mpfs-icicle-kit - - microchip,mpfs-icicle-reference-rtlv2203 - - sundance,polarberry - - const: microchip,mpfs + oneOf: + - items: + - enum: + - microchip,mpfs-icicle-reference-rtlv2203 + - microchip,mpfs-icicle-reference-rtlv2209 + - const: microchip,mpfs-icicle-kit + - const: microchip,mpfs + + - items: + - enum: + - sundance,polarberry + - const: microchip,mpfs additionalProperties: true From patchwork Tue Aug 30 10:17:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 601230 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BEF93C0502A for ; Tue, 30 Aug 2022 10:20:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229749AbiH3KUA (ORCPT ); Tue, 30 Aug 2022 06:20:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53036 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229834AbiH3KTf (ORCPT ); Tue, 30 Aug 2022 06:19:35 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5CCCE1A049; Tue, 30 Aug 2022 03:18:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661854717; x=1693390717; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=OZeyJFPA/WvLA6ncVrroRoLSUAxTbB6g0Lz4fVqf+F4=; b=2qN9N1c5UREEHBVd49TesAhyp+DCKFVefxii+qN13KGhQX+mgSSPTuzJ 35TqNqK33mM/C85JKN5dkvLRfyHRoDOiW/4QenubqS5nr+qtFAn+KsmSf K0pMDE5AFQzlNE6PcppW2g+87oB3zHamZdvin88Ti1ydalFpO8CrsRjJ5 ec4jwswRVrXWmCOcd3l5snJzFg4TeZJW1u9SHf5JzJ4ZnvAUwkrPEgELo VCq1bbRD8UFQqeZq9S5d1GMGp3n3c2acFZQcUuB2u8KIkZ8SxQ2MDJpkY RkgTlXMQzXNvPuULBjvl4TzKiv7XW0ShvVUW7Cm1dLfTf5uwk7/s4/FFz g==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="174786766" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:18:36 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:18:34 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:18:31 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v2 2/9] dt-bindings: riscv: microchip: document the aries m100pfsevp Date: Tue, 30 Aug 2022 11:17:57 +0100 Message-ID: <20220830101803.1456180-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830101803.1456180-1-conor.dooley@microchip.com> References: <20220830101803.1456180-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatibles for both configurations of the Aries Embedded M100PFSEVP SOM + EVK platform. Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 485981fbfb4b..04ebd48caaa7 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -27,9 +27,12 @@ properties: - items: - enum: + - aries,m100pfsevp-emmc + - aries,m100pfsevp-sdcard - sundance,polarberry - const: microchip,mpfs + additionalProperties: true ... From patchwork Tue Aug 30 10:17:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 601672 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AF75C0502E for ; Tue, 30 Aug 2022 10:20:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229812AbiH3KUA (ORCPT ); Tue, 30 Aug 2022 06:20:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54928 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229837AbiH3KTf (ORCPT ); Tue, 30 Aug 2022 06:19:35 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4E929165AB; Tue, 30 Aug 2022 03:18:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661854718; x=1693390718; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TR46wwbk70LqsH/TntWu/z4cAhBybgWj960ITKppR4k=; b=us7BZXvLfSEqeDCEPb69/BHXhXktzZzTIbWTaGkF8aMNq4OYYhKaXCaN UP/XWjSYazE7m2OVmpt9wTQX1NIQ+Qm6+/PESwE0RSUtGiPKZiReMMn8N ev3OJaZLqHzm2HS/1+cxW1Bu3HocbRN+NDMK6fAc3jIP6u86FwYrvRJym GVXyrlHb0oGLV4PETrLcupG+cerQYxse3aHN1DiH/PxQZD43tFYbMbHVN It3pziNSMsOhrghWENJirp9aCMveNRzSkAzJPpI10pVpm71CGTiPYcMz5 aFPt3YsM/qc3UmUeakpUsyaVg4lso/WIorUZLt1TUuFPyAwesTkTq+IzG w==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="174786778" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:18:37 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:18:37 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:18:34 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , , Krzysztof Kozlowski Subject: [PATCH v2 3/9] dt-bindings: riscv: microchip: document the sev kit Date: Tue, 30 Aug 2022 11:17:58 +0100 Message-ID: <20220830101803.1456180-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830101803.1456180-1-conor.dooley@microchip.com> References: <20220830101803.1456180-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Shravan Chippa Update devicetree bindings document with PolarFire SoC Video Kit, known by its "sev-kit" product code. Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Shravan Chippa Reviewed-by: Krzysztof Kozlowski Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/microchip.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 04ebd48caaa7..f8b9a3288437 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -29,10 +29,10 @@ properties: - enum: - aries,m100pfsevp-emmc - aries,m100pfsevp-sdcard + - microchip,mpfs-sev-kit - sundance,polarberry - const: microchip,mpfs - additionalProperties: true ... From patchwork Tue Aug 30 10:17:59 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 601671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9AA13C0502A for ; Tue, 30 Aug 2022 10:20:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229798AbiH3KUD (ORCPT ); Tue, 30 Aug 2022 06:20:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53004 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229826AbiH3KTg (ORCPT ); Tue, 30 Aug 2022 06:19:36 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98DD73889; Tue, 30 Aug 2022 03:18:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661854723; x=1693390723; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hyLDKbNNI38wXrC5Tei7bV2mB9uLlpphPD5ViUjlS80=; b=00y3xTx1HNyOyT+ygH1do5n1a6LAxDpMLi4RUtBN0cKD64AahsJ5D5cZ 9XNe5jHuuA4isNMzQXz4a/iVjZ6t2c0rJ9OeLkSyv5m0+hVgP1Iq7JOI/ vFz/OSy23Hvm3mBerbibiUOEfR1hl+P7J9+RnLTtT+PsVZU6M9ECkgZ3r hLXsqFYIAS1QKGuqx6OzNP+SwtiwT8WSOk2NaDOlVIbOfpRPIjYpRCwzu 9SV/F4jhgJ/d4czWeZEo8lpv1G5goYpefDEoCURVIELI6oyn1Qg9fOUJu Rqz54siisry4cWe0F14cDdtQ+gw+MJ5Ck8ePfooXZuBrEw0wW0sNwM31H g==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="174786788" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:18:43 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:18:40 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:18:37 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v2 4/9] riscv: dts: microchip: add pci dma ranges for the icicle kit Date: Tue, 30 Aug 2022 11:17:59 +0100 Message-ID: <20220830101803.1456180-5-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830101803.1456180-1-conor.dooley@microchip.com> References: <20220830101803.1456180-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The recently removed, accidentally included, "matr0" property was used in place of a dma-ranges property. The PCI controller is non-functional with mainline Linux in the v2022.02 or later reference designs and has not worked without configuration of address-translation since v2021.08. Add the address translation that will be used by the v2022.09 reference design & update the compatible used by the dts. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 7 ++++++- arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts | 3 ++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 0d28858b83f2..c0fb9dd7b2c8 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,7 +2,8 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ / { - compatible = "microchip,mpfs-icicle-reference-rtlv2203", "microchip,mpfs"; + compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit", + "microchip,mpfs"; core_pwm0: pwm@41000000 { compatible = "microchip,corepwm-rtl-v4"; @@ -37,3 +38,7 @@ fabric_clk1: fabric-clk1 { clock-frequency = <125000000>; }; }; + +&pcie { + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts index f3f87ed2007f..5e2b8aa2ff64 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts @@ -11,7 +11,8 @@ / { model = "Microchip PolarFire-SoC Icicle Kit"; - compatible = "microchip,mpfs-icicle-kit", "microchip,mpfs"; + compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit", + "microchip,mpfs"; aliases { ethernet0 = &mac1; From patchwork Tue Aug 30 10:18:00 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 601229 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E87C5ECAAD4 for ; Tue, 30 Aug 2022 10:20:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229962AbiH3KUC (ORCPT ); Tue, 30 Aug 2022 06:20:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229839AbiH3KTg (ORCPT ); Tue, 30 Aug 2022 06:19:36 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 25E251A069; Tue, 30 Aug 2022 03:18:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661854728; x=1693390728; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5en4qBuVzdeyn5IGKXiQxzbRqw1ndSal365HolbPArY=; b=uVoCIlReDe5zINvhbnhDYFNBFAFeDNg5MQbd+ZKyqCWxMA6WG2vLMfrg j4sU/MAKwCx11cIWfX85GkhWVg9i+RoQlHB/aO8H6pwJEb/+v/v4X1T9V QAd99IHnii5gWx84klJwYWLBBckYqfgdHQmLSmSyzXlaa3EfNPRNZhbRC W2SPTScbF+nKBJyJLEmntSrPM1SL4GdFYsaUPE1CIFVmnucpGb9gjsZEp 0Qyp/IvzoMsce6jVJe/v6SbL5KMtjcOBcnfZQfqoP2Fkak4cQy8bemlcA OaqeCI9lNVnYNNdyVtPM6rFXUDxZ3EduCnUgzw9qsHcAHHld5onMjKZVC Q==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="174786808" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:18:45 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:18:43 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:18:41 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v2 5/9] riscv: dts: microchip: move the mpfs' pci node to -fabric.dtsi Date: Tue, 30 Aug 2022 11:18:00 +0100 Message-ID: <20220830101803.1456180-6-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830101803.1456180-1-conor.dooley@microchip.com> References: <20220830101803.1456180-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org In today's edition of moving things around: The PCIe root port on PolarFire SoC is more part of the FPGA than of the Core Complex. It is located on the other side of the chip and, apart from its interrupts, most of its configuration is determined by the FPGA bitstream rather. This includes: - address translation in both directions - the addresses at which the config and data regions appear to the core complex - the clocks used by the AXI bus - the plic interrupt used Moving the PCIe node to the -fabric.dtsi makes it clearer than a singular configuration for root port is not correct & allows the base SoC dtsi to be more easily included. Signed-off-by: Conor Dooley --- .../dts/microchip/mpfs-icicle-kit-fabric.dtsi | 32 +++++++++++++++++-- .../dts/microchip/mpfs-polarberry-fabric.dtsi | 29 +++++++++++++++++ arch/riscv/boot/dts/microchip/mpfs.dtsi | 29 ----------------- 3 files changed, 58 insertions(+), 32 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index c0fb9dd7b2c8..a21440c8ee03 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -37,8 +37,34 @@ fabric_clk1: fabric-clk1 { #clock-cells = <0>; clock-frequency = <125000000>; }; -}; -&pcie { - dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names = "fic0", "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi index 49380c428ec9..67303bc0e451 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-polarberry-fabric.dtsi @@ -13,4 +13,33 @@ fabric_clk1: fabric-clk1 { #clock-cells = <0>; clock-frequency = <125000000>; }; + + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names = "fic0", "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; }; diff --git a/arch/riscv/boot/dts/microchip/mpfs.dtsi b/arch/riscv/boot/dts/microchip/mpfs.dtsi index a1176260086a..5974066298e1 100644 --- a/arch/riscv/boot/dts/microchip/mpfs.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs.dtsi @@ -464,35 +464,6 @@ usb: usb@20201000 { status = "disabled"; }; - pcie: pcie@2000000000 { - compatible = "microchip,pcie-host-1.0"; - #address-cells = <0x3>; - #interrupt-cells = <0x1>; - #size-cells = <0x2>; - device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; - reg-names = "cfg", "apb"; - bus-range = <0x0 0x7f>; - interrupt-parent = <&plic>; - interrupts = <119>; - interrupt-map = <0 0 0 1 &pcie_intc 0>, - <0 0 0 2 &pcie_intc 1>, - <0 0 0 3 &pcie_intc 2>, - <0 0 0 4 &pcie_intc 3>; - interrupt-map-mask = <0 0 0 7>; - clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names = "fic0", "fic1", "fic3"; - ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; - msi-parent = <&pcie>; - msi-controller; - status = "disabled"; - pcie_intc: interrupt-controller { - #address-cells = <0>; - #interrupt-cells = <1>; - interrupt-controller; - }; - }; - mbox: mailbox@37020000 { compatible = "microchip,mpfs-mailbox"; reg = <0x0 0x37020000 0x0 0x1000>, <0x0 0x2000318C 0x0 0x40>; From patchwork Tue Aug 30 10:18:01 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 601228 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6A3A6ECAAD4 for ; Tue, 30 Aug 2022 10:20:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230004AbiH3KUE (ORCPT ); Tue, 30 Aug 2022 06:20:04 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53200 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229846AbiH3KTh (ORCPT ); Tue, 30 Aug 2022 06:19:37 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 023BC1A39D; Tue, 30 Aug 2022 03:18:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661854732; x=1693390732; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fKL2pKdfe49aKzGqeWYbXuxKM2r4HTWOwpLHntUQotA=; b=jE4dAYYqIjTHoTKnCCGNCT8O6PScfztT5KjvaP3jx5H+IAP1DkB/bk5t yVItjdvWw6ibsd8Q/cdEK4YAG9iFYWhPCho2Q8+wtISe26HlWahuxSd+r AE64bl9gp/9yv57M/+yjiCrpkdM6xKLikt3IEyQ6QOBqjnhtxquRjz7DV 8A8lgxpP62UH4QHVN4ZiD8pfOT6sNhreaCKX62Ow/aq+6+iUTeZv8csWr mRZiYGyCCmrmEYUVxCY1noxOUD5texgauUsxXFBmlJVDiRVRXA5qSllFI Am1Eps5SNtVaTyy+cqfaoXswwPKY3LbAemTEutFVT++iUPd6s/iNMPwZq A==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="174786835" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:18:48 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:18:47 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:18:44 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v2 6/9] riscv: dts: microchip: icicle: update pci address properties Date: Tue, 30 Aug 2022 11:18:01 +0100 Message-ID: <20220830101803.1456180-7-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830101803.1456180-1-conor.dooley@microchip.com> References: <20220830101803.1456180-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org For the v2022.09 reference design the PCI root port's data region has been moved to FIC1 from FIC0. This is a shorter path, allowing for higher clock rates and improved through-put. As a result, the address at which the PCIe's data region appears to the core complex has changed. The config region's address is unchanged. As FIC0 is no longer used, its clock can be removed too. Signed-off-by: Conor Dooley --- .../boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index a21440c8ee03..32d51c4a5b0c 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -2,6 +2,7 @@ /* Copyright (c) 2020-2021 Microchip Technology Inc */ / { + compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit", "microchip,mpfs"; @@ -38,13 +39,13 @@ fabric_clk1: fabric-clk1 { clock-frequency = <125000000>; }; - pcie: pcie@2000000000 { + pcie: pcie@3000000000 { compatible = "microchip,pcie-host-1.0"; #address-cells = <0x3>; #interrupt-cells = <0x1>; #size-cells = <0x2>; device_type = "pci"; - reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg = <0x30 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; reg-names = "cfg", "apb"; bus-range = <0x0 0x7f>; interrupt-parent = <&plic>; @@ -54,9 +55,9 @@ pcie: pcie@2000000000 { <0 0 0 3 &pcie_intc 2>, <0 0 0 4 &pcie_intc 3>; interrupt-map-mask = <0 0 0 7>; - clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; - clock-names = "fic0", "fic1", "fic3"; - ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + clocks = <&fabric_clk1>, <&fabric_clk3>; + clock-names = "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x30 0x8000000 0x0 0x80000000>; dma-ranges = <0x02000000 0x0 0x00000000 0x0 0x00000000 0x1 0x00000000>; msi-parent = <&pcie>; msi-controller; From patchwork Tue Aug 30 10:18:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 601670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F39A6C0502A for ; Tue, 30 Aug 2022 10:20:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229446AbiH3KUH (ORCPT ); Tue, 30 Aug 2022 06:20:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229770AbiH3KTg (ORCPT ); Tue, 30 Aug 2022 06:19:36 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB9651A38B; Tue, 30 Aug 2022 03:18:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661854732; x=1693390732; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=rZMihXhOLlKxYs0tCwQAUj7e9S0faqqljRoP4WeBM6o=; b=nLpwaPrcJ0mDGLYENMDwMYUekhaBkUmsugZZY5cQ29cz3IH0J1zg36Iu ZbUklh7EFHgnxSKlJCQNnf6DbG8t98uc3Mi+FupctGMjB3B7ZNJl6VBpC KH1MZkN/uGAV+BMRRvu6C66kY4Y7jReR6nh/RcYIkCVob2i6gSE5/rViP ITMwZ8ZJ7pHbm0fmYJSFI8NK4+1HTnzBZ7DOKhEUCvkgDFNKf+RC+pbAk Q6P2qL3GqwSEl14M3CMh1CGYXTTeRzoxDaqctG8r+g0aRIiFb8b1CrzUE qbE8UCIr8uu2Bd/6TxsMDYviUnVmwlFWLPlK3edh0CJYmQDQIDn3RwOxY w==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="178277338" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:18:51 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:18:50 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:18:47 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v2 7/9] riscv: dts: microchip: icicle: re-jig fabric peripheral addresses Date: Tue, 30 Aug 2022 11:18:02 +0100 Message-ID: <20220830101803.1456180-8-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830101803.1456180-1-conor.dooley@microchip.com> References: <20220830101803.1456180-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org When users try to add onto the reference design, they find that the current addresses that peripherals connected to Fabric InterConnect (FIC) 3 use are restrictive. For the v2022.09 reference design, the peripherals have been shifted down, leaving more contiguous address space for their custom IP/peripherals. Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi index 32d51c4a5b0c..98f04be0dc6b 100644 --- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi +++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit-fabric.dtsi @@ -6,18 +6,18 @@ / { compatible = "microchip,mpfs-icicle-reference-rtlv2209", "microchip,mpfs-icicle-kit", "microchip,mpfs"; - core_pwm0: pwm@41000000 { + core_pwm0: pwm@40000000 { compatible = "microchip,corepwm-rtl-v4"; - reg = <0x0 0x41000000 0x0 0xF0>; + reg = <0x0 0x40000000 0x0 0xF0>; microchip,sync-update-mask = /bits/ 32 <0>; #pwm-cells = <2>; clocks = <&fabric_clk3>; status = "disabled"; }; - i2c2: i2c@44000000 { + i2c2: i2c@40000200 { compatible = "microchip,corei2c-rtl-v7"; - reg = <0x0 0x44000000 0x0 0x1000>; + reg = <0x0 0x40000200 0x0 0x1000>; #address-cells = <1>; #size-cells = <0>; clocks = <&fabric_clk3>; From patchwork Tue Aug 30 10:18:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 601227 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 51371ECAAA1 for ; Tue, 30 Aug 2022 10:20:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230076AbiH3KUH (ORCPT ); Tue, 30 Aug 2022 06:20:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229449AbiH3KTi (ORCPT ); Tue, 30 Aug 2022 06:19:38 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C38BB1A3AC; Tue, 30 Aug 2022 03:18:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661854734; x=1693390734; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wYLnJ/r2/6cv7cgLTA2f55BdTU7OBp01DEfsGbye9PI=; b=FnWvoEGCDENLcqwqXxOhUBkkzvtVd8vfrQIIOGLwHECeqJCGNLNDTtu8 M9P1CVPj2I6Rc2Vrs56jqmdSn3SyHY5+DpKtNY54NwwKVVx9fek2V5IaK 6F+6hKprwnE5qQzIwF+MYfziA0HxaFxpUBArOJHBzUkbjowGMj6W5pXES dlGv4preB6NzBwyKNQa5p/WT7yzBZwY8Hpz+yPHyRMevT6FF1H7smMPCs tLSNocX16a8t9YjQTuBqLcXXBTM7UinDgn4jL/JbqJ5M5OxS6HStUjk3b 64BmwxsKQwtbsuG7UlwAQ/h7Y4xlNMvnDWMdauNKnxKpoVt9IdHV7BNtu g==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="111364510" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:18:53 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:18:53 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:18:50 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v2 8/9] riscv: dts: microchip: add sevkit device tree Date: Tue, 30 Aug 2022 11:18:03 +0100 Message-ID: <20220830101803.1456180-9-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830101803.1456180-1-conor.dooley@microchip.com> References: <20220830101803.1456180-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Vattipalli Praveen Add a basic dts for the Microchip Smart Embedded Vision dev kit. The SEV kit is an upcoming first party board, featuring an MPFS250T and: - Dual Sony Camera Sensors (IMX334) - IEEE 802.11 b/g/n 20MHz (1x1) Wi-Fi - Bluetooth 5 Low Energy - 4 GB DDR4 x64 - 2 GB LPDDR4 x32 - 1 GB SPI Flash - 8 GB eMMC flash & SD card slot (multiplexed) - HDMI2.0 Video Input/Output - MIPI DSI Output - MIPI CSI-2 Input Link: https://onlinedocs.microchip.com/pr/GUID-404D3738-DC76-46BA-8683-6A77E837C2DD-en-US-1/index.html?GUID-065AEBEE-7B2C-4895-8579-B1D73D797F06 Signed-off-by: Vattipalli Praveen Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-sev-kit-fabric.dtsi | 45 ++++++ .../riscv/boot/dts/microchip/mpfs-sev-kit.dts | 145 ++++++++++++++++++ 3 files changed, 191 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 39aae7b04f1c..f18477b2e86d 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,4 +1,5 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi new file mode 100644 index 000000000000..8545baf4d129 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit-fabric.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names = "fic0", "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts new file mode 100644 index 000000000000..e810ad453452 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-sev-kit.dts @@ -0,0 +1,145 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-sev-kit-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + #address-cells = <2>; + #size-cells = <2>; + model = "Microchip PolarFire-SoC SEV Kit"; + compatible = "microchip,mpfs-sev-kit", "microchip,mpfs"; + + aliases { + ethernet0 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fabricbuf0ddrc: buffer@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x2000000>; + }; + + fabricbuf1ddrnc: buffer@c4000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xc4000000 0x0 0x4000000>; + }; + + fabricbuf2ddrncwcb: buffer@d4000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0xd4000000 0x0 0x4000000>; + }; + }; + + ddrc_cache: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x0 0x0 0x76000000>; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&gpio2 { + interrupts = <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>, + <53>, <53>, <53>, <53>; + status = "okay"; +}; + +&mac0 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy0>; + phy1: ethernet-phy@9 { + reg = <9>; + }; + phy0: ethernet-phy@8 { + reg = <8>; + }; +}; + +&mac1 { + status = "okay"; + phy-mode = "sgmii"; + phy-handle = <&phy1>; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + status = "okay"; + bus-width = <4>; + disable-wp; + cap-sd-highspeed; + cap-mmc-highspeed; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart2 { + status = "okay"; +}; + +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&rtc { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "otg"; +}; From patchwork Tue Aug 30 10:18:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Conor Dooley X-Patchwork-Id: 601669 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D383C0502E for ; Tue, 30 Aug 2022 10:20:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229832AbiH3KUJ (ORCPT ); Tue, 30 Aug 2022 06:20:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54966 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229879AbiH3KTj (ORCPT ); Tue, 30 Aug 2022 06:19:39 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9CE0316581; Tue, 30 Aug 2022 03:19:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1661854741; x=1693390741; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=yKgAt3C7Fyh1kNQmbM/QmIH0uqeZcK+a+yeHIz/VQwU=; b=RI8WCuuAzJ3x0yG34qz+v0jmA9FWATWKd6zahEEC8RN0hyC6LHgfx/hO UXh4Bl29garA9TJ68tk2NbbeOHZsb72LwKQruVwCk65YedUT0tfcI7yM2 I5vJx5yI+WsNeWgeuQtBIAopa7hAOUtRsl+/NvBr8ZJ1zFDYsGsUM3lSQ iy2wekHOMWmqASFUclkuHkvRJuif4SMEQ2W24K3JMElx7BZp8MUlklIPY WJhb6X8wMKxAGr4LHlx6nawZL4QoKN1nDoVdri3fLQ31NhplJWtg150lS ZZjcfKPn1Xur48jLyJPcSX+Ac8veT/R6697o/L8hSXSlMXmREwfSmxa6a Q==; X-IronPort-AV: E=Sophos;i="5.93,274,1654585200"; d="scan'208";a="171566701" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Aug 2022 03:19:00 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 30 Aug 2022 03:18:57 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 30 Aug 2022 03:18:54 -0700 From: Conor Dooley To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Daire McNamara , Shravan Chippa CC: Paul Walmsley , Palmer Dabbelt , Albert Ou , Cyril Jean , Lewis Hanly , Vattipalli Praveen , Wolfgang Grandegger , Hugh Breslin , , , Subject: [PATCH v2 9/9] riscv: dts: microchip: add a devicetree for aries' m100pfsevp Date: Tue, 30 Aug 2022 11:18:04 +0100 Message-ID: <20220830101803.1456180-10-conor.dooley@microchip.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220830101803.1456180-1-conor.dooley@microchip.com> References: <20220830101803.1456180-1-conor.dooley@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add device trees for both configs used by the Aries Embedded M100PFSEVP. The M100OFSEVP consists of a MPFS250T on a SOM, featuring: - 2GB DDR4 SDRAM dedicated to the HMS - 512MB DDR4 SDRAM dedicated to the FPGA - 32 MB SPI NOR Flash - 4 GByte eMMC and a carrier board with: - 2x Gigabit Ethernet - USB - 2x UART - 2x CAN - TFT connector - HSMC extension connector - 3x PMOD extension connectors - microSD-card slot Link: https://www.aries-embedded.com/polarfire-soc-fpga-microsemi-m100pfs-som-mpfs025t-pcie-serdes Link: https://www.aries-embedded.com/evaluation-kit/fpga/polarfire-microchip-soc-fpga-m100pfsevp-riscv-hsmc-pmod Link: https://downloads.aries-embedded.de/products/M100PFS/Hardware/M100PFSEVP-Schematics.pdf Co-developed-by: Wolfgang Grandegger Signed-off-by: Wolfgang Grandegger Signed-off-by: Conor Dooley --- arch/riscv/boot/dts/microchip/Makefile | 2 + .../dts/microchip/mpfs-m100pfs-fabric.dtsi | 45 +++++ .../dts/microchip/mpfs-m100pfsevp-emmc.dts | 37 +++++ .../dts/microchip/mpfs-m100pfsevp-sdcard.dts | 37 +++++ .../boot/dts/microchip/mpfs-m100pfsevp.dtsi | 155 ++++++++++++++++++ 5 files changed, 276 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts create mode 100644 arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index f18477b2e86d..ea14afab0010 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp-emmc.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp-sdcard.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi new file mode 100644 index 000000000000..7b9ee13b6a3a --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfs-fabric.dtsi @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names = "fic0", "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts new file mode 100644 index 000000000000..3a656c982781 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-emmc.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ + +/dts-v1/; + +#include "mpfs-m100pfsevp.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + model = "Aries Embedded M100PFEVPS eMMC"; + compatible = "aries,m100pfsevp-emmc", "microchip,mpfs"; +}; + +&gpio0 { + emmc-sel-hog { + gpio-hog; + gpios = <12 0>; + output-low; + }; +}; + +&mmc { + max-frequency = <50000000>; + bus-width = <8>; + cap-mmc-highspeed; + no-1-8-v; + non-removable; + disable-wp; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts new file mode 100644 index 000000000000..90fdeac22d24 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp-sdcard.dts @@ -0,0 +1,37 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ + +/dts-v1/; + +#include "mpfs-m100pfsevp.dtsi" + +/ { + model = "Aries Embedded M100PFEVPS sd-card"; + compatible = "aries,m100pfsevp-sdcard", "microchip,mpfs"; +}; + +&gpio0 { + sdcard-sel-hog { + gpio-hog; + gpios = <12 0>; + output-high; + }; +}; + +&mmc { + max-frequency = <50000000>; + bus-width = <4>; + no-1-8-v; + cap-sd-highspeed; + sd-uhs-sdr12; + sd-uhs-sdr25; + sd-uhs-sdr50; + sd-uhs-sdr104; + disable-wp; + status = "okay"; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi new file mode 100644 index 000000000000..e6b6b4647e42 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-m100pfsevp.dtsi @@ -0,0 +1,155 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2021-2022 - Wolfgang Grandegger + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley + */ +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-m100pfs-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define RTCCLK_FREQ 1000000 + +/ { + aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + gpio0 = &gpio0; + gpio1 = &gpio2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + cpus { + timebase-frequency = ; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x40000000>; + }; + ddrc_cache_hi: memory@1040000000 { + device_type = "memory"; + reg = <0x10 0x40000000 0x0 0x40000000>; + }; +}; + +&can0 { + status = "okay"; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; +}; + +&gpio0 { + interrupts = <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>; + ngpios = <14>; + status = "okay"; + + pmic-irq-hog { + gpio-hog; + gpios = <13 0>; + input; + }; +}; + +&gpio2 { + interrupts = <13>, <14>, <15>, <16>, + <17>, <18>, <19>, <20>, + <21>, <22>, <23>, <24>, + <25>, <26>, <27>, <28>, + <29>, <30>, <31>, <32>, + <33>, <34>, <35>, <36>, + <37>, <38>, <39>, <40>, + <41>, <42>, <43>, <44>; + status = "okay"; +}; + +&mac0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mac1 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart2 { + status = "okay"; +}; + +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&pcie { + status = "okay"; +}; + +&qspi { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +};