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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.38.51 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:38:51 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:36 -0800 Message-Id: <20190209033847.9014-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::42b Subject: [Qemu-devel] [PATCH v3 01/12] target/arm: Rely on optimization within tcg_gen_gvec_or X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Since we're now handling a == b generically, we no longer need to do it by hand within target/arm/. Reviewed-by: David Gibson Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 6 +----- target/arm/translate-sve.c | 6 +----- target/arm/translate.c | 12 +++--------- 3 files changed, 5 insertions(+), 19 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index e002251ac6..a12bfac719 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10648,11 +10648,7 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn) gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0); return; case 2: /* ORR */ - if (rn == rm) { /* MOV */ - gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0); - } else { - gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); - } + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0); return; case 3: /* ORN */ gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0); diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index b15b615ceb..3a2eb51566 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -280,11 +280,7 @@ static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a) static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a) { - if (a->rn == a->rm) { /* MOV */ - return do_mov_z(s, a->rd, a->rn); - } else { - return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); - } + return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm); } static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a) diff --git a/target/arm/translate.c b/target/arm/translate.c index 66cf28c8cb..9d2dba7ed2 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6294,15 +6294,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); break; - case 2: - if (rn == rm) { - /* VMOV */ - tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size); - } else { - /* VORR */ - tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, - vec_size, vec_size); - } + case 2: /* VORR */ + tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); break; case 3: /* VORN */ tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs, From patchwork Sat Feb 9 03:38:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157905 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp239065jaa; Fri, 8 Feb 2019 19:42:38 -0800 (PST) X-Google-Smtp-Source: AHgI3IYX7NZX0r29WsJet4/YoFSEq3qGmZ0/R+LY8W3owbW0JN/Trqj/djywsULZM+rLlW5OeolV X-Received: by 2002:a5d:65ce:: with SMTP id e14mr18193373wrw.150.1549683758273; Fri, 08 Feb 2019 19:42:38 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549683758; cv=none; d=google.com; s=arc-20160816; b=q2gvTBu0AofGcFC6gJZA1yQx35zq5Xm7LjscW4JGFbrSZHwd2fX5lu7ikXoWoyb+FE fU7QGvlbvBW52YAhmem+pqXygWB34s4yJScfMqQGjrT+/h4CAFpzHZmpi2rQOCsLTKpc A9xrc37lu7ZhhQCcMZm0Ff6VHDpR2gspupLV+zaLLMIeiSXPPEQe33LpYeU03fTi2I3/ 8UFE8TNBbIbsTw2EVuovW89ADooBOPzp1XseKuYyaWK9Em3t9mpHu7TFnvQWzonUEDtQ QTSRmBhtiRPPKn6wyp5f65nT6NkKNpfGVraEy2Jj6XEBRPXWPoBqFDDVviQ8vQnuZUOm j28A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=vfmR0xjiEFR7KqO1KlnHNMMmXo5J+oxa//ouhR3geX4=; b=bs3E1ZXSodQwh0LoElapgzYYObDkk04ti9oXtyyoR7722i41F9DGvtglq+hX2vw8br nXRFoxHt5Z/CeAC3KDp2AYT2NjHjF8mW/BFbLuvn3gDgplRFFIDaCrFLYqJ2qAoQQzcd VkKks499EeIDGXQoruynFKNU8s7DlongOUga94FOMdEmspjZ85ggbi0LrRwpuK1iVq2F 1B4fIDDddPjBkSK4UhnKAeoSnrVrXKuu+mDk2DIJxHgjtQl1G5mmcAkFfvid3zu8z50w Zwt047/a9lQUqaMIK3lSZAcIdEUaNEyF8rJoQTSHMoxflJdPax1OoWer/TYya04zqZEP EMZQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Pimewh7R; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.38.52 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:38:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:37 -0800 Message-Id: <20190209033847.9014-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 Subject: [Qemu-devel] [PATCH v3 02/12] target/arm: Use vector minmax expanders for aarch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 35 ++++++++++++++--------------------- 1 file changed, 14 insertions(+), 21 deletions(-) -- 2.17.2 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a12bfac719..fd5ceb6613 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10948,6 +10948,20 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) } switch (opcode) { + case 0x0c: /* SMAX, UMAX */ + if (u) { + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); + } else { + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smax, size); + } + return; + case 0x0d: /* SMIN, UMIN */ + if (u) { + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umin, size); + } else { + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_smin, size); + } + return; case 0x10: /* ADD, SUB */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_sub, size); @@ -11109,27 +11123,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genenvfn = fns[size][u]; break; } - case 0xc: /* SMAX, UMAX */ - { - static NeonGenTwoOpFn * const fns[3][2] = { - { gen_helper_neon_max_s8, gen_helper_neon_max_u8 }, - { gen_helper_neon_max_s16, gen_helper_neon_max_u16 }, - { tcg_gen_smax_i32, tcg_gen_umax_i32 }, - }; - genfn = fns[size][u]; - break; - } - - case 0xd: /* SMIN, UMIN */ - { - static NeonGenTwoOpFn * const fns[3][2] = { - { gen_helper_neon_min_s8, gen_helper_neon_min_u8 }, - { gen_helper_neon_min_s16, gen_helper_neon_min_u16 }, - { tcg_gen_smin_i32, tcg_gen_umin_i32 }, - }; - genfn = fns[size][u]; - break; - } case 0xe: /* SABD, UABD */ case 0xf: /* SABA, UABA */ { From patchwork Sat Feb 9 03:38:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157906 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp239560jaa; Fri, 8 Feb 2019 19:43:24 -0800 (PST) X-Google-Smtp-Source: AHgI3IYUg1QRceBLb6r2tzAZsPZikv8LJ3IJPOnzcRLzPppovAXnlIerDJQOfxytObAumZNGjQdC X-Received: by 2002:adf:8122:: with SMTP id 31mr19349199wrm.48.1549683804408; Fri, 08 Feb 2019 19:43:24 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549683804; cv=none; d=google.com; s=arc-20160816; b=sbG5Luj/jo0/hqxV9rjoQxj76oB4VgTtQHvb8StjfJW7NdPKFNR117921myF6UWyZb eyPh9D0BVcm1KBwL5ZkCrkP2kJE+YwtMDuqL/cdu67oWBIsHUMu1lherZ6Tm0ZlMCGkT dv2PdfUotAK9niHLoI4TNwEDexRuGD9BMmAsGUKTdq2AT2IkyhzdErh/n0joqd/hHyai /aDIuMxy+ixtF6rzqA743LULg7Bcuakr8yzHLpzGNL1ziqWE3kCJ89vZaCyhSI5ru8mt wggjD8lWj1GCIrbewbPc+JtwlyglIZpFqNmyP4yUluvOfo++0KRIJZByeo3Ya2Pwvkx6 sM+A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=RT1GreJgsvsbPtqY2RbKVaphAKh18dUwun7FW6H0APA=; b=e+iN/xv4uOiysU12KxMSB0ubFjYBBQ8And8ZloBayGOGWic4UiNWSsKg8PeLT01hsz TE2dWYFqg+EHBFoCcnsBqZIjYWeXOX+uXIXMWBUyNUoGMspRa3T1DR06xDpWYFbzqxQn 2uOKBBnHskhgNXLQNr2D2cmVzHJqA0OBHmRdk74fbdVcMRsLAzo/06tXU+N1ny3tNtng 8rf+byLqU7PP5gD53rEPQO6eXHquky9X3GQJ3SL9gxisYWXeR3bPMU0yPv5PBaoFIy/C ZkgX0GTZf+/YHe4B6J3/a1z4ky1T+Msa0pW+JW+cPUpSMo6R7bqdXWv4MYorcpo7HYYt p5GQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=UuGrdyQK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.38.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:38:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:38 -0800 Message-Id: <20190209033847.9014-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 Subject: [Qemu-devel] [PATCH v3 03/12] target/arm: Use vector minmax expanders for aarch32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/translate.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) -- 2.17.2 diff --git a/target/arm/translate.c b/target/arm/translate.c index 9d2dba7ed2..df1cd3fa3e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6368,6 +6368,25 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_gvec_cmp(u ? TCG_COND_GEU : TCG_COND_GE, size, rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size); return 0; + + case NEON_3R_VMAX: + if (u) { + tcg_gen_gvec_umax(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } else { + tcg_gen_gvec_smax(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } + return 0; + case NEON_3R_VMIN: + if (u) { + tcg_gen_gvec_umin(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } else { + tcg_gen_gvec_smin(size, rd_ofs, rn_ofs, rm_ofs, + vec_size, vec_size); + } + return 0; } if (size == 3) { @@ -6533,12 +6552,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VQRSHL: GEN_NEON_INTEGER_OP_ENV(qrshl); break; - case NEON_3R_VMAX: - GEN_NEON_INTEGER_OP(max); - break; - case NEON_3R_VMIN: - GEN_NEON_INTEGER_OP(min); - break; case NEON_3R_VABD: GEN_NEON_INTEGER_OP(abd); break; From patchwork Sat Feb 9 03:38:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157909 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp240825jaa; Fri, 8 Feb 2019 19:45:22 -0800 (PST) X-Google-Smtp-Source: AHgI3IZLBvYIBszxmIR+tEOEMkJcKAGvxBqzie7pQ2fYBbQn8VlA20ovy8XIcN44vkMnD8ORnsvo X-Received: by 2002:a5d:53cd:: with SMTP id a13mr4926399wrw.146.1549683922805; Fri, 08 Feb 2019 19:45:22 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549683922; cv=none; d=google.com; s=arc-20160816; b=x43FLn5xurvzQw1d1TQkEKdqJ3HPnIK73vD8rzHVtSYDeo1+jW+rsrCrVwJKoGNWBw KhBzt1Y8x1MfULqqL6s4yfZmNKa2atAt7bXO8AX25YNRvmeomDRimEVAwYMyBVjR+3Om xEMqQVXg8/jHFIfmp+Xl+TvXmJxEaG0KyK1/nknCIi/cdfijOYuFqbsDZIouoIRRkzIN x00sWGdsqF48E1V08o6QzXEgBtH7p+HIRfa9QjksElBBiWKXcFCoaWtZA0xnuODGMr2q su70a2EmlOGQePXzVQYo0yRHK6tUh5v9porv2Kx2GPYcwTQqYeBtyaXxLxYV930pcbhh 4y9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Ku2qqiofyo2h0KHaCF51MqBaY9+LaL6xQcdtOeJ2hfM=; b=DfMTHHeWahj18duBJSQT4AsC+Ud9KMi9NDFi3EEcrcs6JuEzho+fhhrBAI0eZnHop3 +EI6y3q3x4TVbmEEbXVv2LMpatVWqj1iGfnxMQqXn1OW50K3/IRguA1AWT7nkrmj4fK8 BEqkB9pIMwuL7fbFOJSfhqHHq6aFFwE7eakDWHWjr1YDsY2cBGMFDMBHM1bRNCUVhjeN w6qfdpmaboXsCVE0F2R2v/JeKhb3/kCEz0d1sMlaHKs5jTYmTMXP+J6sIOYUQCbotQK0 Tql7HN+zirNKCjv8IDNodBR8W4y+KYhXpxgndqjXwobm9ZmTr15epQeL3/SZp+t2Sc5X jtEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=CsxEwDwq; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.38.56 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:38:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:39 -0800 Message-Id: <20190209033847.9014-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 Subject: [Qemu-devel] [PATCH v3 04/12] target/arm: Use tcg integer min/max primitives for neon X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The 32-bit PMIN/PMAX has been decomposed to scalars, and so can be trivially expanded inline. Signed-off-by: Richard Henderson --- target/arm/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) -- 2.17.2 diff --git a/target/arm/translate.c b/target/arm/translate.c index df1cd3fa3e..f0101d2788 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4760,10 +4760,10 @@ static inline void gen_neon_rsb(int size, TCGv_i32 t0, TCGv_i32 t1) } /* 32-bit pairwise ops end up the same as the elementwise versions. */ -#define gen_helper_neon_pmax_s32 gen_helper_neon_max_s32 -#define gen_helper_neon_pmax_u32 gen_helper_neon_max_u32 -#define gen_helper_neon_pmin_s32 gen_helper_neon_min_s32 -#define gen_helper_neon_pmin_u32 gen_helper_neon_min_u32 +#define gen_helper_neon_pmax_s32 tcg_gen_smax_i32 +#define gen_helper_neon_pmax_u32 tcg_gen_umax_i32 +#define gen_helper_neon_pmin_s32 tcg_gen_smin_i32 +#define gen_helper_neon_pmin_u32 tcg_gen_umin_i32 #define GEN_NEON_INTEGER_OP_ENV(name) do { \ switch ((size << 1) | u) { \ From patchwork Sat Feb 9 03:38:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157903 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp238773jaa; Fri, 8 Feb 2019 19:42:11 -0800 (PST) X-Google-Smtp-Source: AHgI3IZt7pEmxKy4UDIg+c9c/z+4b1QTOXaUwgklTHsRZDNY1/ItRR3zjLEg6x/261koIpzdBrMz X-Received: by 2002:a5d:5004:: with SMTP id e4mr20443713wrt.59.1549683731719; Fri, 08 Feb 2019 19:42:11 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549683731; cv=none; d=google.com; s=arc-20160816; b=Nd6PYWWWIRgPnD/4N46eRzGziT6eUxLZOq/D8zAirnchgtXOSeckWgKvQl3WD5I9se Bofvt0A9hPbwrEe9J4UkGOMpbExUo2epl1sgussGPonspYztxFbT2EJqjT2JFllib/j5 qeaKkAwxb+J35d3vCXxl/FOLhJ2D8w/931xL+n4xYx+nynegpqoo119m0rSM3t0j1S9P po3v/L2vlAHERwdeTWwXG2DQsE5YFIpL0p0GOC9LyXalj9Ifl6ovFKnv3UJrOdl7Skku s9T35EUnLYk7ISsjR8Vo8eQydJCeKGmrUvMpIzp5nPavmt/VsxfoOrPf/fXKKxeZapkt GVwA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=Zi+eGtIG5ntlRP+2o43haALA7jfJjuuH+C4Q78Yx964=; b=gvqqqd5OL8V3d1UU5ouKUczobvD304QCMj8VwU+DLF8yYDZVCrnNKxRLrw5gOyMm2q VXoGLUt/G6V2uICC3L6xe+GhuZ4MOadGsDkxo1XJwhmJjAWM9QGzkOimU4iGlPKHa95T Wvw9gMFipqpEsLMtsoYojZ26gWTxuYrfy103BtWeGPuzM+jqu1dJyrGpYY7nlKpqYesm fy7x7jOcZrKqgi2cGXmCdyBNt/AxgW1xsyAOdMqnibbCW06g4yvbj2zMCkFajsPrWfhL LySZ7xMcJQx9d/BtnUGiqablLXe0sPTTUdvHXtEFWG6O4lHIQUHLvpI9aR1QsrZV5Il4 QWBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=s6JOGpsM; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.38.58 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:38:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:40 -0800 Message-Id: <20190209033847.9014-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 05/12] target/arm: Remove neon min/max helpers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" These are now unused. Signed-off-by: Richard Henderson --- target/arm/helper.h | 12 ------------ target/arm/neon_helper.c | 12 ------------ 2 files changed, 24 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.h b/target/arm/helper.h index 53a38188c6..9874c35ea9 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -276,18 +276,6 @@ DEF_HELPER_2(neon_cge_s16, i32, i32, i32) DEF_HELPER_2(neon_cge_u32, i32, i32, i32) DEF_HELPER_2(neon_cge_s32, i32, i32, i32) -DEF_HELPER_2(neon_min_u8, i32, i32, i32) -DEF_HELPER_2(neon_min_s8, i32, i32, i32) -DEF_HELPER_2(neon_min_u16, i32, i32, i32) -DEF_HELPER_2(neon_min_s16, i32, i32, i32) -DEF_HELPER_2(neon_min_u32, i32, i32, i32) -DEF_HELPER_2(neon_min_s32, i32, i32, i32) -DEF_HELPER_2(neon_max_u8, i32, i32, i32) -DEF_HELPER_2(neon_max_s8, i32, i32, i32) -DEF_HELPER_2(neon_max_u16, i32, i32, i32) -DEF_HELPER_2(neon_max_s16, i32, i32, i32) -DEF_HELPER_2(neon_max_u32, i32, i32, i32) -DEF_HELPER_2(neon_max_s32, i32, i32, i32) DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index c2c6491a83..3249005b62 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -581,12 +581,6 @@ NEON_VOP(cge_u32, neon_u32, 1) #undef NEON_FN #define NEON_FN(dest, src1, src2) dest = (src1 < src2) ? src1 : src2 -NEON_VOP(min_s8, neon_s8, 4) -NEON_VOP(min_u8, neon_u8, 4) -NEON_VOP(min_s16, neon_s16, 2) -NEON_VOP(min_u16, neon_u16, 2) -NEON_VOP(min_s32, neon_s32, 1) -NEON_VOP(min_u32, neon_u32, 1) NEON_POP(pmin_s8, neon_s8, 4) NEON_POP(pmin_u8, neon_u8, 4) NEON_POP(pmin_s16, neon_s16, 2) @@ -594,12 +588,6 @@ NEON_POP(pmin_u16, neon_u16, 2) #undef NEON_FN #define NEON_FN(dest, src1, src2) dest = (src1 > src2) ? src1 : src2 -NEON_VOP(max_s8, neon_s8, 4) -NEON_VOP(max_u8, neon_u8, 4) -NEON_VOP(max_s16, neon_s16, 2) -NEON_VOP(max_u16, neon_u16, 2) -NEON_VOP(max_s32, neon_s32, 1) -NEON_VOP(max_u32, neon_u32, 1) NEON_POP(pmax_s8, neon_s8, 4) NEON_POP(pmax_u8, neon_u8, 4) NEON_POP(pmax_s16, neon_s16, 2) From patchwork Sat Feb 9 03:38:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157907 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp240423jaa; Fri, 8 Feb 2019 19:44:44 -0800 (PST) X-Google-Smtp-Source: AHgI3IbrvBMZYlHXNt23qT7EAJ9w5S+D1K+51PxfjwALfU3grJo3U5BG9cQZwwldeeOy0APivkUK X-Received: by 2002:adf:f4d0:: with SMTP id h16mr5364075wrp.103.1549683884832; Fri, 08 Feb 2019 19:44:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549683884; cv=none; d=google.com; s=arc-20160816; b=K0hUFKMF5wB3ls7TqZOqSGhhmD7CpOHQ4qKh9nrOg0p+Qq69rVTtgDDriU9GLHpmle Z8XG8+sMgu6ZaME5AOSi17ma+2musMfI3vZSN9gPVsRT1GZQwZQEQ+vrRfuAdDWbCoJO v6mkzW3DMfES5ItBFeuk/a26rbUrlsxZyZcveA/WKdK/d2zsWNXjJXOImzWdoXzDgPEk kx44LQ75QkJ44y386Fa6jyKqivotJYM/GQYRekdigVD4YBr/GK8o3VutZ5y1/8LRIBQn QT+selXQAc6T01h+8IYaKQpNDIeCqr3Fl155gUkQT2SZyMOdIuqoAJf9pzFQyTgBKIX7 L1tg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=smm0FHV8915qY07Dv9BtLFPbyAAqc9wK+rxK6VxHR+0=; b=KdgaaF64ZTlr3FFD5JIKwRjc9w6Lee+T1zYoYhK7od/lD1GGXjywyiInI7VEiHmvoo siCTQQrT2hOmrKgiG4rJm0hY3WRiYDNkNVRi1pOpR/IF+soxuTWpT6BVg6fHGv5B7STD VNBxjwstKTeWJgfmqpGtwMD7TMllkC7Z/FgDIJE13gbCqNXJKtle9Q51+NG/C9Nf6kyS bnZy1kDb13B9UT7lgsbEh3wACY1H0eL9Uirl5eHMdfhxUJKGFCugNFKxDADSFftm0TPQ wbT2mOU5SXQ/NfrbYiwwxB7KJfLwZALzrGUIhbBafqmulmAAwBkWWz8DGTiCBT+vGMnU loLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="A/PAtmne"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.38.59 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:39:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:41 -0800 Message-Id: <20190209033847.9014-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 Subject: [Qemu-devel] [PATCH v3 06/12] target/arm: Fix vfp_gdb_get/set_reg vs FPSCR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The components of this register is stored in several different locations. Signed-off-by: Richard Henderson --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 520ceea7a4..6ac81c2ca2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -81,7 +81,7 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) } switch (reg - nregs) { case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4; - case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4; + case 1: stl_p(buf, vfp_get_fpscr(env)); return 4; case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4; } return 0; @@ -107,7 +107,7 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) } switch (reg - nregs) { case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4; - case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4; + case 1: vfp_set_fpscr(env, ldl_p(buf)); return 4; case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4; } return 0; From patchwork Sat Feb 9 03:38:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157913 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp243128jaa; Fri, 8 Feb 2019 19:49:13 -0800 (PST) X-Google-Smtp-Source: AHgI3IatgXM6fENjJ/yAQtk/JBeZmxsDXfMvfsFlUi0NVBqLDIc/7+iqyugZFfPRc5bI47l/FQDd X-Received: by 2002:adf:824b:: with SMTP id 69mr8258667wrb.24.1549684153540; Fri, 08 Feb 2019 19:49:13 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549684153; cv=none; d=google.com; s=arc-20160816; b=hDtl6ulYV4pWyjDGdnhU8AHATagL1fsKW36QCetJtuOIt5vpFQ+A1krY/Lj+jXLyF5 VYz61RuNK9tWEzfQoTgNzo/8KVosNOqLLyTzlM/wWMXqBwYWI6nnkHDRqTq3duweW0vw YVK1p/SHi6ucBv2g1Qt64t4pE9WsIlI474+9FbQZdWv8qsNhihfIxpniNnqCjXdtUGvj wjCwkOQVV7+Q++kigonN48UYL3bEW/jkFUFIKjLANF24DYUOWlFFMGqUKGT4r9dPobUh SQj9qmU4twXtREzxZzUgk5Nhct7bqSX2eqQXYJ8JR2gBBSNTCq832zFjXuFCi8PfhfTl 4bIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=4vo5h8ohfFheLvmyTEpJJcqtpBW3TwPHJrdpa8cctgQ=; b=FNZBXBssIBKFTYvb4mcEA4R1nlSqfdmXaD+BrzDOMcM2BcCM/PDGWOF6ohRaNzv5ZB WAUPsjWd7VwGcOoaGjEpc5b6R1vplQKpbqzpdbrs+KDa1lBstoR2pQDysFDXWfoHArK2 jCEpERTVyRyI2YjE4up3Q8xotcuePWYRkBSoOlKEw1meeAaOoIpk1at2alGTk1jca2mP Y1rmIhg/f4TnUrX1UPrTEHUbQ3ATe5A1HppAsGUUEjitzCMNtrpwyNFMb0aqYUgrhQpp ZCeVGIdc37/QZgX0mBQiNhrWw3jiRhWUJ2UE7ZOykZwEh28y4RyuAIzaR6S/ZHV+yyyL 7jwg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="LnOvi2d/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.39.01 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:39:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:42 -0800 Message-Id: <20190209033847.9014-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 Subject: [Qemu-devel] [PATCH v3 07/12] target/arm: Fix arm_cpu_dump_state vs FPSCR X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- target/arm/translate.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/translate.c b/target/arm/translate.c index f0101d2788..9b426f4271 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -13641,7 +13641,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, i * 2 + 1, (uint32_t)(v >> 32), i, v); } - cpu_fprintf(f, "FPSCR: %08x\n", (int)env->vfp.xregs[ARM_VFP_FPSCR]); + cpu_fprintf(f, "FPSCR: %08x\n", vfp_get_fpscr(env)); } } From patchwork Sat Feb 9 03:38:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157914 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp243930jaa; Fri, 8 Feb 2019 19:50:29 -0800 (PST) X-Google-Smtp-Source: AHgI3Iaf9ldFv7An1rlbzMg4N8h7Qe2LAwd586AgbXIgr0mIym+YNiA1gcy3E+AJjN/XLOZrFzbf X-Received: by 2002:a1c:9e4a:: with SMTP id h71mr1348784wme.82.1549684229567; Fri, 08 Feb 2019 19:50:29 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549684229; cv=none; d=google.com; s=arc-20160816; b=EizDS6vDeo7fjzEPuNbRcmFODfWjQeby9F5TD4eiq0Uew0rBmoLgcjRDcyzyj7MvQC +KaMpVOAgeRjAA2K8BNBDeeVNt+gaK42bEllzyW/z1MjW820GPgTkvbtIN3r9uKTJ1vz w9REjPhzNFYJ2LFCizlQiT2GqPPCp+M/e0PfIbx0hn/wESbhApSKmmnMY+dfHuAESolE pGB/bFEwjWh41P3NrbPq3xSu+QCHJTALbvMWPskg7T/JdpHP4LbDJj7oB0WrnUb3N+4o /SkTSpV4CQxWNX0ARV3OMJat8Ddg1z21DT2dVjFq5PLtiSJEghY52FzILFKbIWT5btA2 a74w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=mbI6BmlEcsoQbk9otTO/UpbfLnedk7lNBUH1NdN1wA0=; b=woot+m0sXOj/bGEXfQHBavKh2AdLKiwArPGUfERuPX13ehHNO3Izndkgw5nyUS8crc dWOzgvxWt60Yld6G7oYBmJ6kqIrscFs04EWGOGi+64KNtQKTYLOBBblB73ymDBy6r2q+ BUgq64VvPUqb4z68Nvb9ctNl8LgbkxLAIjbbaAYLMKEcBGrPxPMnZ+0EFzCkP8hXXXFb 7diUjBJDoNP2gB0NMVfTH+FYQwy/313qqRY8nIpev2lI2AZZYB4OtUY1B5oOzZDPHl7n CUNEdeManTaoDZC99hIeYPn+VJz/A5hw9yOzInalA9kL5n4H3UNg61PwP24PFhbOIM7J Q5WA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=NyCCjsZj; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.39.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:39:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:43 -0800 Message-Id: <20190209033847.9014-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::636 Subject: [Qemu-devel] [PATCH v3 08/12] target/arm: Split out flags setting from vfp compares X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Minimize the code within a macro by splitting out a helper function. Use deposit32 instead of manual bit manipulation. Signed-off-by: Richard Henderson --- target/arm/helper.c | 45 +++++++++++++++++++++++++++------------------ 1 file changed, 27 insertions(+), 18 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 6ac81c2ca2..51be3fa16f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12752,31 +12752,40 @@ float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env) return float64_sqrt(a, &env->vfp.fp_status); } +static void softfloat_to_vfp_compare(CPUARMState *env, int cmp) +{ + uint32_t flags; + switch (cmp) { + case float_relation_equal: + flags = 0x6; + break; + case float_relation_less: + flags = 0x8; + break; + case float_relation_greater: + flags = 0x2; + break; + case float_relation_unordered: + flags = 0x3; + break; + default: + g_assert_not_reached(); + } + env->vfp.xregs[ARM_VFP_FPSCR] = + deposit32(env->vfp.xregs[ARM_VFP_FPSCR], 28, 4, flags); +} + /* XXX: check quiet/signaling case */ #define DO_VFP_cmp(p, type) \ void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \ { \ - uint32_t flags; \ - switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \ - case 0: flags = 0x6; break; \ - case -1: flags = 0x8; break; \ - case 1: flags = 0x2; break; \ - default: case 2: flags = 0x3; break; \ - } \ - env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ - | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ + softfloat_to_vfp_compare(env, \ + type ## _compare_quiet(a, b, &env->vfp.fp_status)); \ } \ void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \ { \ - uint32_t flags; \ - switch(type ## _compare(a, b, &env->vfp.fp_status)) { \ - case 0: flags = 0x6; break; \ - case -1: flags = 0x8; break; \ - case 1: flags = 0x2; break; \ - default: case 2: flags = 0x3; break; \ - } \ - env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \ - | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \ + softfloat_to_vfp_compare(env, \ + type ## _compare(a, b, &env->vfp.fp_status)); \ } DO_VFP_cmp(s, float32) DO_VFP_cmp(d, float64) From patchwork Sat Feb 9 03:38:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157910 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp241087jaa; Fri, 8 Feb 2019 19:45:52 -0800 (PST) X-Google-Smtp-Source: AHgI3Ibxw3drrODAbUOZTCe8L1Z5Te5ieit8y5Jlc6AhizQZIWLhW/NZbinxMDizC4rHWz6fr8Pm X-Received: by 2002:a5d:6b09:: with SMTP id v9mr19951498wrw.304.1549683952141; Fri, 08 Feb 2019 19:45:52 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549683952; cv=none; d=google.com; s=arc-20160816; b=xqWjYYRFeFz9B0doAJYEhZPqTjptHlM2gZohdDay9DQBRTeZqBI19FpHIQdAl1Og5Q cZ0IUJAVLtBmZPMYlhlQkLmpT4XTGMZHNUkDCyhUHdAvpv1PgQTbm1xxSiLyStwtmxwr w2VF3tMSIMX94GTYE26rQMJQTNfcBkgauXeFO17lMhGGxJ+dR0JuYOk7zuFpPFnn7XIE kBUyzrZ1j/lmTTQMF4GYDwNqC9am/LMNPWvJcptxN+HgU6fG3Rq+GfTTIQ4QO/ToTiTM AaKXZbvL8v4C3ihBQCqUAmZjc6XlqWloSwu3wAz/GMgtePylXsoVAI3gOLMPVs1xcONt /EZg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=io0Q8vKcg32ZslzsokBprL4UTtWvNRVBn1H6HUdOh9Q=; b=XMKWDOHRXyBFJoThwnZ+uXg3MvGAlSZnv1Umy2AE8g9vBYGVD6yl0EJKmOrI+YCamh S9IWo84rRwaajWS+X4Gdg6XysBXq3xB+OsjgnO5O13gqaFAUk/xI22PaVztjp1E3pD2m CUMOCVRIXpeJFEUrboi0rA7f2AsLDMmDlLFkhHY+QfncZbKIqzb+cSigOfE5sGs+TG8Q /gHpuVYhqIqDUfTwRYVjdy9twyzxSU3/BYzemFia8rMSBmOffZdje73jXpYRQQy+/Foz u9t2K5ycKRBExkk2nsfE8IOsldAk6uGmmDuBsSdVexmWTbjh25TQ9SKmhfpFFgnGclzx GPUA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Qvlrwxqp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.39.03 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:39:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:44 -0800 Message-Id: <20190209033847.9014-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 09/12] target/arm: Fix set of bits kept in xregs[ARM_VFP_FPSCR] X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Given that we mask bits properly on set, there is no reason to mask them again on get. We failed to clear the exception status bits, 0x9f, which means that the wrong value would be returned on get. Except in the (probably normal) case in which the set clears all of the bits. Simplify the code in set to also clear the RES0 bits. Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 51be3fa16f..af22274bd9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12588,7 +12588,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) int i; uint32_t fpscr; - fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff) + fpscr = env->vfp.xregs[ARM_VFP_FPSCR] | (env->vfp.vec_len << 16) | (env->vfp.vec_stride << 20); @@ -12630,7 +12630,7 @@ static inline int vfp_exceptbits_to_host(int target_bits) void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) { int i; - uint32_t changed; + uint32_t changed = env->vfp.xregs[ARM_VFP_FPSCR]; /* When ARMv8.2-FP16 is not supported, FZ16 is RES0. */ if (!cpu_isar_feature(aa64_fp16, arm_env_get_cpu(env))) { @@ -12639,12 +12639,13 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) /* * We don't implement trapped exception handling, so the - * trap enable bits are all RAZ/WI (not RES0!) + * trap enable bits, IDE|IXE|UFE|OFE|DZE|IOE are all RAZ/WI (not RES0!) + * + * If we exclude the exception flags, IOC|DZC|OFC|UFC|IXC|IDC + * (which are stored in fp_status), and the other RES0 bits + * in between, then we clear all of the low 16 bits. */ - val &= ~(FPCR_IDE | FPCR_IXE | FPCR_UFE | FPCR_OFE | FPCR_DZE | FPCR_IOE); - - changed = env->vfp.xregs[ARM_VFP_FPSCR]; - env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff); + env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xffc80000; env->vfp.vec_len = (val >> 16) & 7; env->vfp.vec_stride = (val >> 20) & 3; From patchwork Sat Feb 9 03:38:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157911 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp241992jaa; Fri, 8 Feb 2019 19:47:15 -0800 (PST) X-Google-Smtp-Source: AHgI3IZbuC5/7pI9jl3kMa3MDiw1eAPMSItcxtTe4VOD7NefcR0tWKTCTFoKfPpCaZ0fC2GGnCqV X-Received: by 2002:a1c:7312:: with SMTP id d18mr543285wmb.24.1549684034993; Fri, 08 Feb 2019 19:47:14 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549684034; cv=none; d=google.com; s=arc-20160816; b=jze3W7czNpYxJZHa5y2obL6AcpsuRigW+N/CvqqQltOw/r8NWacHnkhcH03P2ezXG1 LAvDLsdejWLPYU+Yg4Xg3BJMSWWcq4S37duiDscsGsg+WSHUXoHJlr5cnI8+4MtdNu8U HILvfj6OlsBG994DiVz8Mq58qM7QavclT1MCV2a/ANtNMDTcfCjGM0Ogo0WzX2zn3oM9 Iy8vAY4aWyRkAHIfToNLJz2PHW615L6wW13I/w4LoSpsfmlGz9jnWiS0TMefWjPbx6// 7Gh4DE2gpbnoUKyEHjyhgtlzY5JDOLRupYakQ17C8MF8XTo/+yh6OPCQCaghMQPSAQgl hzAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=aCH1tSuPlPTrUampigSo2Lvj/9ILp6juR6hIm3KXMeA=; b=Kx8ZLiWHtNSMfwX6NKTfAX4s+wmx2PRs0haALG+WuarvZLFzsmOptd8qRI3+tj+ELB +zWefnc+MwXe9QuIiqTiRyoJJ1txKEBkd8rky6CcGhzinSZa5QnUMhPFV9kmgGNchOof N0rNBiDaM62t5eQbtgqjGVSi5FxpR3LPkkygjXYOv39ROK91MqasUOoxDjHqXgMoc5Dy W+hHgzZvbCEby/Iv5VA6Mp3sZ3vhEj3E5C9zsVYlpQDN0l0ZjpSHLVG3qzRWrTzuVRQ3 Jn7Qql7nJdkg1dIeb3EJBEEzdQzp8BXvWY+i58Edmcplttnn5Mc7eFH+HK+n3PbMBEw5 LuDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=dRTA+h+y; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.39.04 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:39:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:45 -0800 Message-Id: <20190209033847.9014-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 Subject: [Qemu-devel] [PATCH v3 10/12] target/arm: Split out FPSCR.QC to a vector field X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Change the representation of this field such that it is easy to set from vector code. Signed-off-by: Richard Henderson --- target/arm/cpu.h | 5 ++++- target/arm/helper.c | 19 +++++++++++++++---- target/arm/neon_helper.c | 2 +- target/arm/vec_helper.c | 2 +- 4 files changed, 21 insertions(+), 7 deletions(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 47238e4245..b96463e8f1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -577,11 +577,13 @@ typedef struct CPUARMState { ARMPredicateReg preg_tmp; #endif - uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ + uint32_t qc[4] QEMU_ALIGNED(16); int vec_len; int vec_stride; + uint32_t xregs[16]; + /* Scratch space for aa32 neon expansion. */ uint32_t scratch[8]; @@ -1427,6 +1429,7 @@ void vfp_set_fpscr(CPUARMState *env, uint32_t val); #define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ #define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ #define FPCR_DN (1 << 25) /* Default NaN enable bit */ +#define FPCR_QC (1 << 27) /* Cumulative saturation bit */ static inline uint32_t vfp_get_fpsr(CPUARMState *env) { diff --git a/target/arm/helper.c b/target/arm/helper.c index af22274bd9..7ed9933663 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12585,8 +12585,7 @@ static inline int vfp_exceptbits_from_host(int host_bits) uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) { - int i; - uint32_t fpscr; + uint32_t i, fpscr; fpscr = env->vfp.xregs[ARM_VFP_FPSCR] | (env->vfp.vec_len << 16) @@ -12597,8 +12596,11 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) /* FZ16 does not generate an input denormal exception. */ i |= (get_float_exception_flags(&env->vfp.fp_status_f16) & ~float_flag_input_denormal); - fpscr |= vfp_exceptbits_from_host(i); + + i = env->vfp.qc[0] | env->vfp.qc[1] | env->vfp.qc[2] | env->vfp.qc[3]; + fpscr |= i ? FPCR_QC : 0; + return fpscr; } @@ -12645,10 +12647,19 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) * (which are stored in fp_status), and the other RES0 bits * in between, then we clear all of the low 16 bits. */ - env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xffc80000; + env->vfp.xregs[ARM_VFP_FPSCR] = val & 0xf7c80000; env->vfp.vec_len = (val >> 16) & 7; env->vfp.vec_stride = (val >> 20) & 3; + /* + * The bit we set within fpscr_q is arbitrary; the register as a + * whole being zero/non-zero is what counts. + */ + env->vfp.qc[0] = val & FPCR_QC; + env->vfp.qc[1] = 0; + env->vfp.qc[2] = 0; + env->vfp.qc[3] = 0; + changed ^= val; if (changed & (3 << 22)) { i = (val >> 22) & 3; diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index 3249005b62..ed1c6fc41c 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -15,7 +15,7 @@ #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) -#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q +#define SET_QC() env->vfp.qc[0] = 1 #define NEON_TYPE1(name, type) \ typedef struct \ diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 37f338732e..65a18af4e0 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -36,7 +36,7 @@ #define H4(x) (x) #endif -#define SET_QC() env->vfp.xregs[ARM_VFP_FPSCR] |= CPSR_Q +#define SET_QC() env->vfp.qc[0] = 1 static void clear_tail(void *vd, uintptr_t opr_sz, uintptr_t max_sz) { From patchwork Sat Feb 9 03:38:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157915 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp244765jaa; Fri, 8 Feb 2019 19:51:47 -0800 (PST) X-Google-Smtp-Source: AHgI3IYjhnERX3ctmCHkVcFa/fP8atnKYcC9rlwF4MKW9kWmE5NoLwS1h9/ks4mEghi1JF908eno X-Received: by 2002:adf:f34e:: with SMTP id e14mr20231662wrp.240.1549684307116; Fri, 08 Feb 2019 19:51:47 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549684307; cv=none; d=google.com; s=arc-20160816; b=AgHCV+1W/GtrZIYrJVlZ1/TA+WHvWwwVODWBisci4gxwa6R8Xph+3ExD6Dntt46tWq LX3Jt0z3t7xCY5YynWOpfx1P6j+XFiMrJl8rs6ErBNU6WD46JmZchqB/lJfmR0dcVI/o xjdhwSQM6RA3/5YJYMHwIUuwI2OqSd067rjfN5N2UUBpRVPYPXFdNA+ZmoCPDsNY60yH VfvatcmRtoOzalWyUEkYcSY7dOi/ytJe/MUC7vk8hl5CQ02Pak5liF6dnejkZ8jdO1aN WVcGP5D5UJtq1I8R8vIPb4CeLvERtfTDBteRCB5+aQCKyosQ8AIw9bNfK6viEeEaL4EH xDwg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ekZakn26RrnuoOdbmnjbqOhwwrv1WMbjn8NMae33G2c=; b=1DYvshR1ZcApMazwKLHUz8ooLFXdlKDSANZ7vXCQaohA10BmqW4NoqTThzFx4hmBgO QWunFr4yYeKPt73cexnvDf5aps4u2DmRhZLHgggjYEr8Iz/J8TNGbOlEH8w7nZcIDpeC NV8bLnlVqQgyZYvjK4WPF3gjcPC6Y+WnfKX7/U3DwONJL66PbyknTNS/KQMgf6il0AOR SWMyUeF9q9w0CgpJVvT6FGf9x6tPBcFb1AwP3Fo8n4salV+y4e49f3ND2psyW770+nAu GERz915TI68eTXzhCBqIsCMlbNxO4aiRIQA9iksKwlsTCD9XzrTPLq7aF3gR0555p2F6 UPvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nsEbfiuG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.39.06 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:39:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:46 -0800 Message-Id: <20190209033847.9014-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 Subject: [Qemu-devel] [PATCH v3 11/12] target/arm: Use vector operations for saturation X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For same-sign saturation, we have tcg vector operations. We can compute the QC bit by comparing the saturated value against the unsaturated value. Signed-off-by: Richard Henderson --- target/arm/helper.h | 33 +++++++ target/arm/translate.h | 4 + target/arm/translate-a64.c | 36 ++++---- target/arm/translate.c | 172 +++++++++++++++++++++++++++++++------ target/arm/vec_helper.c | 130 ++++++++++++++++++++++++++++ 5 files changed, 331 insertions(+), 44 deletions(-) -- 2.17.2 diff --git a/target/arm/helper.h b/target/arm/helper.h index 9874c35ea9..923e8e1525 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -641,6 +641,39 @@ DEF_HELPER_FLAGS_6(gvec_fmla_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fmla_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqadd_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqadd_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_uqsub_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(gvec_sqsub_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + #ifdef TARGET_AARCH64 #include "helper-a64.h" #include "helper-sve.h" diff --git a/target/arm/translate.h b/target/arm/translate.h index 17748ddfb9..f25fe75685 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -214,6 +214,10 @@ extern const GVecGen2i ssra_op[4]; extern const GVecGen2i usra_op[4]; extern const GVecGen2i sri_op[4]; extern const GVecGen2i sli_op[4]; +extern const GVecGen4 uqadd_op[4]; +extern const GVecGen4 sqadd_op[4]; +extern const GVecGen4 uqsub_op[4]; +extern const GVecGen4 sqsub_op[4]; void gen_cmtst_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); /* diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fd5ceb6613..af8e4fd4be 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -10948,6 +10948,22 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) } switch (opcode) { + case 0x01: /* SQADD, UQADD */ + tcg_gen_gvec_4(vec_full_reg_offset(s, rd), + offsetof(CPUARMState, vfp.qc), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s), + (u ? uqadd_op : sqadd_op) + size); + return; + case 0x05: /* SQSUB, UQSUB */ + tcg_gen_gvec_4(vec_full_reg_offset(s, rd), + offsetof(CPUARMState, vfp.qc), + vec_full_reg_offset(s, rn), + vec_full_reg_offset(s, rm), + is_q ? 16 : 8, vec_full_reg_size(s), + (u ? uqsub_op : sqsub_op) + size); + return; case 0x0c: /* SMAX, UMAX */ if (u) { gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_umax, size); @@ -11043,16 +11059,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genfn = fns[size][u]; break; } - case 0x1: /* SQADD, UQADD */ - { - static NeonGenTwoOpEnvFn * const fns[3][2] = { - { gen_helper_neon_qadd_s8, gen_helper_neon_qadd_u8 }, - { gen_helper_neon_qadd_s16, gen_helper_neon_qadd_u16 }, - { gen_helper_neon_qadd_s32, gen_helper_neon_qadd_u32 }, - }; - genenvfn = fns[size][u]; - break; - } case 0x2: /* SRHADD, URHADD */ { static NeonGenTwoOpFn * const fns[3][2] = { @@ -11073,16 +11079,6 @@ static void disas_simd_3same_int(DisasContext *s, uint32_t insn) genfn = fns[size][u]; break; } - case 0x5: /* SQSUB, UQSUB */ - { - static NeonGenTwoOpEnvFn * const fns[3][2] = { - { gen_helper_neon_qsub_s8, gen_helper_neon_qsub_u8 }, - { gen_helper_neon_qsub_s16, gen_helper_neon_qsub_u16 }, - { gen_helper_neon_qsub_s32, gen_helper_neon_qsub_u32 }, - }; - genenvfn = fns[size][u]; - break; - } case 0x8: /* SSHL, USHL */ { static NeonGenTwoOpFn * const fns[3][2] = { diff --git a/target/arm/translate.c b/target/arm/translate.c index 9b426f4271..dac737f6ca 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6148,6 +6148,142 @@ const GVecGen3 cmtst_op[4] = { .vece = MO_64 }, }; +static void gen_uqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec x = tcg_temp_new_vec_matching(t); + tcg_gen_add_vec(vece, x, a, b); + tcg_gen_usadd_vec(vece, t, a, b); + tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t); + tcg_gen_or_vec(vece, sat, sat, x); + tcg_temp_free_vec(x); +} + +const GVecGen4 uqadd_op[4] = { + { .fniv = gen_uqadd_vec, + .fno = gen_helper_gvec_uqadd_b, + .opc = INDEX_op_usadd_vec, + .write_aofs = true, + .vece = MO_8 }, + { .fniv = gen_uqadd_vec, + .fno = gen_helper_gvec_uqadd_h, + .opc = INDEX_op_usadd_vec, + .write_aofs = true, + .vece = MO_16 }, + { .fniv = gen_uqadd_vec, + .fno = gen_helper_gvec_uqadd_s, + .opc = INDEX_op_usadd_vec, + .write_aofs = true, + .vece = MO_32 }, + { .fniv = gen_uqadd_vec, + .fno = gen_helper_gvec_uqadd_d, + .opc = INDEX_op_usadd_vec, + .write_aofs = true, + .vece = MO_64 }, +}; + +static void gen_sqadd_vec(unsigned vece, TCGv_vec t, TCGv_vec sat, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec x = tcg_temp_new_vec_matching(t); + tcg_gen_add_vec(vece, x, a, b); + tcg_gen_ssadd_vec(vece, t, a, b); + tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t); + tcg_gen_or_vec(vece, sat, sat, x); + tcg_temp_free_vec(x); +} + +const GVecGen4 sqadd_op[4] = { + { .fniv = gen_sqadd_vec, + .fno = gen_helper_gvec_sqadd_b, + .opc = INDEX_op_ssadd_vec, + .write_aofs = true, + .vece = MO_8 }, + { .fniv = gen_sqadd_vec, + .fno = gen_helper_gvec_sqadd_h, + .opc = INDEX_op_ssadd_vec, + .write_aofs = true, + .vece = MO_16 }, + { .fniv = gen_sqadd_vec, + .fno = gen_helper_gvec_sqadd_s, + .opc = INDEX_op_ssadd_vec, + .write_aofs = true, + .vece = MO_32 }, + { .fniv = gen_sqadd_vec, + .fno = gen_helper_gvec_sqadd_d, + .opc = INDEX_op_ssadd_vec, + .write_aofs = true, + .vece = MO_64 }, +}; + +static void gen_uqsub_vec(unsigned vece, TCGv_vec t, TCGv_vec sat, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec x = tcg_temp_new_vec_matching(t); + tcg_gen_sub_vec(vece, x, a, b); + tcg_gen_ussub_vec(vece, t, a, b); + tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t); + tcg_gen_or_vec(vece, sat, sat, x); + tcg_temp_free_vec(x); +} + +const GVecGen4 uqsub_op[4] = { + { .fniv = gen_uqsub_vec, + .fno = gen_helper_gvec_uqsub_b, + .opc = INDEX_op_ussub_vec, + .write_aofs = true, + .vece = MO_8 }, + { .fniv = gen_uqsub_vec, + .fno = gen_helper_gvec_uqsub_h, + .opc = INDEX_op_ussub_vec, + .write_aofs = true, + .vece = MO_16 }, + { .fniv = gen_uqsub_vec, + .fno = gen_helper_gvec_uqsub_s, + .opc = INDEX_op_ussub_vec, + .write_aofs = true, + .vece = MO_32 }, + { .fniv = gen_uqsub_vec, + .fno = gen_helper_gvec_uqsub_d, + .opc = INDEX_op_ussub_vec, + .write_aofs = true, + .vece = MO_64 }, +}; + +static void gen_sqsub_vec(unsigned vece, TCGv_vec t, TCGv_vec sat, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec x = tcg_temp_new_vec_matching(t); + tcg_gen_sub_vec(vece, x, a, b); + tcg_gen_sssub_vec(vece, t, a, b); + tcg_gen_cmp_vec(TCG_COND_NE, vece, x, x, t); + tcg_gen_or_vec(vece, sat, sat, x); + tcg_temp_free_vec(x); +} + +const GVecGen4 sqsub_op[4] = { + { .fniv = gen_sqsub_vec, + .fno = gen_helper_gvec_sqsub_b, + .opc = INDEX_op_sssub_vec, + .write_aofs = true, + .vece = MO_8 }, + { .fniv = gen_sqsub_vec, + .fno = gen_helper_gvec_sqsub_h, + .opc = INDEX_op_sssub_vec, + .write_aofs = true, + .vece = MO_16 }, + { .fniv = gen_sqsub_vec, + .fno = gen_helper_gvec_sqsub_s, + .opc = INDEX_op_sssub_vec, + .write_aofs = true, + .vece = MO_32 }, + { .fniv = gen_sqsub_vec, + .fno = gen_helper_gvec_sqsub_d, + .opc = INDEX_op_sssub_vec, + .write_aofs = true, + .vece = MO_64 }, +}; + /* Translate a NEON data processing instruction. Return nonzero if the instruction is invalid. We process data in a mixture of 32-bit and 64-bit chunks. @@ -6331,6 +6467,18 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } return 0; + case NEON_3R_VQADD: + tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), + rn_ofs, rm_ofs, vec_size, vec_size, + (u ? uqadd_op : sqadd_op) + size); + break; + + case NEON_3R_VQSUB: + tcg_gen_gvec_4(rd_ofs, offsetof(CPUARMState, vfp.qc), + rn_ofs, rm_ofs, vec_size, vec_size, + (u ? uqsub_op : sqsub_op) + size); + break; + case NEON_3R_VMUL: /* VMUL */ if (u) { /* Polynomial case allows only P8 and is handled below. */ @@ -6395,24 +6543,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) neon_load_reg64(cpu_V0, rn + pass); neon_load_reg64(cpu_V1, rm + pass); switch (op) { - case NEON_3R_VQADD: - if (u) { - gen_helper_neon_qadd_u64(cpu_V0, cpu_env, - cpu_V0, cpu_V1); - } else { - gen_helper_neon_qadd_s64(cpu_V0, cpu_env, - cpu_V0, cpu_V1); - } - break; - case NEON_3R_VQSUB: - if (u) { - gen_helper_neon_qsub_u64(cpu_V0, cpu_env, - cpu_V0, cpu_V1); - } else { - gen_helper_neon_qsub_s64(cpu_V0, cpu_env, - cpu_V0, cpu_V1); - } - break; case NEON_3R_VSHL: if (u) { gen_helper_neon_shl_u64(cpu_V0, cpu_V1, cpu_V0); @@ -6528,18 +6658,12 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) case NEON_3R_VHADD: GEN_NEON_INTEGER_OP(hadd); break; - case NEON_3R_VQADD: - GEN_NEON_INTEGER_OP_ENV(qadd); - break; case NEON_3R_VRHADD: GEN_NEON_INTEGER_OP(rhadd); break; case NEON_3R_VHSUB: GEN_NEON_INTEGER_OP(hsub); break; - case NEON_3R_VQSUB: - GEN_NEON_INTEGER_OP_ENV(qsub); - break; case NEON_3R_VSHL: GEN_NEON_INTEGER_OP(shl); break; diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 65a18af4e0..10f17e4b5c 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -766,3 +766,133 @@ DO_FMLA_IDX(gvec_fmla_idx_s, float32, H4) DO_FMLA_IDX(gvec_fmla_idx_d, float64, ) #undef DO_FMLA_IDX + +#define DO_SAT(NAME, WTYPE, TYPEN, TYPEM, OP, MIN, MAX) \ +void HELPER(NAME)(void *vd, void *vq, void *vn, void *vm, uint32_t desc) \ +{ \ + intptr_t i, oprsz = simd_oprsz(desc); \ + TYPEN *d = vd, *n = vn; TYPEM *m = vm; \ + bool q = false; \ + for (i = 0; i < oprsz / sizeof(TYPEN); i++) { \ + WTYPE dd = (WTYPE)n[i] OP m[i]; \ + if (dd < MIN) { \ + dd = MIN; \ + q = true; \ + } else if (dd > MAX) { \ + dd = MAX; \ + q = true; \ + } \ + d[i] = dd; \ + } \ + if (q) { \ + uint32_t *qc = vq; \ + qc[0] = 1; \ + } \ + clear_tail(d, oprsz, simd_maxsz(desc)); \ +} + +DO_SAT(gvec_uqadd_b, int, uint8_t, uint8_t, +, 0, UINT8_MAX) +DO_SAT(gvec_uqadd_h, int, uint16_t, uint16_t, +, 0, UINT16_MAX) +DO_SAT(gvec_uqadd_s, int64_t, uint32_t, uint32_t, +, 0, UINT32_MAX) + +DO_SAT(gvec_sqadd_b, int, int8_t, int8_t, +, INT8_MIN, INT8_MAX) +DO_SAT(gvec_sqadd_h, int, int16_t, int16_t, +, INT16_MIN, INT16_MAX) +DO_SAT(gvec_sqadd_s, int64_t, int32_t, int32_t, +, INT32_MIN, INT32_MAX) + +DO_SAT(gvec_uqsub_b, int, uint8_t, uint8_t, -, 0, UINT8_MAX) +DO_SAT(gvec_uqsub_h, int, uint16_t, uint16_t, -, 0, UINT16_MAX) +DO_SAT(gvec_uqsub_s, int64_t, uint32_t, uint32_t, -, 0, UINT32_MAX) + +DO_SAT(gvec_sqsub_b, int, int8_t, int8_t, -, INT8_MIN, INT8_MAX) +DO_SAT(gvec_sqsub_h, int, int16_t, int16_t, -, INT16_MIN, INT16_MAX) +DO_SAT(gvec_sqsub_s, int64_t, int32_t, int32_t, -, INT32_MIN, INT32_MAX) + +#undef DO_SAT + +void HELPER(gvec_uqadd_d)(void *vd, void *vq, void *vn, + void *vm, uint32_t desc) +{ + intptr_t i, oprsz = simd_oprsz(desc); + uint64_t *d = vd, *n = vn, *m = vm; + bool q = false; + + for (i = 0; i < oprsz / 8; i++) { + uint64_t nn = n[i], mm = m[i], dd = nn + mm; + if (dd < nn) { + dd = UINT64_MAX; + q = true; + } + d[i] = dd; + } + if (q) { + uint32_t *qc = vq; + qc[0] = 1; + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_uqsub_d)(void *vd, void *vq, void *vn, + void *vm, uint32_t desc) +{ + intptr_t i, oprsz = simd_oprsz(desc); + uint64_t *d = vd, *n = vn, *m = vm; + bool q = false; + + for (i = 0; i < oprsz / 8; i++) { + uint64_t nn = n[i], mm = m[i], dd = nn - mm; + if (nn < mm) { + dd = 0; + q = true; + } + d[i] = dd; + } + if (q) { + uint32_t *qc = vq; + qc[0] = 1; + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_sqadd_d)(void *vd, void *vq, void *vn, + void *vm, uint32_t desc) +{ + intptr_t i, oprsz = simd_oprsz(desc); + int64_t *d = vd, *n = vn, *m = vm; + bool q = false; + + for (i = 0; i < oprsz / 8; i++) { + int64_t nn = n[i], mm = m[i], dd = nn + mm; + if (((dd ^ nn) & ~(nn ^ mm)) & INT64_MIN) { + dd = (nn >> 63) ^ ~INT64_MIN; + q = true; + } + d[i] = dd; + } + if (q) { + uint32_t *qc = vq; + qc[0] = 1; + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} + +void HELPER(gvec_sqsub_d)(void *vd, void *vq, void *vn, + void *vm, uint32_t desc) +{ + intptr_t i, oprsz = simd_oprsz(desc); + int64_t *d = vd, *n = vn, *m = vm; + bool q = false; + + for (i = 0; i < oprsz / 8; i++) { + int64_t nn = n[i], mm = m[i], dd = nn - mm; + if (((dd ^ nn) & (nn ^ mm)) & INT64_MIN) { + dd = (nn >> 63) ^ ~INT64_MIN; + q = true; + } + d[i] = dd; + } + if (q) { + uint32_t *qc = vq; + qc[0] = 1; + } + clear_tail(d, oprsz, simd_maxsz(desc)); +} From patchwork Sat Feb 9 03:38:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157912 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp242581jaa; Fri, 8 Feb 2019 19:48:15 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia8vOIxmVCtr7Ss0OqyR+daI4HOKKWvFfyGkaHy4727cL0uO271OBhsxO81tkXQdAkktpKr X-Received: by 2002:a5d:6810:: with SMTP id w16mr2710207wru.62.1549684095773; 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[97.126.115.157]) by smtp.gmail.com with ESMTPSA id s84sm6340737pfi.15.2019.02.08.19.39.07 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 08 Feb 2019 19:39:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Fri, 8 Feb 2019 19:38:47 -0800 Message-Id: <20190209033847.9014-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190209033847.9014-1-richard.henderson@linaro.org> References: <20190209033847.9014-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::52d Subject: [Qemu-devel] [PATCH v3 12/12] target/arm: Add missing clear_tail calls X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Fortunately, the functions affected are so far only called from SVE, so there is no tail to be cleared. But as we convert more of AdvSIMD to gvec, this will matter. Signed-off-by: Richard Henderson --- target/arm/vec_helper.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.2 diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 10f17e4b5c..dfc635cf9a 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -638,6 +638,7 @@ void HELPER(NAME)(void *vd, void *vn, void *stat, uint32_t desc) \ for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ d[i] = FUNC(n[i], stat); \ } \ + clear_tail(d, oprsz, simd_maxsz(desc)); \ } DO_2OP(gvec_frecpe_h, helper_recpe_f16, float16) @@ -688,6 +689,7 @@ void HELPER(NAME)(void *vd, void *vn, void *vm, void *stat, uint32_t desc) \ for (i = 0; i < oprsz / sizeof(TYPE); i++) { \ d[i] = FUNC(n[i], m[i], stat); \ } \ + clear_tail(d, oprsz, simd_maxsz(desc)); \ } DO_3OP(gvec_fadd_h, float16_add, float16)