From patchwork Sun Aug 28 13:33:26 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 600779 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ADDBFECAAD5 for ; Sun, 28 Aug 2022 13:33:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229511AbiH1Ndo (ORCPT ); Sun, 28 Aug 2022 09:33:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60948 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229737AbiH1Ndm (ORCPT ); Sun, 28 Aug 2022 09:33:42 -0400 Received: from mail-ej1-x636.google.com (mail-ej1-x636.google.com [IPv6:2a00:1450:4864:20::636]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8688024F04 for ; Sun, 28 Aug 2022 06:33:40 -0700 (PDT) Received: by mail-ej1-x636.google.com with SMTP id p16so7864520ejb.9 for ; Sun, 28 Aug 2022 06:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=b/btFehREFVzIjnfwZ0fR/od68XSqMjGfHOju/rQyoU=; b=mGwOSs8uRwcBFikc4fKzn6cA61x5ln2dvWQFrU+kdsYkjmEo0WaZUZjIKRHNRtRRN3 qcsD1gSixY0iR9W98/wSTVXkGDCpFsEbjWbU4VEyJjLtkoiKZ+op4cWQt+B5zgbLJKuA uAI962pJ3qTQHXcE0S/0MG238FDGTgRiIpm+g= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=b/btFehREFVzIjnfwZ0fR/od68XSqMjGfHOju/rQyoU=; b=gSMnOXhTccAuXZqGtaoYrA3d4CcxIYCqKlfN5QiWQp8f/YNXgMnhGyD4mt1MkmUVHi vcIKEpo4Ozvv6wd1c0rMP+snADD5p3EgGJULDEUmXmIefZmyverchd3CKjej1yAKgY6g qYe47caW1Ph417FmygkWSNgvwwg2igKiKqhc4lloUk2bamQD0yIoG7Syp/Y4BWb3OCVX CNcvif2DrzEns4M86ihMmpube9rajwjyG1+TnyppnCcnixWk0l7XU66UnU92yKMRVaKm /9e7wBzFFjMixYGHzLSClBjXUY2GacL3YHGlc24G3b35Dr11Vcn14v22Hws7Ac6o/Eoj 7LGg== X-Gm-Message-State: ACgBeo2TWNStZOqiFTHwCoEESgUk2AnZGbXfMAVxGRlmS97bAGb+2S+p KFwPrDkAaHpX1FedygGuACMQQw== X-Google-Smtp-Source: AA6agR4bOIGmsAhChMVhMNdemmW9m88gH6GVC5wHtB5s/IJcxN+33iJUWoFivYFrRrVDuzRxW+6wmA== X-Received: by 2002:a17:906:eec7:b0:733:189f:b07a with SMTP id wu7-20020a170906eec700b00733189fb07amr10600791ejb.230.1661693619043; Sun, 28 Aug 2022 06:33:39 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-31-31-9.retail.telecomitalia.it. [79.31.31.9]) by smtp.gmail.com with ESMTPSA id u26-20020a1709064ada00b007313a25e56esm3247669ejt.29.2022.08.28.06.33.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Aug 2022 06:33:38 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Marc Kleine-Budde , Alexandre Torgue , michael@amarulasolutions.com, Amarula patchwork , Vincent Mailhol , Krzysztof Kozlowski , Rob Herring , Dario Binacchi , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Krzysztof Kozlowski , Maxime Coquelin , Paolo Abeni , Rob Herring , Wolfgang Grandegger , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-can@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, netdev@vger.kernel.org Subject: [RFC PATCH v3 1/4] dt-bindings: net: can: add STM32 bxcan DT bindings Date: Sun, 28 Aug 2022 15:33:26 +0200 Message-Id: <20220828133329.793324-2-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220828133329.793324-1-dario.binacchi@amarulasolutions.com> References: <20220828133329.793324-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add documentation of device tree bindings for the STM32 basic extended CAN (bxcan) controller. Signed-off-by: Dario Binacchi --- Changes in v3: - Remove 'Dario Binacchi ' SOB. - Add description to the parent of the two child nodes. - Move "patterProperties:" after "properties: in top level before "required". - Add "clocks" to the "required:" list of the child nodes. Changes in v2: - Change the file name into 'st,stm32-bxcan-core.yaml'. - Rename compatibles: - st,stm32-bxcan-core -> st,stm32f4-bxcan-core - st,stm32-bxcan -> st,stm32f4-bxcan - Rename master property to st,can-master. - Remove the status property from the example. - Put the node child properties as required. .../bindings/net/can/st,stm32-bxcan.yaml | 142 ++++++++++++++++++ 1 file changed, 142 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml diff --git a/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml new file mode 100644 index 000000000000..3278c724e6f5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/can/st,stm32-bxcan.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/can/st,stm32-bxcan.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: STMicroelectronics bxCAN controller + +description: STMicroelectronics BxCAN controller for CAN bus + +maintainers: + - Dario Binacchi + +allOf: + - $ref: can-controller.yaml# + +properties: + compatible: + description: + It manages the access to the 512-bytes SRAM memory shared by the + two bxCAN cells (CAN1 master and CAN2 slave) in dual CAN peripheral + configuration. + enum: + - st,stm32f4-bxcan-core + + reg: + maxItems: 1 + + resets: + maxItems: 1 + + clocks: + description: + Input clock for registers access + maxItems: 1 + + '#address-cells': + const: 1 + + '#size-cells': + const: 0 + +patternProperties: + "^can@[0-9]+$": + type: object + description: + A CAN block node contains two subnodes, representing each one a CAN + instance available on the machine. + + properties: + compatible: + enum: + - st,stm32f4-bxcan + + st,can-master: + description: + Master and slave mode of the bxCAN peripheral is only relevant + if the chip has two CAN peripherals. In that case they share + some of the required logic, and that means you cannot use the + slave CAN without the master CAN. + type: boolean + + reg: + description: | + Offset of CAN instance in CAN block. Valid values are: + - 0x0: CAN1 + - 0x400: CAN2 + maxItems: 1 + + interrupts: + items: + - description: transmit interrupt + - description: FIFO 0 receive interrupt + - description: FIFO 1 receive interrupt + - description: status change error interrupt + + interrupt-names: + items: + - const: tx + - const: rx0 + - const: rx1 + - const: sce + + resets: + maxItems: 1 + + clocks: + description: + Input clock for registers access + maxItems: 1 + + additionalProperties: false + + required: + - compatible + - reg + - interrupts + - resets + - clocks + +required: + - compatible + - reg + - resets + - clocks + - '#address-cells' + - '#size-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + can: can@40006400 { + compatible = "st,stm32f4-bxcan-core"; + reg = <0x40006400 0x800>; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + #address-cells = <1>; + #size-cells = <0>; + + can1: can@0 { + compatible = "st,stm32f4-bxcan"; + reg = <0x0>; + interrupts = <19>, <20>, <21>, <22>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN1)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN1)>; + st,can-master; + }; + + can2: can@400 { + compatible = "st,stm32f4-bxcan"; + reg = <0x400>; + interrupts = <63>, <64>, <65>, <66>; + interrupt-names = "tx", "rx0", "rx1", "sce"; + resets = <&rcc STM32F4_APB1_RESET(CAN2)>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(CAN2)>; + }; + }; From patchwork Sun Aug 28 13:33:28 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 600778 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D144BC0502A for ; Sun, 28 Aug 2022 13:33:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229842AbiH1Ndz (ORCPT ); Sun, 28 Aug 2022 09:33:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229737AbiH1Ndp (ORCPT ); Sun, 28 Aug 2022 09:33:45 -0400 Received: from mail-ed1-x52a.google.com (mail-ed1-x52a.google.com [IPv6:2a00:1450:4864:20::52a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7791624F1F for ; Sun, 28 Aug 2022 06:33:44 -0700 (PDT) Received: by mail-ed1-x52a.google.com with SMTP id c59so1071714edf.10 for ; Sun, 28 Aug 2022 06:33:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=olNapHSIxEXV/j68X2DSb6GA5s0CD+ILvvqYswhlRrM=; b=ptcQCXsHLLK3toTiJrVtNK1GifF5qfJRikV8CrxsZ2iTVLvrah6mSolRcQRnLycQ3P 2dP3PGOipJStLIrORwrRYWysk8kuT3rvjaZt1boB1h/6cJ9L5HimwPp4tZMPDtM5TxOb OIRFEAgYPxIOIHEbFztlN6D76NLngRU5Kg8Cc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=olNapHSIxEXV/j68X2DSb6GA5s0CD+ILvvqYswhlRrM=; b=AlQj9eYvjRjy6XDQKl7wz4N9e0lHLA1a+cRwuuw9sEAHBV9BFh1i+n5ojNpJtnooJp PcWeazVnj14r70FALrL4MLDb0ZDqeoYcdGycAhztvdMWd1lAHImmfaZAkCDcfVp4dQbb EKJCgkqY/jM0QisvnzN4wLSywSoTU1xq6Tu+sGL/SCDijWUtN48g56529KWXRnkHitbj JwfcnTlcpnpx3+wSv1VzLRTOwOPiUttr3bQ2adMm04Km/4bf3N0kU57fgxYcyfjX8M33 kI/hMFv4jxnWwqZYc4A4lu8MIXf0dKpQr75V6ljSr7NDaPPusnAZ3OiD+A44zy2Qk1y7 LZxw== X-Gm-Message-State: ACgBeo3jIbcHLirb4e4R5grU5c+4mf5NqA1JwGbUoDR6s6DMYFkV7JsQ L9y+WOivvLT+adMLXlgAafFzlg== X-Google-Smtp-Source: AA6agR4C0hyJ+1kxqMtNtBNnuPblwiwNAMjYnzqwkv9YZm3cFwmNajdCri4JsEkrluZM4XKIVzLCfw== X-Received: by 2002:a05:6402:3596:b0:447:11ea:362d with SMTP id y22-20020a056402359600b0044711ea362dmr13480103edc.117.1661693622388; Sun, 28 Aug 2022 06:33:42 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.homenet.telecomitalia.it (host-79-31-31-9.retail.telecomitalia.it. [79.31.31.9]) by smtp.gmail.com with ESMTPSA id u26-20020a1709064ada00b007313a25e56esm3247669ejt.29.2022.08.28.06.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Aug 2022 06:33:41 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Marc Kleine-Budde , Alexandre Torgue , michael@amarulasolutions.com, Amarula patchwork , Vincent Mailhol , Krzysztof Kozlowski , Rob Herring , Dario Binacchi , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [RFC PATCH v3 3/4] ARM: dts: stm32: add pin map for CAN controller on stm32f4 Date: Sun, 28 Aug 2022 15:33:28 +0200 Message-Id: <20220828133329.793324-4-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220828133329.793324-1-dario.binacchi@amarulasolutions.com> References: <20220828133329.793324-1-dario.binacchi@amarulasolutions.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pin configurations for using CAN controller on stm32f469-disco board. They are located on the Arduino compatible connector CN5 (CAN1) and on the extension connector CN12 (CAN2). Signed-off-by: Dario Binacchi --- Changes in v3: - Remove 'Dario Binacchi ' SOB. - Remove a blank line. Changes in v2: - Remove a blank line. arch/arm/boot/dts/stm32f4-pinctrl.dtsi | 30 ++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi index 500bcc302d42..8a4d51f97248 100644 --- a/arch/arm/boot/dts/stm32f4-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32f4-pinctrl.dtsi @@ -448,6 +448,36 @@ pins2 { slew-rate = <2>; }; }; + + can1_pins_a: can1-0 { + pins1 { + pinmux = ; /* CAN1_TX */ + }; + pins2 { + pinmux = ; /* CAN1_RX */ + bias-pull-up; + }; + }; + + can2_pins_a: can2-0 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; + + can2_pins_b: can2-1 { + pins1 { + pinmux = ; /* CAN2_TX */ + }; + pins2 { + pinmux = ; /* CAN2_RX */ + bias-pull-up; + }; + }; }; }; };