From patchwork Thu Feb 7 11:17:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 157696 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp516673jaa; Thu, 7 Feb 2019 03:17:44 -0800 (PST) X-Google-Smtp-Source: AHgI3IbRUhPgsyZREG/cWi35ZVxueguQMbmtrHHjRiYSP/kiIj4jNIHWycdEJ480HSYzp3WSxT2G X-Received: by 2002:a17:902:4464:: with SMTP id k91mr16097209pld.13.1549538264862; Thu, 07 Feb 2019 03:17:44 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549538264; cv=none; d=google.com; s=arc-20160816; b=FLyUO0XuIqaI+nyn68B/hMYVVCPfgvm7LugHgChV03l/lXqueVAEIg8/5rKYg1Xtyd RTbt/QBDAwGN+IRyR2WlNaU2b4JTjEr4nfYJ7HOuU+kIbJ75HKnsmi6jd23FcPlOyPHh Y3kx4dK9/t8R6JO0vQqiVdScZR4b1IQPTcfGBzxiD7K1geHaTLNcW1PMc74AOgQ+hKzC U6UGv9AfLmMBZ2fR8pw+ST256RSdvIJXx0hELj769VF7wgVdvX+OsTYPr4REpem7Pcim IxqdfC5JHgq77XjoGHN9c7YbCxc5jhIO/VpEd68fmUWoT6FQjAsC2BHRZgQjJlR95/FX CtHA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=LbpoBRsypdTGREkLevfYOmN/+f576KJEExTxTQozG1I=; b=xZf6auKKQQNSiMnmGc2pCKLEUadcZUlIjYX920MEEo+eo4Es3oEwsVeMIa/l+PxU9B +SthJh8UnO5uZXYvdc7Zfc13fElrBQBriUUatLJk/I8bJGASzsrxIIBLoJgsxrejZrMv BtudzOwXi1zep355FWuX8RXugyRgvXHrUpLy3aCwT2BrI+Kq6tLp/V7XsZdC1uBjoGHx SfY1XmtXa+Q2zO4Hm+oBfoFqOIzj1R5GfkDqr2Xi4JKJPr943s6TLcwnhIC9UcDQ5tqP 9fy/xabsM3lgKzA3rACAvQ4LZG66vdwYRSU8NYUsQ2qmHrXDyC7NxEIWWSEKNMMYi56S ip5Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xekeLArv; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[95.121.90.42]) by smtp.gmail.com with ESMTPSA id a62sm24490224wmf.47.2019.02.07.03.17.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Feb 2019 03:17:40 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, robh@kernel.org, bjorn.andersson@linaro.org Cc: swboyd@chromium.org, andy.gross@linaro.org, shawn.guo@linaro.org, gregkh@linuxfoundation.org, mark.rutland@arm.com, kishon@ti.com, jackp@codeaurora.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, khasim.mohammed@linaro.org Subject: [PATCH v4 1/4] dt-bindings: phy: remove qcom-dwc3-usb-phy Date: Thu, 7 Feb 2019 12:17:31 +0100 Message-Id: <20190207111734.24171-2-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190207111734.24171-1-jorge.ramirez-ortiz@linaro.org> References: <20190207111734.24171-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This binding is not used by any driver. Signed-off-by: Jorge Ramirez-Ortiz --- .../bindings/phy/qcom-dwc3-usb-phy.txt | 37 ------------------- 1 file changed, 37 deletions(-) delete mode 100644 Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt -- 2.20.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt b/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt deleted file mode 100644 index a1697c27aecd..000000000000 --- a/Documentation/devicetree/bindings/phy/qcom-dwc3-usb-phy.txt +++ /dev/null @@ -1,37 +0,0 @@ -Qualcomm DWC3 HS AND SS PHY CONTROLLER --------------------------------------- - -DWC3 PHY nodes are defined to describe on-chip Synopsis Physical layer -controllers. Each DWC3 PHY controller should have its own node. - -Required properties: -- compatible: should contain one of the following: - - "qcom,dwc3-hs-usb-phy" for High Speed Synopsis PHY controller - - "qcom,dwc3-ss-usb-phy" for Super Speed Synopsis PHY controller -- reg: offset and length of the DWC3 PHY controller register set -- #phy-cells: must be zero -- clocks: a list of phandles and clock-specifier pairs, one for each entry in - clock-names. -- clock-names: Should contain "ref" for the PHY reference clock - -Optional clocks: - "xo" External reference clock - -Example: - phy@100f8800 { - compatible = "qcom,dwc3-hs-usb-phy"; - reg = <0x100f8800 0x30>; - clocks = <&gcc USB30_0_UTMI_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - }; - - phy@100f8830 { - compatible = "qcom,dwc3-ss-usb-phy"; - reg = <0x100f8830 0x30>; - clocks = <&gcc USB30_0_MASTER_CLK>; - clock-names = "ref"; - #phy-cells = <0>; - - }; From patchwork Thu Feb 7 11:17:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 157699 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp516976jaa; Thu, 7 Feb 2019 03:18:02 -0800 (PST) X-Google-Smtp-Source: AHgI3IZNFoOh9JM3CRcQRDWTTgUIjimSFs/706NG8+1gh822VddFksPuUMXmOw0/qqbVQKlXUVjQ X-Received: by 2002:a17:902:1022:: with SMTP id b31mr15805102pla.141.1549538281964; Thu, 07 Feb 2019 03:18:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549538281; cv=none; d=google.com; s=arc-20160816; b=lkxeBXlXHqA8f7rXDZPz9bF5T6zzFo3TIqdqJWuJQg9cVNFVZ7b/RO9BYHzhHWQtxT HFCsCGZxclyH5p95sN5uWA4z0Mio80R/t3oZWWwsjoztNooqsF6gn7O07EeDU6x3mjuf 1Q8OU1UxxbNtybntFpWE+96+kyjvce9iwL42BUfHSPKtK47PtSIlRnS2oyD5G6QW3ynk iHuyW5f/sqLIHSUUyeeHI6yTYOw35Tc4d6/+lHzdexvtRVLfbP0JbqQDm6WLAjCw/S1h 46cCMno6Ws+JugfWZCxLT8eQjdpeBeteoesljw7e4vE2oco1XWoKzTPVa1LAHlSA29+H qhLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=oBG4BBi2BLLQTeAw9jQ6rQjuF426ty7AkYNuZtLk2uo=; b=B8KFMu2rdYQE0j/agf2kkYeBarnM2vA7Z/pBxil1uFT/hTnPYoqdDYZptoUptDsKDa abJyxSNhDGXPpXRVYtYv1E5yhqaZB8tPpNg7BLlBjcQEEWeyL4mLT96WQewS7yj1rKEs Gcy34LtpjKjmoDb+H63r4GB9wUzHmCf1wQRnR9t8LphZBlPWRRqhMIa7q3bUn7E4mwi3 m2zWEe54PDMAkPp/78CukaU1y7zNmuKUWXOriZfuTqrWS5kgimQnmdQvHiog8kq9PlRj YX7hRv2lwK6jQMpXWzrb1eB2QT2MeaydkWh0RvSSQmO0LXKVsmOtK8yVXZ/jxR5vdxuz 54wA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=uRsmHZv0; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[95.121.90.42]) by smtp.gmail.com with ESMTPSA id a62sm24490224wmf.47.2019.02.07.03.17.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Feb 2019 03:17:42 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, robh@kernel.org, bjorn.andersson@linaro.org Cc: swboyd@chromium.org, andy.gross@linaro.org, shawn.guo@linaro.org, gregkh@linuxfoundation.org, mark.rutland@arm.com, kishon@ti.com, jackp@codeaurora.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, khasim.mohammed@linaro.org Subject: [PATCH v4 2/4] dt-bindings: connector: Add vbus-supply property Date: Thu, 7 Feb 2019 12:17:32 +0100 Message-Id: <20190207111734.24171-3-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190207111734.24171-1-jorge.ramirez-ortiz@linaro.org> References: <20190207111734.24171-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Some phys might need to control their VBUS regulators while not being supplied by them. If such support is required, use the vbus-supply property in the connector to retrieve the regulator. Signed-off-by: Jorge Ramirez-Ortiz --- Documentation/devicetree/bindings/connector/usb-connector.txt | 4 ++++ 1 file changed, 4 insertions(+) -- 2.20.1 Reviewed-by: Rob Herring diff --git a/Documentation/devicetree/bindings/connector/usb-connector.txt b/Documentation/devicetree/bindings/connector/usb-connector.txt index a9a2f2fc44f2..2ad22dd6dc39 100644 --- a/Documentation/devicetree/bindings/connector/usb-connector.txt +++ b/Documentation/devicetree/bindings/connector/usb-connector.txt @@ -16,6 +16,10 @@ Optional properties: non-fullsize connectors: "mini", "micro". - self-powered: Set this property if the usb device that has its own power source. +- vbus-supply: + Value type: + Definition: phandle to the regulator VBUS supply node. Set this property if + the connector is supplied by VBUS. Optional properties for usb-c-connector: - power-role: should be one of "source", "sink" or "dual"(DRP) if typec From patchwork Thu Feb 7 11:17:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jorge Ramirez-Ortiz X-Patchwork-Id: 157698 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp516796jaa; Thu, 7 Feb 2019 03:17:51 -0800 (PST) X-Google-Smtp-Source: AHgI3Ia4PapAg/5wgxstSk/1yv30OKP/LwgRBszp+ZJHaS3UfkieS14I3mfjSVOH+WzwJ99a9mwx X-Received: by 2002:a17:902:7581:: with SMTP id j1mr15824250pll.260.1549538271462; Thu, 07 Feb 2019 03:17:51 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549538271; cv=none; d=google.com; s=arc-20160816; b=WOlDttPLhSTfOD5DfwhIw5G0L/E6EqEC1HaD6fpfudGcCSsnL2welQEIbyIkgQdWOT WfA60D5xBuafCuaUzDL+DRhwksDPHTeVvjfRYbdxi/q3WHADSGEs8OnStfHxGy5G9jfP Amt0cWnsVN2H0Ii68E2mE8Cuwlhzyg2poBYChNb77VPFCdF4V6aZ093O/eqXDIGwoChA 8jzRlxK3KD7Z4VTZk6ZfMY18Ga8cWl091SDxTe19ROn5XTwBOZZ3Mpr5yTTU9Kfj5pnX RzSqhyc0hTmbCQup3AeW+9g0kNaV10y5qz9AMtE5MGcaCoaqT0/pR6I04Fv+k0zorC/u 6H/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:content-transfer-encoding:mime-version :references:in-reply-to:message-id:date:subject:cc:to:from :dkim-signature; bh=zTy2BpKVewWPthIYhj+giYm90T25s2YtqlFNS6fzNgk=; b=SrjuNQuIgIGla1p4P5OId71Z9k/9CfL6MyGH71bnfMyu3UG0Uh6tB5/JOPk+zR2AE/ 0l6Q2vnJXSkP59BNp0cCiLWtLmDS04Ma7bwAgyWgsTIObkqa/oxprfQq6b53lVHTSWbI Woj/Ch/PS68Ox71y7kr/O6I1FIx1P/zarDtXuFeSc/EQJ+9S3ogZaLcaUZgQ97Uv8oBg tZdz7rwJ8Rcvq8NFnXsxF5pUMV0c/yJQZ3mIm5K703GijgGn9qf3U7BlwNn92CFI+98H 1TKRG2hvYkp9YF+VoHs73vY1WJojxlChqtCawIP8ShbNWOMnpWzuGMWwHamkCUNDoXlG vozg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XyC9zWg9; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[95.121.90.42]) by smtp.gmail.com with ESMTPSA id a62sm24490224wmf.47.2019.02.07.03.17.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 07 Feb 2019 03:17:44 -0800 (PST) From: Jorge Ramirez-Ortiz To: jorge.ramirez-ortiz@linaro.org, robh@kernel.org, bjorn.andersson@linaro.org Cc: swboyd@chromium.org, andy.gross@linaro.org, shawn.guo@linaro.org, gregkh@linuxfoundation.org, mark.rutland@arm.com, kishon@ti.com, jackp@codeaurora.org, devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-usb@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, khasim.mohammed@linaro.org Subject: [PATCH v4 4/4] phy: qualcomm: usb: Add SuperSpeed PHY driver Date: Thu, 7 Feb 2019 12:17:34 +0100 Message-Id: <20190207111734.24171-5-jorge.ramirez-ortiz@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190207111734.24171-1-jorge.ramirez-ortiz@linaro.org> References: <20190207111734.24171-1-jorge.ramirez-ortiz@linaro.org> MIME-Version: 1.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Controls Qualcomm's SS phy 1.0.0 implemented in the QCS404 and some other Qualcomm platforms. Based on Sriharsha Allenki's original code. Signed-off-by: Jorge Ramirez-Ortiz --- drivers/phy/qualcomm/Kconfig | 11 + drivers/phy/qualcomm/Makefile | 1 + drivers/phy/qualcomm/phy-qcom-usb-ss.c | 322 +++++++++++++++++++++++++ 3 files changed, 334 insertions(+) create mode 100644 drivers/phy/qualcomm/phy-qcom-usb-ss.c -- 2.20.1 diff --git a/drivers/phy/qualcomm/Kconfig b/drivers/phy/qualcomm/Kconfig index 32f7d34eb784..a8dc550d25fb 100644 --- a/drivers/phy/qualcomm/Kconfig +++ b/drivers/phy/qualcomm/Kconfig @@ -82,3 +82,14 @@ config PHY_QCOM_USB_HSIC select GENERIC_PHY help Support for the USB HSIC ULPI compliant PHY on QCOM chipsets. + +config PHY_QCOM_USB_SS + tristate "Qualcomm USB SS PHY driver" + depends on ARCH_QCOM || COMPILE_TEST + depends on EXTCON || !EXTCON # if EXTCON=m, this cannot be built-in + select GENERIC_PHY + help + Enable this to support the Super-Speed USB transceiver on Qualcomm + chips. This driver supports the PHY which uses the QSCRATCH-based + register set for its control sequences, normally paired with newer + DWC3-based Super-Speed controllers on Qualcomm SoCs. diff --git a/drivers/phy/qualcomm/Makefile b/drivers/phy/qualcomm/Makefile index c56efd3af205..d594d532d137 100644 --- a/drivers/phy/qualcomm/Makefile +++ b/drivers/phy/qualcomm/Makefile @@ -9,3 +9,4 @@ obj-$(CONFIG_PHY_QCOM_UFS_14NM) += phy-qcom-ufs-qmp-14nm.o obj-$(CONFIG_PHY_QCOM_UFS_20NM) += phy-qcom-ufs-qmp-20nm.o obj-$(CONFIG_PHY_QCOM_USB_HS) += phy-qcom-usb-hs.o obj-$(CONFIG_PHY_QCOM_USB_HSIC) += phy-qcom-usb-hsic.o +obj-$(CONFIG_PHY_QCOM_USB_SS) += phy-qcom-usb-ss.o diff --git a/drivers/phy/qualcomm/phy-qcom-usb-ss.c b/drivers/phy/qualcomm/phy-qcom-usb-ss.c new file mode 100644 index 000000000000..cf3216669f78 --- /dev/null +++ b/drivers/phy/qualcomm/phy-qcom-usb-ss.c @@ -0,0 +1,322 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2012-2014,2017 The Linux Foundation. All rights reserved. + * Copyright (c) 2018, Linaro Limited + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define PHY_CTRL0 0x6C +#define PHY_CTRL1 0x70 +#define PHY_CTRL2 0x74 +#define PHY_CTRL4 0x7C + +/* PHY_CTRL bits */ +#define REF_PHY_EN BIT(0) +#define LANE0_PWR_ON BIT(2) +#define SWI_PCS_CLK_SEL BIT(4) +#define TST_PWR_DOWN BIT(4) +#define PHY_RESET BIT(7) + +#define NUM_BULK_CLKS 3 +#define NUM_BULK_REGS 2 + +struct ssphy_priv { + void __iomem *base; + struct device *dev; + struct reset_control *reset_com; + struct reset_control *reset_phy; + struct regulator_bulk_data regs[NUM_BULK_REGS]; + struct clk_bulk_data clks[NUM_BULK_CLKS]; + struct vbus_regulator { + struct regulator *consumer; + bool voted; /* regulator balancing: extcon controlled voltage */ + } vbus; + enum phy_mode mode; +}; + +static inline void qcom_ssphy_updatel(void __iomem *addr, u32 mask, u32 val) +{ + writel((readl(addr) & ~mask) | val, addr); +} + +static int qcom_ssphy_vbus_enable(struct vbus_regulator *vbus) +{ + int ret; + + if (vbus->voted) + return 0; + + ret = regulator_enable(vbus->consumer); + if (!ret) { + /* use count only increments on success */ + vbus->voted = true; + } + + return ret; +} + +static int qcom_ssphy_vbus_disable(struct vbus_regulator *vbus) +{ + if (!vbus->voted) + return 0; + + vbus->voted = false; + + return regulator_disable(vbus->consumer); +} + +static int qcom_ssphy_vbus_ctrl(struct vbus_regulator *vbus, enum phy_mode mode) +{ + if (mode == PHY_MODE_INVALID) + return 0; + + /* gadget attached */ + if (mode == PHY_MODE_USB_HOST) + return qcom_ssphy_vbus_enable(vbus); + + /* USB_DEVICE: gadget removed: enable detection */ + return qcom_ssphy_vbus_disable(vbus); +} + +static int qcom_ssphy_do_reset(struct ssphy_priv *priv) +{ + int ret; + + if (!priv->reset_com) { + qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, + PHY_RESET); + usleep_range(10, 20); + qcom_ssphy_updatel(priv->base + PHY_CTRL1, PHY_RESET, 0); + } else { + ret = reset_control_assert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "Failed to assert reset com\n"); + return ret; + } + + ret = reset_control_assert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "Failed to assert reset phy\n"); + return ret; + } + + usleep_range(10, 20); + + ret = reset_control_deassert(priv->reset_com); + if (ret) { + dev_err(priv->dev, "Failed to deassert reset com\n"); + return ret; + } + + ret = reset_control_deassert(priv->reset_phy); + if (ret) { + dev_err(priv->dev, "Failed to deassert reset phy\n"); + return ret; + } + } + + return 0; +} + +static int qcom_ssphy_power_on(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + int ret; + + ret = regulator_bulk_enable(NUM_BULK_REGS, priv->regs); + if (ret) + return ret; + + ret = clk_bulk_prepare_enable(NUM_BULK_CLKS, priv->clks); + if (ret) + goto err_disable_regulator; + + /* depending on the extcon reported mode, enable or disable vbus */ + ret = qcom_ssphy_vbus_ctrl(&priv->vbus, priv->mode); + if (ret) + goto err_disable_clock; + + ret = qcom_ssphy_do_reset(priv); + if (ret) + goto err_disable_vbus; + + writeb(SWI_PCS_CLK_SEL, priv->base + PHY_CTRL0); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, LANE0_PWR_ON); + qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, REF_PHY_EN); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, 0); + + return 0; + +err_disable_vbus: + qcom_ssphy_vbus_disable(&priv->vbus); +err_disable_clock: + clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks); +err_disable_regulator: + regulator_bulk_disable(NUM_BULK_REGS, priv->regs); + + return ret; +} + +static int qcom_ssphy_power_off(struct phy *phy) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + + qcom_ssphy_updatel(priv->base + PHY_CTRL4, LANE0_PWR_ON, 0); + qcom_ssphy_updatel(priv->base + PHY_CTRL2, REF_PHY_EN, 0); + qcom_ssphy_updatel(priv->base + PHY_CTRL4, TST_PWR_DOWN, TST_PWR_DOWN); + + clk_bulk_disable_unprepare(NUM_BULK_CLKS, priv->clks); + regulator_bulk_disable(NUM_BULK_REGS, priv->regs); + qcom_ssphy_vbus_disable(&priv->vbus); + + return 0; +} + +static int qcom_ssphy_init_clock(struct ssphy_priv *priv) +{ + priv->clks[0].id = "ref"; + priv->clks[1].id = "phy"; + priv->clks[2].id = "pipe"; + + return devm_clk_bulk_get(priv->dev, NUM_BULK_CLKS, priv->clks); +} + +static int qcom_ssphy_init_regulator(struct ssphy_priv *priv) +{ + int ret; + + priv->regs[0].supply = "vdd"; + priv->regs[1].supply = "vdda1p8"; + ret = devm_regulator_bulk_get(priv->dev, NUM_BULK_REGS, priv->regs); + if (ret) { + if (ret != -EPROBE_DEFER) + dev_err(priv->dev, "Failed to get regulators\n"); + return ret; + } + + priv->vbus.voted = false; + priv->vbus.consumer = devm_regulator_get(priv->dev, "vbus"); + if (IS_ERR(priv->vbus.consumer)) { + ret = PTR_ERR(priv->vbus.consumer); + if (ret != -EPROBE_DEFER) + dev_err(priv->dev, "Failed to get vbus regulator\n"); + } + + return ret; +} + +static int qcom_ssphy_init_reset(struct ssphy_priv *priv) +{ + priv->reset_com = devm_reset_control_get_optional(priv->dev, "com"); + if (IS_ERR(priv->reset_com)) { + dev_err(priv->dev, "Failed to get reset control com\n"); + return PTR_ERR(priv->reset_com); + } + + if (priv->reset_com) { + /* if reset_com is present, reset_phy is no longer optional */ + priv->reset_phy = devm_reset_control_get(priv->dev, "phy"); + if (IS_ERR(priv->reset_phy)) { + dev_err(priv->dev, "Failed to get reset control phy\n"); + return PTR_ERR(priv->reset_phy); + } + } + + return 0; +} + +static int qcom_ssphy_set_mode(struct phy *phy, enum phy_mode mode, int submode) +{ + struct ssphy_priv *priv = phy_get_drvdata(phy); + + if (mode != PHY_MODE_USB_HOST && mode != PHY_MODE_USB_DEVICE) + return -EINVAL; + + priv->mode = mode; + dev_dbg(priv->dev, "mode %d\n", mode); + + return qcom_ssphy_vbus_ctrl(&priv->vbus, priv->mode); +} + +static const struct phy_ops qcom_ssphy_ops = { + .set_mode = qcom_ssphy_set_mode, + .power_off = qcom_ssphy_power_off, + .power_on = qcom_ssphy_power_on, + .owner = THIS_MODULE, +}; + +static int qcom_ssphy_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct phy_provider *provider; + struct ssphy_priv *priv; + struct resource *res; + struct phy *phy; + int ret; + + priv = devm_kzalloc(dev, sizeof(struct ssphy_priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->dev = dev; + priv->mode = PHY_MODE_INVALID; + + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + priv->base = devm_ioremap_resource(dev, res); + if (IS_ERR(priv->base)) + return PTR_ERR(priv->base); + + ret = qcom_ssphy_init_clock(priv); + if (ret) + return ret; + + ret = qcom_ssphy_init_reset(priv); + if (ret) + return ret; + + ret = qcom_ssphy_init_regulator(priv); + if (ret) + return ret; + + phy = devm_phy_create(dev, dev->of_node, &qcom_ssphy_ops); + if (IS_ERR(phy)) { + dev_err(dev, "Failed to create the SS phy\n"); + return PTR_ERR(phy); + } + + phy_set_drvdata(phy, priv); + + provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); + + return PTR_ERR_OR_ZERO(provider); +} + +static const struct of_device_id qcom_ssphy_match[] = { + { .compatible = "qcom,snps-usb-ssphy", }, + { }, +}; +MODULE_DEVICE_TABLE(of, qcom_ssphy_match); + +static struct platform_driver qcom_ssphy_driver = { + .probe = qcom_ssphy_probe, + .driver = { + .name = "qcom_snps_usb_ssphy", + .of_match_table = qcom_ssphy_match, + }, +}; +module_platform_driver(qcom_ssphy_driver); + +MODULE_DESCRIPTION("Qualcomm SuperSpeed USB PHY driver"); +MODULE_LICENSE("GPL v2");