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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:01 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 01/10] target/arm: Don't corrupt high half of PMOVSR when cycle counter overflows Date: Mon, 22 Aug 2022 14:23:49 +0100 Message-Id: <20220822132358.3524971-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" When the cycle counter overflows, we are intended to set bit 31 in PMOVSR to indicate this. However a missing ULL suffix means that we end up setting all of bits 63-31. Fix the bug. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d7bc467a2a5..87c89748954 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1186,7 +1186,7 @@ static void pmccntr_op_start(CPUARMState *env) uint64_t overflow_mask = env->cp15.c9_pmcr & PMCRLC ? \ 1ull << 63 : 1ull << 31; if (env->cp15.c15_ccnt & ~new_pmccntr & overflow_mask) { - env->cp15.c9_pmovsr |= (1 << 31); + env->cp15.c9_pmovsr |= (1ULL << 31); pmu_update_irq(env); } From patchwork Mon Aug 22 13:23:50 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 599105 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp1652903mae; Mon, 22 Aug 2022 06:25:27 -0700 (PDT) X-Google-Smtp-Source: AA6agR6UAnSJ0R0FOIU3NeWZUnDKIl8/qIqRJqtNBmBS0DafBH22qQXFOcbFr2i3pGA5hNGwrLRX X-Received: by 2002:a37:db02:0:b0:6b8:cb84:be with SMTP id e2-20020a37db02000000b006b8cb8400bemr12385700qki.370.1661174727692; Mon, 22 Aug 2022 06:25:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661174727; cv=none; d=google.com; s=arc-20160816; b=qG9J+hZU5hHullSXE5fPb8UJLtJ3kdgdJRUQcchFOO10eltzUoG97Dq33TRucQcmL/ LME47RueduoPAK9+fIkLnWBb2Rpb3LTop12Jxbm0e1KkJhZJUjrKQpkn18jmmYnGUJqP PwvORLr2USWkquBffQKcQ8h6sJQKgGyG58aMLxcnJd7SMq2vsWc2J4K5WHcUu2ruzN9Y b7OW1MdX3GD9waIdC6drcHb67pP+CGrMmngNxDqRwNSwbOTjE3mUDkywNaCE5PQVNAG+ 1+6CvFQEWQKMQQ83NGkzuIeZMNwWgms7nGMtzYENut26fmnnLKF3YnLeRtBCSm9dAeOw b1VQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6876aucf7V//qP9FMCQSiTLY5Lo8nlXr95EXwywYwmM=; b=QKHteiB/AV+xqh1VNFeyTWzUwmxeUFNp5XLLdqb3NYYzo88l836/Gin0cVx+Ff2ZRs DJgzPCPN+Rkz+wOxAL0SF/aII8gTCmgAgCBlBN5atU53Q89q5pG3EAeQd+CyBXhplZGn MePw648jzq17bgWfKTy1QhL+yCM/RsAduz96pllu9Vdn33/0kfqPBKB1GPGvdwPOBdLo F9MLhPnxq5KQkyybWUKPEd9/3+TMe/Ypaib5kBiZJ1l8AP27Xu9PGCAGZfaHrOwkbURV hOutH+XzqQ4EgZ6EiQO6a5MdjVC2d17T7M0sDGSn41nH3SQEkx4KgQuB4ZSKSjFN0FkF Z9SA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hmp1kUo1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:02 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 02/10] target/arm: Correct value returned by pmu_counter_mask() Date: Mon, 22 Aug 2022 14:23:50 +0100 Message-Id: <20220822132358.3524971-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" pmu_counter_mask() accidentally returns a value with bits [63:32] set, because the expression it returns is evaluated as a signed value that gets sign-extended to 64 bits. Force the whole expression to be evaluated with 64-bit arithmetic with ULL suffixes. The main effect of this bug was that a guest could write to the bits in the high half of registers like PMCNTENSET_EL0 that are supposed to be RES0. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/internals.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index b8fefdff675..83526166de0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1296,7 +1296,7 @@ static inline uint32_t pmu_num_counters(CPUARMState *env) /* Bits allowed to be set/cleared for PMCNTEN* and PMINTEN* */ static inline uint64_t pmu_counter_mask(CPUARMState *env) { - return (1 << 31) | ((1 << pmu_num_counters(env)) - 1); + return (1ULL << 31) | ((1ULL << pmu_num_counters(env)) - 1); } #ifdef TARGET_AARCH64 From patchwork Mon Aug 22 13:23:51 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 599106 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp1653238mae; Mon, 22 Aug 2022 06:25:58 -0700 (PDT) X-Google-Smtp-Source: AA6agR6qJBDNfF6ImjiHVQ+/yU5+fOC67qVqyTew5VXhfHanJNqRVwOg8gyPPtRYYNvHGCHeojlJ X-Received: by 2002:ac8:7f0e:0:b0:344:8c43:e68d with SMTP id f14-20020ac87f0e000000b003448c43e68dmr15199703qtk.572.1661174758195; Mon, 22 Aug 2022 06:25:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661174758; cv=none; d=google.com; s=arc-20160816; b=lks/aY/ZPCi9chbYzFi4to7B1IFrQg5ZADZv2R9JSeaXfJMUVBbEuMYCDIIBX4KI1x uGtghnND65CkWk50D/n+tNCIbXlB9EVv2xzAFF9lL3L8t+5ryCVEad686U1mm/eEsBii xFmcors0I2gdyKSKU/j+/PU+vSCTkIy1QJAmsvy0sD1OPugYghmifV+ZjDZwg1LV1eiL 4QueqFAMwjzLMtg2OS6nls+o9NqgeBdqmqE5m9cfz48EpnEk1bYBPRAvjp6Yi+QnBytU h8QkLtpo6HBhMR9xLZnmukeHmY8DtTcPfibr9y5Ae1i0c8V9dxSh4J9Zjzw0ntz0JcXE lasg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=z3HMTNdAubSdARHZ1TYHyaaRh8yZaKl7eKMF8WGzqZY=; b=vzgFPvKDUf41KoZv8qPojBg3DNYI+XDPre0SW0zQ9YkmNjGg0hC+SnsgyDOAgclUkg ASl7Nao1SIUfjlfqOPMGUlfSpKkawkk8Crl6oym98rb61IGblYEgfnRuk/sqOpXpAkfl +4AHiL0FgAWoSjGG+qJiq9ahLAhXEnA/ZQ5vwD4EceOPEdOmws/4SyiCMvn23mGm0pg3 X1IAbi3VIrspeKLyNoufSXnAta58eGrXjF0ZkMnoJsWQ8OgcU0GgJyd1eBFDZ6ySZ5c6 +WgBxhZoW5E6GQbX7wS+7L0dVW00Wtr0qGY1naqxuHoTUSHPPznyk+sfKzovzRs6DPPJ 8yCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MQ9ppO9M; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:03 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 03/10] target/arm: Don't mishandle count when enabling or disabling PMU counters Date: Mon, 22 Aug 2022 14:23:51 +0100 Message-Id: <20220822132358.3524971-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The PMU cycle and event counter infrastructure design requires that operations on the PMU register fields are wrapped in pmu_op_start() and pmu_op_finish() calls (or their more specific pmmcntr and pmevcntr equivalents). This includes any changes to registers which affect whether the counter should be enabled or disabled, but we forgot to do this. The effect of this bug is that in sequences like: * disable the cycle counter (PMCCNTR) using the PMCNTEN register * write a value such as 0xfffff000 to the PMCCNTR * restart the counter by writing to PMCNTEN the value written to the cycle counter is corrupted, and it starts counting from the wrong place. (Essentially, we fail to record that the QEMU_CLOCK_VIRTUAL timestamp when the counter should be considered to have started counting is the point when PMCNTEN is written to enable the counter.) Add the necessary bracketing calls, so that updates to the various registers which affect whether the PMU is counting are handled correctly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: fixed comment typo --- target/arm/helper.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 87c89748954..59e1280a9cd 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1079,6 +1079,14 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env, return pmreg_access(env, ri, isread); } +/* + * Bits in MDCR_EL2 and MDCR_EL3 which pmu_counter_enabled() looks at. + * We use these to decide whether we need to wrap a write to MDCR_EL2 + * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls. + */ +#define MDCR_EL2_PMU_ENABLE_BITS (MDCR_HPME | MDCR_HPMD | MDCR_HPMN) +#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME) + /* Returns true if the counter (pass 31 for PMCCNTR) should count events using * the current EL, security state, and register configuration. */ @@ -1432,15 +1440,19 @@ static uint64_t pmccfiltr_read_a32(CPUARMState *env, const ARMCPRegInfo *ri) static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + pmu_op_start(env); value &= pmu_counter_mask(env); env->cp15.c9_pmcnten |= value; + pmu_op_finish(env); } static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + pmu_op_start(env); value &= pmu_counter_mask(env); env->cp15.c9_pmcnten &= ~value; + pmu_op_finish(env); } static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -4681,7 +4693,39 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri, static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + /* + * Some MDCR_EL3 bits affect whether PMU counters are running: + * if we are trying to change any of those then we must + * bracket this update with PMU start/finish calls. + */ + bool pmu_op = (env->cp15.mdcr_el3 ^ value) & MDCR_EL3_PMU_ENABLE_BITS; + + if (pmu_op) { + pmu_op_start(env); + } env->cp15.mdcr_el3 = value & SDCR_VALID_MASK; + if (pmu_op) { + pmu_op_finish(env); + } +} + +static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Some MDCR_EL2 bits affect whether PMU counters are running: + * if we are trying to change any of those then we must + * bracket this update with PMU start/finish calls. + */ + bool pmu_op = (env->cp15.mdcr_el2 ^ value) & MDCR_EL2_PMU_ENABLE_BITS; + + if (pmu_op) { + pmu_op_start(env); + } + env->cp15.mdcr_el2 = value; + if (pmu_op) { + pmu_op_finish(env); + } } static const ARMCPRegInfo v8_cp_reginfo[] = { @@ -7669,6 +7713,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo mdcr_el2 = { .name = "MDCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 1, + .writefn = mdcr_el2_write, .access = PL2_RW, .resetvalue = pmu_num_counters(env), .fieldoffset = offsetof(CPUARMState, cp15.mdcr_el2), }; From patchwork Mon Aug 22 13:23:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 599111 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp1659417mae; Mon, 22 Aug 2022 06:33:37 -0700 (PDT) X-Google-Smtp-Source: AA6agR52gL5pzJ68g+GWokh45RjQsLcUxfAhMYmj/wsf3vUYnMPQNrPRahXqAHDv0+SJodkmeqty X-Received: by 2002:a05:620a:4104:b0:6bb:61ce:73a3 with SMTP id j4-20020a05620a410400b006bb61ce73a3mr12289962qko.250.1661175217669; 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[209.51.188.17]) by mx.google.com with ESMTPS id f2-20020a05620a408200b006b94668cedcsi5437265qko.630.2022.08.22.06.33.37 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 22 Aug 2022 06:33:37 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SZEbkUyO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1]:39192 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1oQ7Yf-0000cN-9N for patch@linaro.org; Mon, 22 Aug 2022 09:33:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58702) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1oQ7PU-0005yb-NW for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:08 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:43648) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1oQ7PS-0001eY-51 for qemu-devel@nongnu.org; Mon, 22 Aug 2022 09:24:08 -0400 Received: by mail-wr1-x435.google.com with SMTP id n4so13189693wrp.10 for ; Mon, 22 Aug 2022 06:24:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=aFjhTAogUKZHPlT633nMjBBSLixPxUKktQV7BA0xzwY=; b=SZEbkUyO8ke8oO6QGqEB8mbtGeHhXYHlX1SlPwJZYpKl20hS48Wd7D/+bnMdP/wyq/ ro52b0f0Nz+G/UdiUYK/29aM6ZDzcCOeyKSJhQ4hKo4bvSxI/rbJvxAGGJWl3MFA7qvA +8YJWUW5mSGRUyZom9VcUsBr+mvz9IWKIB+Cq274ysjRQIbQE+N7jPxLIUHU+SFPI23y pwm7n3x8XR4/LJo3ikPlEZ/tkZelw3OQz2q2g4FXdXzgTaMUu59d8wiSBcJXMMOgwXW6 k6mcOdyFmWXb+Dy8rw0ng8uLEE2l3S5NMO0DnBYaVTepAKxaD1oiPpyRY+Hpu1ZY/f1r FxAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=aFjhTAogUKZHPlT633nMjBBSLixPxUKktQV7BA0xzwY=; b=CvzOXq01LTEYpiFCx68r18AM8nkM0MTlrIhW8ASSqyeqNQVOEOYutbNWnnvev1rnBg 7c6vgYml+fkbvVr3Kl1JD5ysEbcdXvVpKzI65epy1+7Hwivr8BqULDGU6b0s0EgHyhiT nbqEOktwD6f/mdmPMAgHpJ/5K0dXERBmA57/Q4Em9QfBNuzMk68jDhHNHfkq0L7x/HTG o4ubV1QoLqXRcnmcL57Awek+mkhqXtagS6KOy7dJl08kCJ9ck8yWsM/vPoDrnX+EXKHj bGzigRYtMVZdBxac1d1CEmBu8m1P6dh5hKErHeqe+kuvqrUMIfXqxEI3O53NMFEXm8Vd jneg== X-Gm-Message-State: ACgBeo360N2R91v5fOUuoY+p/dPmdBZMLL9Uz3lljbvtCq1v21X1PcWn fT4hChFHiAYw5Oclg02w8ezKFg== X-Received: by 2002:a5d:59ad:0:b0:225:5b64:8c6a with SMTP id p13-20020a5d59ad000000b002255b648c6amr2091290wrr.558.1661174644731; Mon, 22 Aug 2022 06:24:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:04 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 04/10] target/arm: Ignore PMCR.D when PMCR.LC is set Date: Mon, 22 Aug 2022 14:23:52 +0100 Message-Id: <20220822132358.3524971-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The architecture requires that if PMCR.LC is set (for a 64-bit cycle counter) then PMCR.D (which enables the clock divider so the counter ticks every 64 cycles rather than every cycle) should be ignored. We were always honouring PMCR.D; fix the bug so we correctly ignore it in this situation. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 17 +++++++++++++---- 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 59e1280a9cd..f2bf1c52eb2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1172,6 +1172,17 @@ static void pmu_update_irq(CPUARMState *env) (env->cp15.c9_pminten & env->cp15.c9_pmovsr)); } +static bool pmccntr_clockdiv_enabled(CPUARMState *env) +{ + /* + * Return true if the clock divider is enabled and the cycle counter + * is supposed to tick only once every 64 clock cycles. This is + * controlled by PMCR.D, but if PMCR.LC is set to enable the long + * (64-bit) cycle counter PMCR.D has no effect. + */ + return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD; +} + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1184,8 +1195,7 @@ static void pmccntr_op_start(CPUARMState *env) if (pmu_counter_enabled(env, 31)) { uint64_t eff_cycles = cycles; - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ + if (pmccntr_clockdiv_enabled(env)) { eff_cycles /= 64; } @@ -1228,8 +1238,7 @@ static void pmccntr_op_finish(CPUARMState *env) #endif uint64_t prev_cycles = env->cp15.c15_ccnt_delta; - if (env->cp15.c9_pmcr & PMCRD) { - /* Increment once every 64 processor clock cycles */ + if (pmccntr_clockdiv_enabled(env)) { prev_cycles /= 64; } env->cp15.c15_ccnt_delta = prev_cycles - env->cp15.c15_ccnt; From patchwork Mon Aug 22 13:23:53 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 599107 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp1654023mae; Mon, 22 Aug 2022 06:27:04 -0700 (PDT) X-Google-Smtp-Source: AA6agR6t03YrxZXEaAZonyJSzNf71mJiSPbX3LR0rSc2Kpcdfpuxm1eR2FgcCyw8GUlJJau/c/Kz X-Received: by 2002:a05:6214:1d0f:b0:496:b99f:3b3c with SMTP id e15-20020a0562141d0f00b00496b99f3b3cmr15401975qvd.113.1661174824006; Mon, 22 Aug 2022 06:27:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661174824; cv=none; d=google.com; s=arc-20160816; b=BzOIfRRnhQPBFugvs7KrXaVTxndUszdyOdu/FdX5zZnNlkhnnnXnbQOY2LtKLEj3/I vboV8LIkT6UHW3nQGTObMlenaToAfoSKAr9+s7zXazdELtOU3UtHtkTD7m4wUCuzbH4T MM05WGr0HWfwl6NuxyiqouuzVoseDE7NqVy5KBtPo4EJ4tk8b+PJYGTqI5U1OzsbGSaI 9lCRgMQyJ8l0VXw8/HB3XYX4C/5TfxZMXbUTwy+Ml7UlUNWo9+xCJFC6Ch7qWGnN6wzy APGiU51iG4Zl3B6uaDW+Vf9drKW9jwy7qQkTn5e4aFK54TvSCeq/PrxTz5bn+2qgLR+B 9Z6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6yc2QQJRiauV/rnVG5qIFbv8E5zW00rmH8bNkLiSwRQ=; b=XvUJo2yT7aJ+Er1t2gg5DA0x8jh5H9JGOj9Jx7JToB4To4eCFvezc+gs44tnf8fcbe LwxiqInrJ0dxL1d8a7lBzZsbR975AvcoZQrx9E1NzKCviqKzRs6lktZZQASXgh4YZiWr URDfa+ixpZ17KquoBxLyueGHMzD8GcIbEE++sowgyq3RLTGIjieSxU3eqbqwVOdBFn4K c+q79OGh5GvvgJtrnWzElXWSexgNgR4Bfnkb+KztZyyUOD3tEe54p/NS/UKADkji4cum p8A+L//xgJY0sBUksAtqMU5J9eBb0ssdltC/q03kU+W1pDC6CPMn0/mFA1lJp9WrmUuv jzEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="MxIIKoA/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:05 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 05/10] target/arm: Honour MDCR_EL2.HPMD in Secure EL2 Date: Mon, 22 Aug 2022 14:23:53 +0100 Message-Id: <20220822132358.3524971-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The logic in pmu_counter_enabled() for handling the 'prohibit event counting' bits MDCR_EL2.HPMD and MDCR_EL3.SPME is written in a way that assumes that EL2 is never Secure. This used to be true, but the architecture now permits Secure EL2, and QEMU can emulate this. Refactor the prohibit logic so that we effectively OR together the various prohibit bits when they apply, rather than trying to construct an if-else ladder where any particular state of the CPU ends up in exactly one branch of the ladder. This fixes the Secure EL2 case and also is a better structure for adding the PMUv8.5 bits MDCR_EL2.HCCD and MDCR_EL3.SCCD. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I opted not to use bitwise |= for boolean operations. --- target/arm/helper.c | 17 +++++++---------- 1 file changed, 7 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f2bf1c52eb2..7d4127a1573 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1094,7 +1094,7 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) { uint64_t filter; bool e, p, u, nsk, nsu, nsh, m; - bool enabled, prohibited, filtered; + bool enabled, prohibited = false, filtered; bool secure = arm_is_secure(env); int el = arm_current_el(env); uint64_t mdcr_el2 = arm_mdcr_el2_eff(env); @@ -1112,15 +1112,12 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) } enabled = e && (env->cp15.c9_pmcnten & (1 << counter)); - if (!secure) { - if (el == 2 && (counter < hpmn || counter == 31)) { - prohibited = mdcr_el2 & MDCR_HPMD; - } else { - prohibited = false; - } - } else { - prohibited = arm_feature(env, ARM_FEATURE_EL3) && - !(env->cp15.mdcr_el3 & MDCR_SPME); + /* Is event counting prohibited? */ + if (el == 2 && (counter < hpmn || counter == 31)) { + prohibited = mdcr_el2 & MDCR_HPMD; + } + if (secure) { + prohibited = prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); } if (prohibited && counter == 31) { From patchwork Mon Aug 22 13:23:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 599109 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp1655810mae; Mon, 22 Aug 2022 06:29:30 -0700 (PDT) X-Google-Smtp-Source: AA6agR6eHr4ok9BwwlQdk+tIwisTobnq7iv7ZmZd4TLZocoQPjmXqILVG+HaLGzmGtHyxUDim0w8 X-Received: by 2002:a05:6214:2a81:b0:473:af82:9a95 with SMTP id jr1-20020a0562142a8100b00473af829a95mr15717516qvb.44.1661174970789; Mon, 22 Aug 2022 06:29:30 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661174970; cv=none; d=google.com; s=arc-20160816; b=W8BximQ1etricWWCHRdPe37ZjGmxB8iC+3lOJmAOV7M+aFRCAkKMWyXIC6EAYpbAxX /mn1pal2Tx5kQmBTKkw5t9hcJGl8xvpGtCEDZh+3PYa16PtuPuI2juoNTOuRGtfShJlf xB451FIAOYw5ETM6IanDUE1LiKVCBAHwMt7BxrDEwJN+YMKy7koAvKCt3Na09nyso9ac caiTwAYGAaWCpA9l9WEp3MxKsl39eopDlc808i5aLfMD+Ir1cx7hglZXOqeGb2F4dVhd bY4rekmUng0tvT4RhDzo+vGbaxZ1nOmqTyeDvJChZa7SN+Hmkv2ms+qd+sOFkC4IAwaK xwAg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gAJToUGMZxgV0d4Q4X3oKY4UbjuKkCvUr3anhNbi7Gw=; b=Z43WR9iUevs0VcjmDtLS8MLT0bmEzc9JLvflKwghy7zYsEgBTGC4aTNIa00G8/+bSc O7+CDB4zksO2HFrqVsIIsKRnGmeWE7FEGj0oPj3sByRp/GFYiQq01dmbg8+k4o8EgG2j LIY6A7bFjaARGIK7OuhzP+HpEi+JytpYwNN+cm3R9aLowbBcSft/7niQQHvt/HbtEVRj 4fzFnzQoPvkYQsCBH0Pc3QHPndvhyy5aAfg1Uphp7f1sl4sRo9B3qSgrLVLKZQSr0yhb J1jmnr8jT661UJUwAX5/nDOC6V/QgzFpTUfedWtHJHzZq+Lofj61tnrZO/JKWJIdylJw Nt9g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mp+4Cvc2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:06 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 06/10] target/arm: Detect overflow when calculating next PMU interrupt Date: Mon, 22 Aug 2022 14:23:54 +0100 Message-Id: <20220822132358.3524971-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" In pmccntr_op_finish() and pmevcntr_op_finish() we calculate the next point at which we will get an overflow and need to fire the PMU interrupt or set the overflow flag. We do this by calculating the number of nanoseconds to the overflow event and then adding it to qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL). However, we don't check whether that signed addition overflows, which can happen if the next PMU interrupt would happen massively far in the future (250 years or more). Since QEMU assumes that "when the QEMU_CLOCK_VIRTUAL rolls over" is "never", the sensible behaviour in this situation is simply to not try to set the timer if it would be beyond that point. Detect the overflow, and skip setting the timer in that case. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: fixed bogus indentation --- target/arm/helper.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d4127a1573..94307a6c417 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1227,10 +1227,13 @@ static void pmccntr_op_finish(CPUARMState *env) int64_t overflow_in = cycles_ns_per(remaining_cycles); if (overflow_in > 0) { - int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - overflow_in; - ARMCPU *cpu = env_archcpu(env); - timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + int64_t overflow_at; + + if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + overflow_in, &overflow_at)) { + ARMCPU *cpu = env_archcpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } } #endif @@ -1275,10 +1278,13 @@ static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) int64_t overflow_in = pm_events[event_idx].ns_per_count(delta); if (overflow_in > 0) { - int64_t overflow_at = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + - overflow_in; - ARMCPU *cpu = env_archcpu(env); - timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + int64_t overflow_at; + + if (!sadd64_overflow(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + overflow_in, &overflow_at)) { + ARMCPU *cpu = env_archcpu(env); + timer_mod_anticipate_ns(cpu->pmu_timer, overflow_at); + } } #endif From patchwork Mon Aug 22 13:23:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 599113 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp1704512mae; Mon, 22 Aug 2022 07:27:55 -0700 (PDT) X-Google-Smtp-Source: AA6agR6b4hE526/QQLp43AKHX1/0a1mo9MB1ay/c8oWHe2QV73IK2S/blqt4jx8BaAnEDmidLgM2 X-Received: by 2002:a05:6214:4005:b0:472:be5a:810d with SMTP id kd5-20020a056214400500b00472be5a810dmr15949764qvb.36.1661178475525; Mon, 22 Aug 2022 07:27:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661178475; cv=none; d=google.com; s=arc-20160816; b=yGd1EM2vzoIsVMwww5sK7ErCbAAmx7cYIlhz/AlIDAa5kWSpMAbhlv2cGt8Ei2MQFN zhQEhMMNhGvKym+qDZ2F3/h1OH5kdo7ksqbML2zkSVbyTlpLQt5XkAwTqTYVrg6LRSQY wUGW1UjwtNTWNG+zW5rXZJF7VGpLk0wKukq/HIQ62MZmQ5Q9Luz3kRqVVl/Qrh6Qq5d1 wv77wP5njeY8ZaIkkTdI1o1MdVa8B+SyULzBiVnp4nqXHlrpNXdlQuTZQYZrJFU/IQ+t CWGbsE32t1TH7fRQpiTYordggEAVV+tNDx3c0GUA+gE3HFf7AqR62tpIpS4vpPwyBKgM J6Xg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2fxzttXpNNgLe45+/J1iHDaTona/8trrZi4UUTNeBEw=; b=jrY5Ah/KnXHO9uQI3r0xo/T1dlTSuhTYV4WvV1s5bGK5Z9IrKTVfq7hGp81BhZkvk8 rG0rDO+fbiSxU6SIkKdY+Y0ZtDEW3p0O7DV/KS345N1UqjEADdlQ0LDoeBEXy1Hpv8Zy q5HH/OjdXQj2zEKh8Ja03eyhxbhlogsmZRkrJJF+0q/aJ9u6mZJa/WtZPEfsanEsTAFe JYBGpnvzZXRjuKNK96HCGb5TsVo/zPXkxoFYSvMe/W4d/tdXYgAfRtOWWxGFvpsjuKIJ dm3XysLPDCDArCbYY2vLXIuE2SmAHNPD4gEpPFC6tZim9NF9iCbqnXx91evMlpehXHZd 9XDg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="ymXq/t4+"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:07 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 07/10] target/arm: Rename pmu_8_n feature test functions Date: Mon, 22 Aug 2022 14:23:55 +0100 Message-Id: <20220822132358.3524971-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Our feature test functions that check the PMU version are named isar_feature_{aa32,aa64,any}_pmu_8_{1,4}. This doesn't match the current Arm ARM official feature names, which are FEAT_PMUv3p1 and FEAT_PMUv3p4. Rename these functions to _pmuv3p1 and _pmuv3p4. This commit was created with: sed -i -e 's/pmu_8_/pmuv3p/g' target/arm/*.[ch] Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 16 ++++++++-------- target/arm/helper.c | 18 +++++++++--------- 2 files changed, 17 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 5168e3d837e..122ec8a47ec 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3710,14 +3710,14 @@ static inline bool isar_feature_aa32_ats1e1(const ARMISARegisters *id) return FIELD_EX32(id->id_mmfr3, ID_MMFR3, PAN) >= 2; } -static inline bool isar_feature_aa32_pmu_8_1(const ARMISARegisters *id) +static inline bool isar_feature_aa32_pmuv3p1(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 4 && FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; } -static inline bool isar_feature_aa32_pmu_8_4(const ARMISARegisters *id) +static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) { /* 0xf means "non-standard IMPDEF PMU" */ return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 5 && @@ -4036,13 +4036,13 @@ static inline bool isar_feature_aa64_sme(const ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SME) != 0; } -static inline bool isar_feature_aa64_pmu_8_1(const ARMISARegisters *id) +static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 4 && FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } -static inline bool isar_feature_aa64_pmu_8_4(const ARMISARegisters *id) +static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 5 && FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; @@ -4211,14 +4211,14 @@ static inline bool isar_feature_any_predinv(const ARMISARegisters *id) return isar_feature_aa64_predinv(id) || isar_feature_aa32_predinv(id); } -static inline bool isar_feature_any_pmu_8_1(const ARMISARegisters *id) +static inline bool isar_feature_any_pmuv3p1(const ARMISARegisters *id) { - return isar_feature_aa64_pmu_8_1(id) || isar_feature_aa32_pmu_8_1(id); + return isar_feature_aa64_pmuv3p1(id) || isar_feature_aa32_pmuv3p1(id); } -static inline bool isar_feature_any_pmu_8_4(const ARMISARegisters *id) +static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) { - return isar_feature_aa64_pmu_8_4(id) || isar_feature_aa32_pmu_8_4(id); + return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); } static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) diff --git a/target/arm/helper.c b/target/arm/helper.c index 94307a6c417..5212750b378 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -879,16 +879,16 @@ static int64_t instructions_ns_per(uint64_t icount) } #endif -static bool pmu_8_1_events_supported(CPUARMState *env) +static bool pmuv3p1_events_supported(CPUARMState *env) { /* For events which are supported in any v8.1 PMU */ - return cpu_isar_feature(any_pmu_8_1, env_archcpu(env)); + return cpu_isar_feature(any_pmuv3p1, env_archcpu(env)); } -static bool pmu_8_4_events_supported(CPUARMState *env) +static bool pmuv3p4_events_supported(CPUARMState *env) { /* For events which are supported in any v8.1 PMU */ - return cpu_isar_feature(any_pmu_8_4, env_archcpu(env)); + return cpu_isar_feature(any_pmuv3p4, env_archcpu(env)); } static uint64_t zero_event_get_count(CPUARMState *env) @@ -922,17 +922,17 @@ static const pm_event pm_events[] = { }, #endif { .number = 0x023, /* STALL_FRONTEND */ - .supported = pmu_8_1_events_supported, + .supported = pmuv3p1_events_supported, .get_count = zero_event_get_count, .ns_per_count = zero_event_ns_per, }, { .number = 0x024, /* STALL_BACKEND */ - .supported = pmu_8_1_events_supported, + .supported = pmuv3p1_events_supported, .get_count = zero_event_get_count, .ns_per_count = zero_event_ns_per, }, { .number = 0x03c, /* STALL */ - .supported = pmu_8_4_events_supported, + .supported = pmuv3p4_events_supported, .get_count = zero_event_get_count, .ns_per_count = zero_event_ns_per, }, @@ -6400,7 +6400,7 @@ static void define_pmu_regs(ARMCPU *cpu) g_free(pmevtyper_name); g_free(pmevtyper_el0_name); } - if (cpu_isar_feature(aa32_pmu_8_1, cpu)) { + if (cpu_isar_feature(aa32_pmuv3p1, cpu)) { ARMCPRegInfo v81_pmu_regs[] = { { .name = "PMCEID2", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 4, @@ -6413,7 +6413,7 @@ static void define_pmu_regs(ARMCPU *cpu) }; define_arm_cp_regs(cpu, v81_pmu_regs); } - if (cpu_isar_feature(any_pmu_8_4, cpu)) { + if (cpu_isar_feature(any_pmuv3p4, cpu)) { static const ARMCPRegInfo v84_pmmir = { .name = "PMMIR_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 6, From patchwork Mon Aug 22 13:23:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 599110 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp1657039mae; Mon, 22 Aug 2022 06:31:00 -0700 (PDT) X-Google-Smtp-Source: AA6agR5eYE7aeUKIP6pQb8qf4o1CMPod96dlVyCgQnkXXGsDLbnkPDMsr6DAlBAlOS7dhc/74i2s X-Received: by 2002:a05:622a:1906:b0:343:55d3:54ec with SMTP id w6-20020a05622a190600b0034355d354ecmr15468297qtc.168.1661175060475; Mon, 22 Aug 2022 06:31:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661175060; cv=none; d=google.com; s=arc-20160816; b=TMJlQexs/cSgPOjPSWtpy+7n4jJCYpQNa0epgb8S3hWu3aZiVSl1LXT7KVngm5MpRN MUPTnKIznpDczd25UUIp4EHmip99nunfpG8ETQG2HG5++dIc0H7qTzHp6CRHDmMstTBA 4RRotcn/ZbZDOaRGvpmitlHjUZzK3ApesLV1KY6Zk+nwZSVaBEtSoiZd+9DQMslFZDzq e8Dq1NF7m9i1LVYeU2dndOlObdom97/Hz+i2dYIVXkJvnCr/tciMes1gFYKTOdKyP5yY qeLgkDsMu38ue0OHyiwYvE5IizNrtn5wqPamsEa70IEjopYjW1DyVv55chW+hbBe7T7k YrkA== ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:08 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 08/10] target/arm: Implement FEAT_PMUv3p5 cycle counter disable bits Date: Mon, 22 Aug 2022 14:23:56 +0100 Message-Id: <20220822132358.3524971-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" FEAT_PMUv3p5 introduces new bits which disable the cycle counter from counting: * MDCR_EL2.HCCD disables the counter when in EL2 * MDCR_EL3.SCCD disables the counter when Secure Add the code to support these bits. (Note that there is a third documented counter-disable bit, MDCR_EL3.MCCD, which disables the counter when in EL3. This is not present until FEAT_PMUv3p7, so is out of scope for now.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: Get the MDCR_EL3 bit right; v1 implemented something more like MDCR_EL3.MCCD. --- target/arm/cpu.h | 20 ++++++++++++++++++++ target/arm/helper.c | 21 +++++++++++++++++---- 2 files changed, 37 insertions(+), 4 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 122ec8a47ec..1f6ccc6f217 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1332,6 +1332,8 @@ FIELD(CPTR_EL3, TTA, 20, 1) FIELD(CPTR_EL3, TAM, 30, 1) FIELD(CPTR_EL3, TCPAC, 31, 1) +#define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ +#define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) #define MDCR_SPME (1U << 17) /* MDCR_EL3 */ @@ -3724,6 +3726,13 @@ static inline bool isar_feature_aa32_pmuv3p4(const ARMISARegisters *id) FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; } +static inline bool isar_feature_aa32_pmuv3p5(const ARMISARegisters *id) +{ + /* 0xf means "non-standard IMPDEF PMU" */ + return FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) >= 6 && + FIELD_EX32(id->id_dfr0, ID_DFR0, PERFMON) != 0xf; +} + static inline bool isar_feature_aa32_hpd(const ARMISARegisters *id) { return FIELD_EX32(id->id_mmfr4, ID_MMFR4, HPDS) != 0; @@ -4048,6 +4057,12 @@ static inline bool isar_feature_aa64_pmuv3p4(const ARMISARegisters *id) FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; } +static inline bool isar_feature_aa64_pmuv3p5(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) >= 6 && + FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, PMUVER) != 0xf; +} + static inline bool isar_feature_aa64_rcpc_8_3(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, LRCPC) != 0; @@ -4221,6 +4236,11 @@ static inline bool isar_feature_any_pmuv3p4(const ARMISARegisters *id) return isar_feature_aa64_pmuv3p4(id) || isar_feature_aa32_pmuv3p4(id); } +static inline bool isar_feature_any_pmuv3p5(const ARMISARegisters *id) +{ + return isar_feature_aa64_pmuv3p5(id) || isar_feature_aa32_pmuv3p5(id); +} + static inline bool isar_feature_any_ccidx(const ARMISARegisters *id) { return isar_feature_aa64_ccidx(id) || isar_feature_aa32_ccidx(id); diff --git a/target/arm/helper.c b/target/arm/helper.c index 5212750b378..d22debcd57b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1084,8 +1084,8 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env, * We use these to decide whether we need to wrap a write to MDCR_EL2 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls. */ -#define MDCR_EL2_PMU_ENABLE_BITS (MDCR_HPME | MDCR_HPMD | MDCR_HPMN) -#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME) +#define MDCR_EL2_PMU_ENABLE_BITS (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD) +#define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD) /* Returns true if the counter (pass 31 for PMCCNTR) should count events using * the current EL, security state, and register configuration. @@ -1120,8 +1120,21 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter) prohibited = prohibited || !(env->cp15.mdcr_el3 & MDCR_SPME); } - if (prohibited && counter == 31) { - prohibited = env->cp15.c9_pmcr & PMCRDP; + if (counter == 31) { + /* + * The cycle counter defaults to running. PMCR.DP says "disable + * the cycle counter when event counting is prohibited". + * Some MDCR bits disable the cycle counter specifically. + */ + prohibited = prohibited && env->cp15.c9_pmcr & PMCRDP; + if (cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + if (secure) { + prohibited = prohibited || (env->cp15.mdcr_el3 & MDCR_SCCD); + } + if (el == 2) { + prohibited = prohibited || (mdcr_el2 & MDCR_HCCD); + } + } } if (counter == 31) { From patchwork Mon Aug 22 13:23:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 599112 Delivered-To: patch@linaro.org Received: by 2002:a05:7000:4388:0:0:0:0 with SMTP id w8csp1661801mae; Mon, 22 Aug 2022 06:36:39 -0700 (PDT) X-Google-Smtp-Source: AA6agR5Jy76YogHonn+1u3dC5QXMI3h+pDkVW5BGaQasIlsWUiVB02ac4RWmfrVaQVyVNthqSagd X-Received: by 2002:a05:620a:1193:b0:6bb:b867:c095 with SMTP id b19-20020a05620a119300b006bbb867c095mr12284215qkk.227.1661175399685; Mon, 22 Aug 2022 06:36:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661175399; cv=none; d=google.com; s=arc-20160816; b=KqZVB9ht9l1vbQc9BrZnpRcI5IUIU7pRY7UZiJPyv2AApJTWxau558uFAeoV3qq68+ /3UhoFNfdUBWdrM5k54qCG/0NqhZtlyAsJKUYFi78ZjfzOd8OC8SohhaHxNhlGtU6PMG F6sYDsYluzOoevD5GX0AHYAsC3Vgzziy01bW3djps39abC7/OXpxFJb1SwROTq5XPVDZ odfcgGN82/GUCbrQBA8OaOcainJjUnuywKD546KT83EH3OjP2BmSBDrVIuvkfhg7HYi8 4XsgcaCRu+Tlw3d0rlvfNGtwC7Qe6ai3Ag1FAp6dVjcG+x7bj61Js8ArBar6/hvsLS4j fVAw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vD+of0yf04XIK3wSlDEJY0alv64T6b7yHWK7FZo8BaI=; b=Ojm6rq63iRjSrL7zEwyoLA4IF4DHWIA2rDz7E9vX2UiZ4M8lrBQMcZsA3pfyQaqKyw +9Kfy047U4qrPI58odlxBvrEg1giJrKlJ7uGSVaaLdwvfeWSgMDtjkMw+yX/mi1uNsUe fBfdwL5t5+1oElT8QvojIkvsoxn00nEzLI4BwS8+f2H/ZAXg/yO4Q2IHETmrhTzoUmNq ryLbSvL3m8vXHysfZ/p2/7IBwlI4Z7VYwSK6U0lBSm3s/AedYWUSwah/fTPrSv39lyJ9 i1RaDMdq4sMkfzYSC+ma+wTxw8XAWnQgpnusluCQ+aO0ZssQ07EvLk8RmJLNhlgL7HSS CuuQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tfLW+4yB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:09 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 09/10] target/arm: Support 64-bit event counters for FEAT_PMUv3p5 Date: Mon, 22 Aug 2022 14:23:57 +0100 Message-Id: <20220822132358.3524971-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" With FEAT_PMUv3p5, the event counters are now 64 bit, rather than 32 bit. (Previously, only the cycle counter could be 64 bit, and other event counters were always 32 bits). For any given event counter, whether the overflow event is noted for overflow from bit 31 or from bit 63 is controlled by a combination of PMCR.LP, MDCR_EL2.HLP and MDCR_EL2.HPMN. Implement the 64-bit event counter handling. We choose to make our counters always 64 bits, and mask out the top 32 bits on read or write of PMXEVCNTR for CPUs which don't have FEAT_PMUv3p5. (Note that the changes to pmenvcntr_op_start() and pmenvcntr_op_finish() bring their logic closer into line with that of pmccntr_op_start() and pmccntr_op_finish(), which already had to cope with the overflow being either at 32 or 64 bits.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 1 + target/arm/internals.h | 3 +- target/arm/helper.c | 62 ++++++++++++++++++++++++++++++++++++------ 3 files changed, 57 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1f6ccc6f217..be79394dcc7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1332,6 +1332,7 @@ FIELD(CPTR_EL3, TTA, 20, 1) FIELD(CPTR_EL3, TAM, 30, 1) FIELD(CPTR_EL3, TCPAC, 31, 1) +#define MDCR_HLP (1U << 26) /* MDCR_EL2 */ #define MDCR_SCCD (1U << 23) /* MDCR_EL3 */ #define MDCR_HCCD (1U << 23) /* MDCR_EL2 */ #define MDCR_EPMAD (1U << 21) diff --git a/target/arm/internals.h b/target/arm/internals.h index 83526166de0..bf60cd5f845 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1256,6 +1256,7 @@ enum MVEECIState { /* Definitions for the PMU registers */ #define PMCRN_MASK 0xf800 #define PMCRN_SHIFT 11 +#define PMCRLP 0x80 #define PMCRLC 0x40 #define PMCRDP 0x20 #define PMCRX 0x10 @@ -1267,7 +1268,7 @@ enum MVEECIState { * Mask of PMCR bits writable by guest (not including WO bits like C, P, * which can be written as 1 to trigger behaviour but which stay RAZ). */ -#define PMCR_WRITABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) +#define PMCR_WRITABLE_MASK (PMCRLP | PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE) #define PMXEVTYPER_P 0x80000000 #define PMXEVTYPER_U 0x40000000 diff --git a/target/arm/helper.c b/target/arm/helper.c index d22debcd57b..133ca39700f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1084,7 +1084,8 @@ static CPAccessResult pmreg_access_ccntr(CPUARMState *env, * We use these to decide whether we need to wrap a write to MDCR_EL2 * or MDCR_EL3 in pmu_op_start()/pmu_op_finish() calls. */ -#define MDCR_EL2_PMU_ENABLE_BITS (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD) +#define MDCR_EL2_PMU_ENABLE_BITS \ + (MDCR_HPME | MDCR_HPMD | MDCR_HPMN | MDCR_HCCD | MDCR_HLP) #define MDCR_EL3_PMU_ENABLE_BITS (MDCR_SPME | MDCR_SCCD) /* Returns true if the counter (pass 31 for PMCCNTR) should count events using @@ -1193,6 +1194,32 @@ static bool pmccntr_clockdiv_enabled(CPUARMState *env) return (env->cp15.c9_pmcr & (PMCRD | PMCRLC)) == PMCRD; } +static bool pmevcntr_is_64_bit(CPUARMState *env, int counter) +{ + /* Return true if the specified event counter is configured to be 64 bit */ + + /* This isn't intended to be used with the cycle counter */ + assert(counter < 31); + + if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + return false; + } + + if (arm_feature(env, ARM_FEATURE_EL2)) { + /* + * MDCR_EL2.HLP still applies even when EL2 is disabled in the + * current security state, so we don't use arm_mdcr_el2_eff() here. + */ + bool hlp = env->cp15.mdcr_el2 & MDCR_HLP; + int hpmn = env->cp15.mdcr_el2 & MDCR_HPMN; + + if (hpmn != 0 && counter >= hpmn) { + return hlp; + } + } + return env->cp15.c9_pmcr & PMCRLP; +} + /* * Ensure c15_ccnt is the guest-visible count so that operations such as * enabling/disabling the counter or filtering, modifying the count itself, @@ -1269,9 +1296,11 @@ static void pmevcntr_op_start(CPUARMState *env, uint8_t counter) } if (pmu_counter_enabled(env, counter)) { - uint32_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; + uint64_t new_pmevcntr = count - env->cp15.c14_pmevcntr_delta[counter]; + uint64_t overflow_mask = pmevcntr_is_64_bit(env, counter) ? + 1ULL << 63 : 1ULL << 31; - if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & INT32_MIN) { + if (env->cp15.c14_pmevcntr[counter] & ~new_pmevcntr & overflow_mask) { env->cp15.c9_pmovsr |= (1 << counter); pmu_update_irq(env); } @@ -1286,9 +1315,13 @@ static void pmevcntr_op_finish(CPUARMState *env, uint8_t counter) #ifndef CONFIG_USER_ONLY uint16_t event = env->cp15.c14_pmevtyper[counter] & PMXEVTYPER_EVTCOUNT; uint16_t event_idx = supported_event_map[event]; - uint64_t delta = UINT32_MAX - - (uint32_t)env->cp15.c14_pmevcntr[counter] + 1; - int64_t overflow_in = pm_events[event_idx].ns_per_count(delta); + uint64_t delta = -(env->cp15.c14_pmevcntr[counter] + 1); + int64_t overflow_in; + + if (!pmevcntr_is_64_bit(env, counter)) { + delta = (uint32_t)delta; + } + overflow_in = pm_events[event_idx].ns_per_count(delta); if (overflow_in > 0) { int64_t overflow_at; @@ -1375,6 +1408,8 @@ static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { unsigned int i; + uint64_t overflow_mask, new_pmswinc; + for (i = 0; i < pmu_num_counters(env); i++) { /* Increment a counter's count iff: */ if ((value & (1 << i)) && /* counter's bit is set */ @@ -1388,9 +1423,12 @@ static void pmswinc_write(CPUARMState *env, const ARMCPRegInfo *ri, * Detect if this write causes an overflow since we can't predict * PMSWINC overflows like we can for other events */ - uint32_t new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; + new_pmswinc = env->cp15.c14_pmevcntr[i] + 1; - if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & INT32_MIN) { + overflow_mask = pmevcntr_is_64_bit(env, i) ? + 1ULL << 63 : 1ULL << 31; + + if (env->cp15.c14_pmevcntr[i] & ~new_pmswinc & overflow_mask) { env->cp15.c9_pmovsr |= (1 << i); pmu_update_irq(env); } @@ -1597,6 +1635,10 @@ static uint64_t pmxevtyper_read(CPUARMState *env, const ARMCPRegInfo *ri) static void pmevcntr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value, uint8_t counter) { + if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ + value &= MAKE_64BIT_MASK(0, 32); + } if (counter < pmu_num_counters(env)) { pmevcntr_op_start(env, counter); env->cp15.c14_pmevcntr[counter] = value; @@ -1616,6 +1658,10 @@ static uint64_t pmevcntr_read(CPUARMState *env, const ARMCPRegInfo *ri, pmevcntr_op_start(env, counter); ret = env->cp15.c14_pmevcntr[counter]; pmevcntr_op_finish(env, counter); + if (!cpu_isar_feature(any_pmuv3p5, env_archcpu(env))) { + /* Before FEAT_PMUv3p5, top 32 bits of event counters are RES0 */ + ret &= MAKE_64BIT_MASK(0, 32); + } return ret; } else { /* We opt to behave as a RAZ/WI when attempts to access PM[X]EVCNTR From patchwork Mon Aug 22 13:23:58 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 599114 Delivered-To: patch@linaro.org Received: by 2002:a05:6918:5e84:b0:d4:ea33:5523 with SMTP id nd4csp1754883ysb; Mon, 22 Aug 2022 07:42:43 -0700 (PDT) X-Google-Smtp-Source: AA6agR4TKsaJLjK/M4oB90PISdUFZ7+BXAmVfncjuqdmk7GbyjbC94qyK2k9oBmvmzJv0+luyoD1 X-Received: by 2002:a05:6214:5185:b0:472:f9b0:cbc6 with SMTP id kl5-20020a056214518500b00472f9b0cbc6mr15650950qvb.92.1661179362032; Mon, 22 Aug 2022 07:42:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1661179362; cv=none; d=google.com; s=arc-20160816; b=DtrIb5ZyIjTHHqel8T9osgLB1OBsgLALKUrU0KEsNnya5GXSqlCguNXeiD7cAJPgVD tXTwvoCVW08yXKFylLs89Ohd6BRhonOg41pVvgg6R9FHRl5Ld2+uVflCYkGfl+Bpxa5o 5HOSG6BetvmQw0Wco0WofxvI0rEvCkueU5N9Bn54QVIoEEUCuHgd9X9TvgZ7hUDZOwV/ xuXJ1ZXDZB+YXZSYuYp0QMD9CSmsG4lnVBVfpaV+M/GU0SahfWxnLukstwFmXsLyL+UM E1x5JhrQdWIvZYDfGisp+Jn87Khd5bYo9Ea1mkqIb7PBIoQOFox14/UOJ2+bg7a7B3Ge rOcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WKtyI8kjRNlnCB4JM27i0afmEKH1KHPL+DE/obbLKuA=; b=iMcP+o7fbkfwZ/ayhx7HxRPZoR9VhT4YnXZEdkyn/imYOfUw99ZLA75lYdblZjUeFA oyGIYVvuIsivK8OdzV0SvhQEitOBbOfxTmWNBlVmLoUzDEqfS83EBpFIC2AZNhixLLgB Pf8AWwFpcm+Q04wXQvXBcO81sUzEE4/rc9PEKbboXhBpv7i+Ho8qRJ5IA1tWB5pjzGHz YtetXFE8FSi0+aJpRpDyA/uh7+55ypqUuuHQ/5oMoPXfjVLWzqv0Ea7hNCjGDMePbBxa u+saiv8D8TV1yoPP4BWixJYko6lfqrKAcejbFyn71DqP+2qbCvadHYm0XcLdJBc5EXgJ 1RSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XIvLYfSW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id f12-20020adff98c000000b0021f13097d6csm11527946wrr.16.2022.08.22.06.24.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 22 Aug 2022 06:24:10 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PATCH v2 10/10] target/arm: Report FEAT_PMUv3p5 for TCG '-cpu max' Date: Mon, 22 Aug 2022 14:23:58 +0100 Message-Id: <20220822132358.3524971-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220822132358.3524971-1-peter.maydell@linaro.org> References: <20220822132358.3524971-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Update the ID registers for TCG's '-cpu max' to report a FEAT_PMUv3p5 compliant PMU. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- v1->v2: update emulation.rst too --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 8e494c8bea5..e36a60a4da6 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -52,6 +52,7 @@ the following architecture extensions: - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) +- FEAT_PMUv3p5 (PMU Extensions v3.5) - FEAT_RAS (Reliability, availability, and serviceability) - FEAT_RASv1p1 (RAS Extension v1.1) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 78e27f778ac..fa4b0152706 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -1072,7 +1072,7 @@ static void aarch64_max_initfn(Object *obj) t = cpu->isar.id_aa64dfr0; t = FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ - t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ + t = FIELD_DP64(t, ID_AA64DFR0, PMUVER, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_aa64dfr0 = t; t = cpu->isar.id_aa64smfr0; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 3099b38e32b..4c71a0b612d 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -81,7 +81,7 @@ void aa32_max_features(ARMCPU *cpu) t = cpu->isar.id_dfr0; t = FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ t = FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ - t = FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ + t = FIELD_DP32(t, ID_DFR0, PERFMON, 6); /* FEAT_PMUv3p5 */ cpu->isar.id_dfr0 = t; }