From patchwork Sun Aug 21 18:19:02 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 599567 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59898C32789 for ; Sun, 21 Aug 2022 18:18:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231665AbiHUSSv (ORCPT ); Sun, 21 Aug 2022 14:18:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60482 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231655AbiHUSSu (ORCPT ); Sun, 21 Aug 2022 14:18:50 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 29B1B15FF5; Sun, 21 Aug 2022 11:18:49 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id y15so4438886pfr.9; Sun, 21 Aug 2022 11:18:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=oSgkN+dTN7nRZb20JasKAqJ/0pKCu6M2zNDhcnKlGu0=; b=MkZHKAGKHan5H72D8tPjvl3t5B0A1ynHIQaPnJRJ5crpXL2QupZxn+K5xNrx16Jowe T8gGwT9SKtRepT3P1aZFte+0Fu4PCMbqwqf/I2pL5Oj7WdW2FWmJ1dafGEsMI46JAZed CjLfcNP1U+8SAIAe2NdElNpU/XaECGX77/aNshLSGmH3yo5QZUBVsbG55lCQkxSfBEmo ktbahVOVyTLG5IStMa+S3UEG0T3v6983R4ptNSKz1WlJkOIV4ieio6MMTZ9S6ZSvNLkx re5Sz1ZHevGLSNH80ua19vTRoQIC4NYZSAK4LPtqwOXPH02oMly8hfL8F0f225yicMtY CYZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=oSgkN+dTN7nRZb20JasKAqJ/0pKCu6M2zNDhcnKlGu0=; b=xLz70WE9aM++Ajp++4KNCTjNbilSA44yfkTSl7sb3qa6gh6mWp/aWHz3SHIXjZKgKM gOzfSjCLjmiNlrXxkoGrKoKxCMRyS7f1kQo/EKHH1+PfdebJa8kN2sB6Z+G96Fpzx33K 0eclWJUsdQ/c6KA/hF+LIv5zaBLaDALWIZBGv4nlf8XpHILXDIPieundZUbdb9Np5Y2W lGBhAMUSwHrUveKz9D3dc8xfVUqZOrH1rbSw6FJsbhArlH4VjkQgzsTKTrcm1RQKT+2Z 7u03Pn5OKNmnkVYeRCtc8AUJsmXSSYmcD4a+ECW8wNCAybTdvOUsNMY39YcTIYnWSd3f YeFw== X-Gm-Message-State: ACgBeo1cAx/emiBQoFPEY78qx+ZqSXDeZz0ZpYC+1yaMSeeJw6FTBY6h nnatZPxVWN8BNkj4oP0SvZyZse5f/0g= X-Google-Smtp-Source: AA6agR6WWMc3ZkdxZ/qB/4q1PzNtoY5Nih3Ar2rTZXIOvK3bglEb6Kp9bCIcl/7BDvowbchcx6VF7Q== X-Received: by 2002:a63:5b4f:0:b0:426:9c52:a1f with SMTP id l15-20020a635b4f000000b004269c520a1fmr14188278pgm.511.1661105928539; Sun, 21 Aug 2022 11:18:48 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id p27-20020aa79e9b000000b00535bed953e8sm7147739pfq.94.2022.08.21.11.18.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Aug 2022 11:18:47 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 1/5] iommu/arm-smmu-qcom: Fix indentation Date: Sun, 21 Aug 2022 11:19:02 -0700 Message-Id: <20220821181917.1188021-2-robdclark@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220821181917.1188021-1-robdclark@gmail.com> References: <20220821181917.1188021-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Plus typo. Signed-off-by: Rob Clark --- include/linux/adreno-smmu-priv.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index c637e0997f6d..ac4c2c0ab724 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -37,7 +37,7 @@ struct adreno_smmu_fault_info { /** * struct adreno_smmu_priv - private interface between adreno-smmu and GPU * - * @cookie: An opque token provided by adreno-smmu and passed + * @cookie: An opaque token provided by adreno-smmu and passed * back into the callbacks * @get_ttbr1_cfg: Get the TTBR1 config for the GPUs context-bank * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A @@ -61,12 +61,12 @@ struct adreno_smmu_fault_info { * it's domain. */ struct adreno_smmu_priv { - const void *cookie; - const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); - int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); - void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); - void (*set_stall)(const void *cookie, bool enabled); - void (*resume_translation)(const void *cookie, bool terminate); + const void *cookie; + const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); + int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); + void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); + void (*set_stall)(const void *cookie, bool enabled); + void (*resume_translation)(const void *cookie, bool terminate); }; #endif /* __ADRENO_SMMU_PRIV_H */ From patchwork Sun Aug 21 18:19:03 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 598916 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 780B2C32772 for ; Sun, 21 Aug 2022 18:18:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231684AbiHUSS4 (ORCPT ); Sun, 21 Aug 2022 14:18:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231679AbiHUSSz (ORCPT ); Sun, 21 Aug 2022 14:18:55 -0400 Received: from mail-pj1-x1029.google.com (mail-pj1-x1029.google.com [IPv6:2607:f8b0:4864:20::1029]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 41BCB1C12F; Sun, 21 Aug 2022 11:18:54 -0700 (PDT) Received: by mail-pj1-x1029.google.com with SMTP id s36-20020a17090a69a700b001faad0a7a34so11908786pjj.4; Sun, 21 Aug 2022 11:18:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=3UPV+AIr+VN1gJBjfNvC42kkO2spb7wnrBuGNcr6epA=; b=qvSOn95xRk74S7zpkCSkCjyYWsHCcZk6bI8EiNG721G1MkN0hChGYrFZXC4KLeE/I+ 4OJ+apvmmxlT0d86KhV/qCQw/sYVc6hVP6zkxAiettOdUxl9hQPWOx6PoYLRTtl7YQGJ DTu874p88RWKZUOTvQaToVZPYns9dhdjHDx/yq9qjAEou5Q/gJTlafvC7DP8ao4Lpyzt ApfRLIXQdlDXhLz4kYkymAP1Kjlu0/S7ygei/KXj1+Eab8wBJBNRjWvS0x7gPdleLnEB xeJy9jwo7wPZdQjDogYg+2QQR7q1rqP/qYK1VDEodix280gbUvEHWKl6BFrGrZaAxagE IuvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=3UPV+AIr+VN1gJBjfNvC42kkO2spb7wnrBuGNcr6epA=; b=5mC5sb5HD8LIjNmiqksAV+FBID5YSYqdQN8+LM6qOQ/ApiIycyXb1B/y3vO+oQgGxo Lp3Wr14VaXXWsvHQ4QrBWe1guoIIThh5QeGVq3Ii0SkPzc0quoqsGjQ9G6tr4ABXxfXi dX+zRD2bpE5MhoOJTruwV2ilYa1ZfKA/vZcYzPd6pz4ak1SzhL4AcesP5/FmmZHXF7ID 9k009dL7k5L+DCNLrk23yoFIE9L1NUWZiMuI9cVVD7kXR6f9XVvZzBgV91H4XxsxlPx6 NtfjszSIqMgwOLvQ2VlFYdgScGk9koDISPtuLe/GVZ0B/TTOuMptuYoOJb5nKyyODhHl zfZg== X-Gm-Message-State: ACgBeo3CZGYTayqVzDcWFGx1WiZBX9vAzkg9a0Rv8ZLS+Nh9/dZSduij 1X4e7ERXGxRKD7NllYJ1q8o= X-Google-Smtp-Source: AA6agR7dtmESYOitnU5DYhjNSHX3sh73wN0UvrFXYQMVn/nBm2N8GH+sNa7fESl2HF3bNjC49hhRdQ== X-Received: by 2002:a17:90b:3d7:b0:1fa:e708:ef43 with SMTP id go23-20020a17090b03d700b001fae708ef43mr13620916pjb.239.1661105933694; Sun, 21 Aug 2022 11:18:53 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id u16-20020a170903125000b001726b585d4bsm6792298plh.202.2022.08.21.11.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Aug 2022 11:18:52 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio , Loic Poulain , Vinod Koul , Sibi Sankar , linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU DRIVERS), iommu@lists.linux-foundation.org (open list:IOMMU DRIVERS), iommu@lists.linux.dev (open list:IOMMU DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 2/5] iommu/arm-smmu-qcom: Provide way to access current TTBR0 Date: Sun, 21 Aug 2022 11:19:03 -0700 Message-Id: <20220821181917.1188021-3-robdclark@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220821181917.1188021-1-robdclark@gmail.com> References: <20220821181917.1188021-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark The drm driver can skip tlbinv when unmapping from something that isn't the current pgtables, as there is already a tlbinv on context switch. Signed-off-by: Rob Clark --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 9 +++++++++ include/linux/adreno-smmu-priv.h | 2 ++ 2 files changed, 11 insertions(+) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 7820711c4560..59b460c1c9a5 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -157,6 +157,14 @@ static int qcom_adreno_smmu_set_ttbr0_cfg(const void *cookie, return 0; } +static u64 qcom_adreno_smmu_get_ttbr0(const void *cookie) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_cfg *cfg = &smmu_domain->cfg; + + return arm_smmu_cb_readq(smmu_domain->smmu, cfg->cbndx, ARM_SMMU_CB_TTBR0); +} + static int qcom_adreno_smmu_alloc_context_bank(struct arm_smmu_domain *smmu_domain, struct arm_smmu_device *smmu, struct device *dev, int start) @@ -217,6 +225,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->cookie = smmu_domain; priv->get_ttbr1_cfg = qcom_adreno_smmu_get_ttbr1_cfg; priv->set_ttbr0_cfg = qcom_adreno_smmu_set_ttbr0_cfg; + priv->get_ttbr0 = qcom_adreno_smmu_get_ttbr0; priv->get_fault_info = qcom_adreno_smmu_get_fault_info; priv->set_stall = qcom_adreno_smmu_set_stall; priv->resume_translation = qcom_adreno_smmu_resume_translation; diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index ac4c2c0ab724..4ad90541a095 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -43,6 +43,7 @@ struct adreno_smmu_fault_info { * @set_ttbr0_cfg: Set the TTBR0 config for the GPUs context bank. A * NULL config disables TTBR0 translation, otherwise * TTBR0 translation is enabled with the specified cfg + * @get_ttbr0: Get current TTBR0 value * @get_fault_info: Called by the GPU fault handler to get information about * the fault * @set_stall: Configure whether stall on fault (CFCFG) is enabled. Call @@ -64,6 +65,7 @@ struct adreno_smmu_priv { const void *cookie; const struct io_pgtable_cfg *(*get_ttbr1_cfg)(const void *cookie); int (*set_ttbr0_cfg)(const void *cookie, const struct io_pgtable_cfg *cfg); + u64 (*get_ttbr0)(const void *cookie); void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); void (*set_stall)(const void *cookie, bool enabled); void (*resume_translation)(const void *cookie, bool terminate); From patchwork Sun Aug 21 18:19:04 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 599566 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7B865C00140 for ; Sun, 21 Aug 2022 18:19:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231317AbiHUSTC (ORCPT ); Sun, 21 Aug 2022 14:19:02 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231703AbiHUSTC (ORCPT ); Sun, 21 Aug 2022 14:19:02 -0400 Received: from mail-pj1-x1033.google.com (mail-pj1-x1033.google.com [IPv6:2607:f8b0:4864:20::1033]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E67F11CFC1; Sun, 21 Aug 2022 11:19:00 -0700 (PDT) Received: by mail-pj1-x1033.google.com with SMTP id c16-20020a17090aa61000b001fb3286d9f7so294966pjq.1; Sun, 21 Aug 2022 11:19:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=Jefmh/chTekLzbM/ussShayTDA1/KVFu/osWTYpBS98=; b=WMH6h8qOVU9GDf+A1jGtjFuhN3wUSb5DKdVO9OB/9TqGckhh6xF3p7sXG5Itj9GXBM H1SZOXP4iee2g7Bzr5fKuWShQWBF0CnKh/FUcZ2dvlYQBLsD7w2Vxgk4PPx7NyRtSbDE aSouWTTJV4PBFUbzsZaLZ8IF5wteoL67D7cWxxtcPZ1VnVuSi3XJApuKSONS6R9AzzkJ nE2s0JyuCbMHeatvJ4msfrtw5vznIOu5Cl5jA20qb44qgU6241lQdSRjZR9rZks+QKtB w7qyRc2y8Qgp4PGQ7L8OehegQKs6KSUbHfmuZb1GQZmEL/v0ze8zJPY6s/InUrhcHVK3 SGpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=Jefmh/chTekLzbM/ussShayTDA1/KVFu/osWTYpBS98=; b=T8eiYUPd3/3RcA0s1NtR3tuZpkOrFnmeYHLeAuMrincCZgxLM5td1rVwTgApmFeKe+ 5Myxyt/9+I/Z7oKWxwe7kZdkXrXcKKImInThG4kdHEfUd//j9HUlIiIDRqNbpQOE2BfS vrkIUEP7NWixfIXz35Jctnb7FVPpFh224j+9pCOQJNoIJv1by9nsZZaXr5d8yXHOaxVO x+CzdSKI8P3lyHnn/k6hPyTn5TtdPa1bwcbWlrN0RiN5QA7Z1Lg86TG9LVktPPpjbHVU 0WR4WbEt+l5SgGd2+e2yeQHkFK8Ko7tocTeJSY1iFoy24Flps1CGF8W2hDtI9p0ew1tu nW1Q== X-Gm-Message-State: ACgBeo1H0cT7WhnY8LcYnmEyi/BNpI5WOmZAIhUyV+pEAohAWqnMr3h3 CT2qBoxoKNfwpO4BokEzxdI= X-Google-Smtp-Source: AA6agR59xeDDdukCYLQ+P3WWLp5KGrqni1O1UrEyEWs0/hLes29VrUFXlS2vHJ+xIiXb2XH+D7VjHw== X-Received: by 2002:a17:902:f70d:b0:16c:50a2:78d1 with SMTP id h13-20020a170902f70d00b0016c50a278d1mr16608447plo.34.1661105940414; Sun, 21 Aug 2022 11:19:00 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id x24-20020aa79418000000b0052d50e14f1dsm6986695pfo.78.2022.08.21.11.18.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Aug 2022 11:18:59 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Will Deacon , Robin Murphy , Joerg Roedel , Bjorn Andersson , Konrad Dybcio , Sibi Sankar , Vinod Koul , Loic Poulain , Yang Yingliang , Lu Baolu , linux-arm-kernel@lists.infradead.org (moderated list:ARM SMMU DRIVERS), iommu@lists.linux-foundation.org (open list:IOMMU DRIVERS), iommu@lists.linux.dev (open list:IOMMU DRIVERS), linux-kernel@vger.kernel.org (open list) Subject: [PATCH 3/5] iommu/arm-smmu-qcom: Add private interface to tlbinv by ASID Date: Sun, 21 Aug 2022 11:19:04 -0700 Message-Id: <20220821181917.1188021-4-robdclark@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220821181917.1188021-1-robdclark@gmail.com> References: <20220821181917.1188021-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark This will let the drm driver use different ASID values for each set of pgtables to avoid over-invalidation on unmap. Signed-off-by: Rob Clark --- drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c | 1 + drivers/iommu/arm/arm-smmu/arm-smmu.c | 43 ++++++++++++++++++++-- drivers/iommu/arm/arm-smmu/arm-smmu.h | 1 + include/linux/adreno-smmu-priv.h | 2 + 4 files changed, 43 insertions(+), 4 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c index 59b460c1c9a5..3230348729ab 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu-qcom.c @@ -229,6 +229,7 @@ static int qcom_adreno_smmu_init_context(struct arm_smmu_domain *smmu_domain, priv->get_fault_info = qcom_adreno_smmu_get_fault_info; priv->set_stall = qcom_adreno_smmu_set_stall; priv->resume_translation = qcom_adreno_smmu_resume_translation; + priv->tlb_inv_by_id = arm_smmu_tlb_inv_by_id; return 0; } diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.c b/drivers/iommu/arm/arm-smmu/arm-smmu.c index 2ed3594f384e..624359bb2092 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.c +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.c @@ -252,7 +252,7 @@ static void arm_smmu_tlb_sync_context(struct arm_smmu_domain *smmu_domain) spin_unlock_irqrestore(&smmu_domain->cb_lock, flags); } -static void arm_smmu_tlb_inv_context_s1(void *cookie) +static void arm_smmu_tlb_inv_context_s1_asid(void *cookie, u16 asid) { struct arm_smmu_domain *smmu_domain = cookie; /* @@ -261,21 +261,56 @@ static void arm_smmu_tlb_inv_context_s1(void *cookie) */ wmb(); arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, - ARM_SMMU_CB_S1_TLBIASID, smmu_domain->cfg.asid); + ARM_SMMU_CB_S1_TLBIASID, asid); arm_smmu_tlb_sync_context(smmu_domain); } -static void arm_smmu_tlb_inv_context_s2(void *cookie) +static void arm_smmu_tlb_inv_context_s1(void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + + arm_smmu_tlb_inv_context_s1_asid(cookie, smmu_domain->cfg.asid); +} + +static void arm_smmu_tlb_inv_context_s2_vmid(void *cookie, u16 vmid) { struct arm_smmu_domain *smmu_domain = cookie; struct arm_smmu_device *smmu = smmu_domain->smmu; /* See above */ wmb(); - arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); + arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, vmid); arm_smmu_tlb_sync_global(smmu); } +static void arm_smmu_tlb_inv_context_s2(void *cookie) +{ + struct arm_smmu_domain *smmu_domain = cookie; + + arm_smmu_tlb_inv_context_s2_vmid(cookie, smmu_domain->cfg.vmid); +} + +void arm_smmu_tlb_inv_by_id(const void *cookie, u16 id) +{ + struct arm_smmu_domain *smmu_domain = (void *)cookie; + struct arm_smmu_device *smmu = smmu_domain->smmu; + + arm_smmu_rpm_get(smmu); + switch (smmu_domain->stage) { + case ARM_SMMU_DOMAIN_S1: + arm_smmu_tlb_inv_context_s1_asid(smmu_domain, id); + break; + case ARM_SMMU_DOMAIN_S2: + case ARM_SMMU_DOMAIN_NESTED: + arm_smmu_tlb_inv_context_s2_vmid(smmu_domain, id); + break; + case ARM_SMMU_DOMAIN_BYPASS: + break; + } + + arm_smmu_rpm_put(smmu); +} + static void arm_smmu_tlb_inv_range_s1(unsigned long iova, size_t size, size_t granule, void *cookie, int reg) { diff --git a/drivers/iommu/arm/arm-smmu/arm-smmu.h b/drivers/iommu/arm/arm-smmu/arm-smmu.h index 2b9b42fb6f30..f6fb52d6f841 100644 --- a/drivers/iommu/arm/arm-smmu/arm-smmu.h +++ b/drivers/iommu/arm/arm-smmu/arm-smmu.h @@ -527,6 +527,7 @@ struct arm_smmu_device *arm_smmu_impl_init(struct arm_smmu_device *smmu); struct arm_smmu_device *nvidia_smmu_impl_init(struct arm_smmu_device *smmu); struct arm_smmu_device *qcom_smmu_impl_init(struct arm_smmu_device *smmu); +void arm_smmu_tlb_inv_by_id(const void *cookie, u16 id); void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx); int arm_mmu500_reset(struct arm_smmu_device *smmu); diff --git a/include/linux/adreno-smmu-priv.h b/include/linux/adreno-smmu-priv.h index 4ad90541a095..c44fc68d4de8 100644 --- a/include/linux/adreno-smmu-priv.h +++ b/include/linux/adreno-smmu-priv.h @@ -50,6 +50,7 @@ struct adreno_smmu_fault_info { * before set_ttbr0_cfg(). If stalling on fault is enabled, * the GPU driver must call resume_translation() * @resume_translation: Resume translation after a fault + * @tlb_inv_by_id: Flush TLB by ASID/VMID * * * The GPU driver (drm/msm) and adreno-smmu work together for controlling @@ -69,6 +70,7 @@ struct adreno_smmu_priv { void (*get_fault_info)(const void *cookie, struct adreno_smmu_fault_info *info); void (*set_stall)(const void *cookie, bool enabled); void (*resume_translation)(const void *cookie, bool terminate); + void (*tlb_inv_by_id)(const void *cookie, u16 id); }; #endif /* __ADRENO_SMMU_PRIV_H */ From patchwork Sun Aug 21 18:19:05 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 598915 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 920CBC00140 for ; Sun, 21 Aug 2022 18:19:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230463AbiHUSTK (ORCPT ); Sun, 21 Aug 2022 14:19:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32802 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231722AbiHUSTH (ORCPT ); Sun, 21 Aug 2022 14:19:07 -0400 Received: from mail-pf1-x435.google.com (mail-pf1-x435.google.com [IPv6:2607:f8b0:4864:20::435]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 422311E3DF; Sun, 21 Aug 2022 11:19:04 -0700 (PDT) Received: by mail-pf1-x435.google.com with SMTP id 1so1222847pfu.0; Sun, 21 Aug 2022 11:19:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=KXO1+rEYcOhr3W13ew7JJG2ZdVZOdgDfophycm+/cI0=; b=h1aW2/zXYwlI9VvEyEDwQ9nir0RGoIYAQo3OYZ+A3Sp5OunvV1JlLiVC1VKPARnRSp 3CIOd5VGLg3RTOWctI8KMhDLNAaTyAMXGiqLBkVTj0nVK8Ad7WA401gjUBqpO+VbSp7/ k3KsR+5F/A14QIdl0m0StrFVoo0dqJG+EBJ/vQazrR2VyW+lCOKuIdcS1pYFGgMbgEu0 jPxgEl07gjPZKxHW8S7qYp68TPn8xBJxrS+XeLPRklEflMigP36Auo0NvLUJ7IQ3vWM/ 80CH9dxNboipowi+j4daxl4cF6EBBaaS/4KStd9ixV5QyUjbftbikbaZ0wMyhLiQx/H3 zSFg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=KXO1+rEYcOhr3W13ew7JJG2ZdVZOdgDfophycm+/cI0=; b=SytQtU3suzdc7VZTUYLdUTL5IvOE05qu9nFTGin5j7rtEE79dCFvO3CKy+MrVkrhlv mwMM73bYZaXpKSXyAhH1QSm7F8wt/AdWYdCW6SvSg3hq7GjQWpXpG1W4EKpefvk69XGu yL6wvZGZdKy1W1um1XQE/QDHa9BkBsAQsBxF2l6Q6S7+KwgGf4cBCwW2PMRb1BR/qnFg bdf5027yXLIWwZU/yS0c5JBVfARbJwXX8yFeoPquh5IxyABlXijnCleTg/GBlJflsuOW nRKtJnyNqwRVPqCLih64zSVri1XxO9UFFXp+IuRfygUkP3RuMDB7g8wGx5KZYSQ2OcUs zhsA== X-Gm-Message-State: ACgBeo0hc95je4wJlAvJ+2CzRlNGxjOI4gCgbJreFWAQGQWOZ4Pgj83k DbY/6Z7EelrA0qRSnpRw18M= X-Google-Smtp-Source: AA6agR6i0s4MALSYERHLBE5fmy618sONp39l+osO9fV7k/dJmjUVOWdy1MMzZG71HDJc5xKgxOAxbQ== X-Received: by 2002:a63:88c8:0:b0:41d:260c:ea29 with SMTP id l191-20020a6388c8000000b0041d260cea29mr14004283pgd.284.1661105943530; Sun, 21 Aug 2022 11:19:03 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id r6-20020a634406000000b0042a6dde1d66sm2711467pga.43.2022.08.21.11.19.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Aug 2022 11:19:01 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 4/5] drm/msm: Use separate ASID for each set of pgtables Date: Sun, 21 Aug 2022 11:19:05 -0700 Message-Id: <20220821181917.1188021-5-robdclark@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220821181917.1188021-1-robdclark@gmail.com> References: <20220821181917.1188021-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Optimize TLB invalidation by using different ASID for each set of pgtables. There can be scenarios where multiple processes end up with the same ASID (such as >256 processes using the GPU), but this is harmless, it will only result in some over-invalidation (but less over-invalidation compared to using ASID=0 for all processes) Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/msm_iommu.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index a54ed354578b..94c8c09980d1 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -33,6 +33,8 @@ static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, size_t size) { struct msm_iommu_pagetable *pagetable = to_pagetable(mmu); + struct adreno_smmu_priv *adreno_smmu = + dev_get_drvdata(pagetable->parent->dev); struct io_pgtable_ops *ops = pagetable->pgtbl_ops; size_t unmapped = 0; @@ -43,7 +45,7 @@ static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, size -= 4096; } - iommu_flush_iotlb_all(to_msm_iommu(pagetable->parent)->domain); + adreno_smmu->tlb_inv_by_id(adreno_smmu->cookie, pagetable->asid); return (unmapped == size) ? 0 : -EINVAL; } @@ -147,6 +149,7 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) { + static atomic_t asid = ATOMIC_INIT(1); struct adreno_smmu_priv *adreno_smmu = dev_get_drvdata(parent->dev); struct msm_iommu *iommu = to_msm_iommu(parent); struct msm_iommu_pagetable *pagetable; @@ -210,12 +213,14 @@ struct msm_mmu *msm_iommu_pagetable_create(struct msm_mmu *parent) pagetable->ttbr = ttbr0_cfg.arm_lpae_s1_cfg.ttbr; /* - * TODO we would like each set of page tables to have a unique ASID - * to optimize TLB invalidation. But iommu_flush_iotlb_all() will - * end up flushing the ASID used for TTBR1 pagetables, which is not - * what we want. So for now just use the same ASID as TTBR1. + * ASID 0 is used for kernel mapped buffers in TTBR1, which we + * do not need to invalidate when unmapping from TTBR0 pgtables. + * The hw ASID is at *least* 8b, but can be 16b. We just assume + * the worst: */ pagetable->asid = 0; + while (!pagetable->asid) + pagetable->asid = atomic_inc_return(&asid) & 0xff; return &pagetable->base; } From patchwork Sun Aug 21 18:19:06 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 599565 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6C7EBC32772 for ; Sun, 21 Aug 2022 18:19:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231733AbiHUSTR (ORCPT ); Sun, 21 Aug 2022 14:19:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60844 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231734AbiHUSTJ (ORCPT ); Sun, 21 Aug 2022 14:19:09 -0400 Received: from mail-pg1-x52e.google.com (mail-pg1-x52e.google.com [IPv6:2607:f8b0:4864:20::52e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 85940205F3; Sun, 21 Aug 2022 11:19:08 -0700 (PDT) Received: by mail-pg1-x52e.google.com with SMTP id r22so7585086pgm.5; Sun, 21 Aug 2022 11:19:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=rJPJHp4WUC+k2ZugmXMrEl/gry6ReB2YgyAezAf1/ks=; b=igd3L5C0F/igLnISA3+VP7PELE0Tt3GXUb3snhvjwtOdEzx9eRDgu/de4iZ4v8ZByJ 9p8GsGJC4YZ5AIL7Baq8coyhYhSJlmsz8t61OWkgsoxBiRA8UjJdLUtJv4e6Wd82LuYq YPnSx1vQV1elOuCFKu6lsmXcy3XvF8MvBudyOhK2cf/4X3p7aBLcbyFVpmtyxOsyUNfv jsL1sPaOcZ9p3pub/xX3MxRTnbjyQzn6Q+NgQbFeH5HB4NBRdr2kp9DMEtkJiBh0HnBm CJYGRjFHNaxi6TooTGYKT8+O5Ime+KG9p/MJMa/Gzco2Vc2UKU4rcnUTtcNJsndoT2K3 XALA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=rJPJHp4WUC+k2ZugmXMrEl/gry6ReB2YgyAezAf1/ks=; b=0BaHyIg9t6ypmF/78fvxgM6vegHs1AZk9ebEAmqGZANUluv8zp21x1s1cwStEpe2AH i8mH+6wsU6topHt8/zMuLZvbZmeGNYidSJ5UIKiSACoSdHIJUS1zP0dwP+SY5mOjFsqj dftIh/2/OgwJxe8VkNGOnI0XGmUJOJS8MQl9SGqoFDRMesOUYABQrrX3BIw3c45RB+w6 cMDvpVEfVtBzbiY1fl8qbMAthP/Mhz+7L1c7GR53yrf+8oUwzNozu9zy2wuXTdYLzcT7 Pfs5iW4nBFWU2Vzwmnw1cxVz61gYg+3BotY3kj4ln7fLzUfEb8+/WtU2iDMHulozanRW cNIg== X-Gm-Message-State: ACgBeo3WoJD7potKdXGLUZxkW7wAe+dcgIvIQhs9z3bV0sGtoZBRu3C/ fBdXVUJJNa2lDh5mh2pxGMs= X-Google-Smtp-Source: AA6agR7grPVWv0p0d5feTVXYX0q0iIO3i4jluQbDa7BvmI7ly44pt5otEGUi/E8EyZ4IvklYGtFK9A== X-Received: by 2002:a05:6a00:27a0:b0:52f:8947:4cc5 with SMTP id bd32-20020a056a0027a000b0052f89474cc5mr17505693pfb.16.1661105947769; Sun, 21 Aug 2022 11:19:07 -0700 (PDT) Received: from localhost ([2601:1c0:5200:a6:307:a401:7b76:c6e5]) by smtp.gmail.com with ESMTPSA id nt22-20020a17090b249600b001f55dda84b3sm6602422pjb.22.2022.08.21.11.19.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 21 Aug 2022 11:19:06 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Rob Clark , Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Akhil P Oommen , Konrad Dybcio , Chia-I Wu , Douglas Anderson , linux-kernel@vger.kernel.org (open list) Subject: [PATCH 5/5] drm/msm: Skip tlbinv on unmap from non-current pgtables Date: Sun, 21 Aug 2022 11:19:06 -0700 Message-Id: <20220821181917.1188021-6-robdclark@gmail.com> X-Mailer: git-send-email 2.37.2 In-Reply-To: <20220821181917.1188021-1-robdclark@gmail.com> References: <20220821181917.1188021-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark We can rely on the tlbinv done by CP_SMMU_TABLE_UPDATE in this case. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 6 ++++++ drivers/gpu/drm/msm/msm_iommu.c | 29 +++++++++++++++++++++++++++ 2 files changed, 35 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index c8ad8aeca777..1ba0ed629549 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1180,6 +1180,12 @@ static int hw_init(struct msm_gpu *gpu) /* Always come up on rb 0 */ a6xx_gpu->cur_ring = gpu->rb[0]; + /* + * Note, we cannot assume anything about the state of the SMMU when + * coming back from power collapse, so force a CP_SMMU_TABLE_UPDATE + * on the first submit. Also, msm_iommu_pagetable_unmap() relies on + * this behavior. + */ gpu->cur_ctx_seqno = 0; /* Enable the SQE_to start the CP engine */ diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 94c8c09980d1..218074a58081 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -45,8 +45,37 @@ static int msm_iommu_pagetable_unmap(struct msm_mmu *mmu, u64 iova, size -= 4096; } + /* + * A CP_SMMU_TABLE_UPDATE is always sent for the first + * submit after resume, and that does a TLB invalidate. + * So we can skip that if the device is not currently + * powered. + */ + if (!pm_runtime_get_if_in_use(pagetable->parent->dev)) + goto out; + + /* + * If we are not the current pgtables, we can rely on the + * TLB invalidate done by CP_SMMU_TABLE_UPDATE. + * + * We'll always be racing with the GPU updating ttbr0, + * but there are only two cases: + * + * + either we are not the the current pgtables and there + * will be a tlbinv done by the GPU before we are again + * + * + or we are.. there might have already been a tblinv + * if we raced with the GPU, but we have to assume the + * worse and do the tlbinv + */ + if (adreno_smmu->get_ttbr0(adreno_smmu->cookie) != pagetable->ttbr) + goto out_put; + adreno_smmu->tlb_inv_by_id(adreno_smmu->cookie, pagetable->asid); +out_put: + pm_runtime_put(pagetable->parent->dev); +out: return (unmapped == size) ? 0 : -EINVAL; }