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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 8A7031FF81; Tue, 5 Feb 2019 19:02:24 +0000 (UTC) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 19:02:19 +0000 Message-Id: <20190205190224.2198-2-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205190224.2198-1-alex.bennee@linaro.org> References: <20190205190224.2198-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 Subject: [Qemu-devel] [PATCH v2 1/6] target/arm: relax permission checks for HWCAP_CPUID registers X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Although technically not visible to userspace the kernel does make them visible via a trap and emulate ABI. We provide a new permission mask (PL0U_R) which maps to PL0_R for CONFIG_USER builds and adjust the minimum permission check accordingly. Signed-off-by: Alex Bennée --- target/arm/cpu.h | 12 ++++++++++++ target/arm/helper.c | 6 +++++- 2 files changed, 17 insertions(+), 1 deletion(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a68bcc9fed..1616632dcb 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2211,6 +2211,18 @@ static inline bool cptype_valid(int cptype) #define PL0_R (0x02 | PL1_R) #define PL0_W (0x01 | PL1_W) +/* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ +#ifdef CONFIG_USER_ONLY +#define PL0U_R PL0_R +#else +#define PL0U_R PL1_R +#endif + #define PL3_RW (PL3_R | PL3_W) #define PL2_RW (PL2_R | PL2_W) #define PL1_RW (PL1_R | PL1_W) diff --git a/target/arm/helper.c b/target/arm/helper.c index d070879894..5857c0ba96 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6851,7 +6851,11 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, if (r->state != ARM_CP_STATE_AA32) { int mask = 0; switch (r->opc1) { - case 0: case 1: case 2: + case 0: + /* min_EL EL1, but some accessible to EL0 via kernel ABI */ + mask = PL0U_R | PL1_RW; + break; + case 1: case 2: /* min_EL EL1 */ mask = PL1_RW; break; From patchwork Tue Feb 5 19:02:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 157527 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5576143jaa; Tue, 5 Feb 2019 11:56:01 -0800 (PST) X-Google-Smtp-Source: AHgI3IaNghdJw6201koaWQtjdQUKxCZ9oEgGxeh6oIL+94E80tS0ehffU1h96JzSwMZfyl6tqT4J X-Received: by 2002:a81:594:: with SMTP id 142mr5600441ywf.294.1549396561510; Tue, 05 Feb 2019 11:56:01 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549396561; cv=none; d=google.com; s=arc-20160816; b=sGNiXoXOjzrpHMu5twF0p+A3QTFXfxbRjgo+bbgBYv4YHKzASuYTm+/jp9UT+dulWC KY0XnPZP4OLw8+v29Etnv3OtkkZAmNNN/vxfexcCZTmz1Os8276O0+0XjUO5DZQz2o8t 1H8Tl9QDgryvAebh/ZajWhE92qbvM+nDfHhWEPNsujeC4qaYnstWRdABQ8Hl/yoByi4z pHKdl5IerzdMboHyxbtUMFE4s1zF1SDEWhEodGQIC/Zd2+32VdwoECGjVNRJUaQtqIOG SQkuPYzIoVJP/OKXfYYU11oqWugUUBJFu/yMCwJjIKmVAyOXsRr689t2sfLoNeWNwwIs 016w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=5K8fEiIOFo1VDdNnkd2vN+zdBEFCMFkNkVT82ANMtrs=; b=Ud+eGVMAcRb/0kmG7aeMIRULER9QNFywS3bwNjF54FzSkkiie1iI7OD3LMOlI5eH4q zpODd7bF1389sfnrNwrhgLA9sumuvHOMnkr2GpOn5jOD/weOlMHrPyc1YRSH9YUwVBVA 5gXAmxpy1+C35awZeRk2V1+zEg/VvOevtKFRhZkCVg+fTd8hwomyxKyJklPaXDLnbScd 3hr/TQKKqIZHD7GgQao2hgdsTvT+c9LkFEcNKg2D/WF/LPZ/wKmXgUXCEhxGEM+Z3s5R gY4oEt2U+CAOWb/2iji/8ZGOFj2haQugw/fDXAgnIsgQJL6BBxlKoV5SDz/JaerB7Idm h3Gw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Y+RdRgBy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id 9600C1FF82; Tue, 5 Feb 2019 19:02:24 +0000 (UTC) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 19:02:20 +0000 Message-Id: <20190205190224.2198-3-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205190224.2198-1-alex.bennee@linaro.org> References: <20190205190224.2198-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 Subject: [Qemu-devel] [PATCH v2 2/6] target/arm: expose CPUID registers to userspace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" A number of CPUID registers are exposed to userspace by modern Linux kernels thanks to the "ARM64 CPU Feature Registers" ABI. For QEMU's user-mode emulation we don't need to emulate the kernels trap but just return the value the trap would have done. To avoid too much #ifdef hackery we process ARMCPRegInfo with a new helper (modify_arm_cp_regs) before defining the registers. The modify routine is driven by a simple data structure which describes which bits are exported and which are fixed. Signed-off-by: Alex Bennée --- v4 - tweak commit message - use PL0U_R instead of PL1U_R to be less confusing - more CONFIG_USER logic for special cases - mask a bunch of bits for some registers v5 - use data driven modify_arm_cp_regs --- target/arm/cpu.h | 21 ++++++++++++++++ target/arm/helper.c | 59 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 80 insertions(+) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1616632dcb..354df22102 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2449,6 +2449,27 @@ static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *regs) } const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp); +/* + * Definition of an ARM co-processor register as viewed from + * userspace. This is used for presenting sanitised versions of + * registers to userspace when emulating the Linux AArch64 CPU + * ID/feature ABI (advertised as HWCAP_CPUID). + */ +typedef struct ARMCPRegUserSpaceInfo { + /* Name of register */ + const char *name; + + /* Only some bits are exported to user space */ + uint64_t exported_bits; + + /* Fixed bits are applied after the mask */ + uint64_t fixed_bits; +} ARMCPRegUserSpaceInfo; + +#define REGUSERINFO_SENTINEL { .name = NULL } + +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods); + /* CPWriteFn that can be used to implement writes-ignored behaviour */ void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value); diff --git a/target/arm/helper.c b/target/arm/helper.c index 5857c0ba96..f90754cc11 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6103,6 +6103,30 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue = cpu->pmceid1 }, REGINFO_SENTINEL }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo v8_user_idregs[] = { + { .name = "ID_AA64PFR0_EL1", + .exported_bits = 0x000f000f00ff0000, + .fixed_bits = 0x0000000000000011 }, + { .name = "ID_AA64PFR1_EL1", + .exported_bits = 0x00000000000000f0 }, + { .name = "ID_AA64ZFR0_EL1" }, + { .name = "ID_AA64MMFR0_EL1", + .fixed_bits = 0x00000000ff000000 }, + { .name = "ID_AA64MMFR1_EL1" }, + { .name = "ID_AA64DFR0_EL1", + .fixed_bits = 0x0000000000000006 }, + { .name = "ID_AA64DFR1_EL1" }, + { .name = "ID_AA64AFR0_EL1" }, + { .name = "ID_AA64AFR1_EL1" }, + { .name = "ID_AA64ISAR0_EL1", + .exported_bits = 0x00fffffff0fffff0 }, + { .name = "ID_AA64ISAR1_EL1", + .exported_bits = 0x000000f0ffffffff }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(v8_idregs, v8_user_idregs); +#endif /* RVBAR_EL1 is only implemented if EL1 is the highest EL */ if (!arm_feature(env, ARM_FEATURE_EL3) && !arm_feature(env, ARM_FEATURE_EL2)) { @@ -6379,6 +6403,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W, .type = ARM_CP_NOP | ARM_CP_OVERRIDE }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = { + { .name = "MIDR_EL1", + .exported_bits = 0x00000000ffffffff }, + { .name = "REVIDR_EL1" }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_reginfo); +#endif if (arm_feature(env, ARM_FEATURE_OMAPCP) || arm_feature(env, ARM_FEATURE_STRONGARM)) { ARMCPRegInfo *r; @@ -6960,6 +6993,32 @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu, } } +/* + * Modify ARMCPRegInfo for access from userspace. + * + * This is a data driven modification directed by + * ARMCPRegUserSpaceInfo. All registers become ARM_CP_CONST as + * user-space cannot alter any values and dynamic values pertaining to + * execution state are hidden from user space view anyway. + */ +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods) +{ + const ARMCPRegUserSpaceInfo *m; + ARMCPRegInfo *r; + + for (m = mods; m->name; m++) { + for (r = regs; r->type != ARM_CP_SENTINEL; r++) { + if (strcmp(r->name, m->name) == 0) { + r->type = ARM_CP_CONST; + r->access = PL0U_R; + r->resetvalue &= m->exported_bits; + r->resetvalue |= m->fixed_bits; + break; + } + } + } +} + const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp) { return g_hash_table_lookup(cpregs, &encoded_cp); From patchwork Tue Feb 5 19:02:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 157528 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5578328jaa; Tue, 5 Feb 2019 11:58:40 -0800 (PST) X-Google-Smtp-Source: AHgI3IZguecrkwrr0vFkb8jjLwm7/HcLgD1U9FVyK+1YGKzokl9AOYLjj/dvftivbuq4oP5/0GkB X-Received: by 2002:a81:d804:: with SMTP id d4mr5332182ywj.197.1549396720592; Tue, 05 Feb 2019 11:58:40 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549396720; cv=none; d=google.com; s=arc-20160816; b=PQ25OCb8/eGSjmFqZ7h9cUhDNczvs6dy1iT9cIJDJhlAPcL2Dm5suJ91kH7bKv1utP tPpqjTZvhGcAKjKrdqynW2ZCtzrio4xEBl3qCHGIAHm4rA204ZJtmDI//9zGKeXRcRkQ pBkRXGavlZ/LV0YyMDuznYNuVeJxO+fN+M55JOgxaspzmdrLgbzNV/tDS7tpLzc9BXZ4 LvU+Vg8fEiQpjaUWFUsZSRXjkjIZw+WyEfB1Qr8vgtZnBA68+PrCvqaJlDdC+/4d9TeF S/JYl3woIEkbF43WMEgwZ8TP14spbDhTRFNyBo6E5MMxOkTm7J44ypjPX0na7S8zA2Z8 F/Pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=VSMGan48u0jw2BmDqDF3JBDZ7ZffWC3BIeULp9LWLWg=; b=pEMc1SWlWWSVE0IAJqfr+WRXps3nihqEyvDw3GiLfQ0etzJQOlIXHeJvDLgNOQO8Lb SWXvLDeCzZpGcy0wQdQusUChOLFkd8bJKEkqB6GZwYLdKndE3eNCWdV0eZRwyg4HNqo8 kKPXWLQb2UD2VAGwpbNwnPqU9GnQZVjifT7FpK/voGDfugN+7GEGOaA2k8KwOcESaXGM 6mY6xJIWFWcYMLzH8ARRIs9vv5klW2Noqtsmf/mWr8E4jlcHBnL20xA9PWoEa8uVvMs+ ZxeGvJRqnhbuVfvUGMl4LxLISfoUkHpDhuikahNDpqzAvMLNoygsQCFkvEIDDmyIekD4 ClgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qDtPFwsV; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id A1C4A1FF83; Tue, 5 Feb 2019 19:02:24 +0000 (UTC) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 19:02:21 +0000 Message-Id: <20190205190224.2198-4-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205190224.2198-1-alex.bennee@linaro.org> References: <20190205190224.2198-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH v2 3/6] target/arm: expose MPIDR_EL1 to userspace X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" As this is a single register we could expose it with a simple ifdef but we use the existing modify_arm_cp_regs mechanism for consistency. Signed-off-by: Alex Bennée --- target/arm/helper.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) -- 2.20.1 diff --git a/target/arm/helper.c b/target/arm/helper.c index f90754cc11..f2f868ff92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3657,13 +3657,6 @@ static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri) return mpidr_read_val(env); } -static const ARMCPRegInfo mpidr_cp_reginfo[] = { - { .name = "MPIDR", .state = ARM_CP_STATE_BOTH, - .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, - .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, - REGINFO_SENTINEL -}; - static const ARMCPRegInfo lpae_cp_reginfo[] = { /* NOP AMAIR0/1 */ { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH, @@ -6445,6 +6438,20 @@ void register_cp_regs_for_features(ARMCPU *cpu) } if (arm_feature(env, ARM_FEATURE_MPIDR)) { + ARMCPRegInfo mpidr_cp_reginfo[] = { + { .name = "MPIDR_EL1", .state = ARM_CP_STATE_BOTH, + .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5, + .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_RAW }, + REGINFO_SENTINEL + }; +#ifdef CONFIG_USER_ONLY + ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] = { + { .name = "MPIDR_EL1", + .fixed_bits = 0x0000000080000000 }, + REGUSERINFO_SENTINEL + }; + modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); +#endif define_arm_cp_regs(cpu, mpidr_cp_reginfo); } From patchwork Tue Feb 5 19:02:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 157525 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5566422jaa; Tue, 5 Feb 2019 11:45:28 -0800 (PST) X-Google-Smtp-Source: AHgI3Iab2uf3T7ZEJmrRil/CAnsIrYjzg9lBbHINUWYqls+MxmZ+S5fLYqVGEOyLivoyVkj11MAd X-Received: by 2002:a81:2b04:: with SMTP id r4mr5494262ywr.511.1549395928500; Tue, 05 Feb 2019 11:45:28 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549395928; cv=none; d=google.com; s=arc-20160816; b=ChWByr4Vk/uKa0ALA1hKgPAJBuueX47/oisUwgQt4wwSJ0mLNlDheEwXddXaOyCVCs btetKCY+7X02lhB7r7l8aj5jfHL6eg/ZUFjTr97QequG8SvlSIfKpYMFYFEERtCMVZ0K kwEpNoEzv8+oSV9bkx6Of/zNe+SC31XazgZb/mtxa6y5OKHnyNNxMkDM4Y49utKnV44H +Pf/ODPcha3vpN7Ky7Dp8/oppFR9eo9ry6eQWDieiTuaJj1K3PxuQcx0P+o4R2/R69SZ D8C/oeJrkjRXoyNu3ektsuu1jeEj+QVjZYUCY3QgjZhfQP/FQcinwWgFBqLOZ7Ah1ous cI5w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ZLy6kz/6AjHnhkCqfnV/PRmZe1fLFRArOryBT2bgJ3I=; b=vbC/6O8QpamfIuiqdQV5XlFgF8yhGmz1z5vCCdUHuX106MEaYSmnd7xJZHWl2h9t8a qhyXlqra877dXmvhaA3f2PFTUKa9ji5XwXBeB1b5Ebsxgg3C6D+LX4YZ2KJss/mrKY/q 29xSQTVQ8SvgKGJ5gc77Pv9qYryzYVw+hO/vS3XdyGA2YHIyzzruFuEc8EOLuXt5G1iB BmJRnJDJK0m1NWA4t2/oMWVIbrZ8575ZCiDm/0lX9doR3lWQEGB2VxFVdtTfQTHtVSNy MxwSfWeAO9k9M1Af+EnzZDtQVvOVK4EH0YgHipMfFzgFzXlAam9w0vq/wFoz5E05QOoe pKsw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=kLV7IU3n; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id AD8B21FF84; Tue, 5 Feb 2019 19:02:24 +0000 (UTC) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 19:02:22 +0000 Message-Id: <20190205190224.2198-5-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205190224.2198-1-alex.bennee@linaro.org> References: <20190205190224.2198-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v2 4/6] target/arm: expose remaining CPUID registers as RAZ X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" There are a whole bunch more registers in the CPUID space which are currently not used but are exposed as RAZ. To avoid too much duplication we expand ARMCPRegUserSpaceInfo to understand glob patterns so we only need one entry to tweak whole ranges of registers. Signed-off-by: Alex Bennée --- target/arm/cpu.h | 3 +++ target/arm/helper.c | 26 +++++++++++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) -- 2.20.1 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 354df22102..ae8ccc7dec 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2459,6 +2459,9 @@ typedef struct ARMCPRegUserSpaceInfo { /* Name of register */ const char *name; + /* Is the name actually a glob pattern */ + bool is_glob; + /* Only some bits are exported to user space */ uint64_t exported_bits; diff --git a/target/arm/helper.c b/target/arm/helper.c index f2f868ff92..e999da165b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6103,19 +6103,27 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fixed_bits = 0x0000000000000011 }, { .name = "ID_AA64PFR1_EL1", .exported_bits = 0x00000000000000f0 }, + { .name = "ID_AA64PFR*_EL1_RESERVED", + .is_glob = true }, { .name = "ID_AA64ZFR0_EL1" }, { .name = "ID_AA64MMFR0_EL1", .fixed_bits = 0x00000000ff000000 }, { .name = "ID_AA64MMFR1_EL1" }, + { .name = "ID_AA64MMFR*_EL1_RESERVED", + .is_glob = true }, { .name = "ID_AA64DFR0_EL1", .fixed_bits = 0x0000000000000006 }, { .name = "ID_AA64DFR1_EL1" }, - { .name = "ID_AA64AFR0_EL1" }, - { .name = "ID_AA64AFR1_EL1" }, + { .name = "ID_AA64DFR*_EL1_RESERVED", + .is_glob = true }, + { .name = "ID_AA64AFR*", + .is_glob = true }, { .name = "ID_AA64ISAR0_EL1", .exported_bits = 0x00fffffff0fffff0 }, { .name = "ID_AA64ISAR1_EL1", .exported_bits = 0x000000f0ffffffff }, + { .name = "ID_AA64ISAR*_EL1_RESERVED", + .is_glob = true }, REGUSERINFO_SENTINEL }; modify_arm_cp_regs(v8_idregs, v8_user_idregs); @@ -7014,8 +7022,17 @@ void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods) ARMCPRegInfo *r; for (m = mods; m->name; m++) { + GPatternSpec *pat = NULL; + if (m->is_glob) { + pat = g_pattern_spec_new(m->name); + } for (r = regs; r->type != ARM_CP_SENTINEL; r++) { - if (strcmp(r->name, m->name) == 0) { + if (pat && g_pattern_match_string(pat, r->name)) { + r->type = ARM_CP_CONST; + r->access = PL0U_R; + r->resetvalue = 0; + /* continue */ + } else if (strcmp(r->name, m->name) == 0) { r->type = ARM_CP_CONST; r->access = PL0U_R; r->resetvalue &= m->exported_bits; @@ -7023,6 +7040,9 @@ void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *mods) break; } } + if (pat) { + g_pattern_spec_free(pat); + } } } From patchwork Tue Feb 5 19:02:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 157529 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5586735jaa; Tue, 5 Feb 2019 12:06:03 -0800 (PST) X-Google-Smtp-Source: AHgI3IaJxQ+JiY6j6XQOaZg31LcCmaQO5Wg41ePhwq1RkPMCw3YBCOKjKAXiEw7OAAWhwbLdJ1st X-Received: by 2002:a0d:da44:: with SMTP id c65mr5592709ywe.218.1549397163649; Tue, 05 Feb 2019 12:06:03 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549397163; cv=none; d=google.com; s=arc-20160816; b=PBDbLDG9QPwIFqKYojGX9+KkonLYb4SJT/WGa4RjK5VV2/NBs/4Rk1LVwMSyw0m+JP W5v69VpHVJuWMcFMn07nhZK4Gt08tu0hJH2QcqACg8LckX/+X96l/RmPJCLnTGRLmr7o kUdtzQYP0+cT9uM4KzG0dglJEf2tS/LLH4xv07IqyzcFAcKn6Y63DUMvonXfjOZctTHE p56zcptGPGiNZi1WGgPkzCbaVLQTBlxdhTYcTX59HylB0uVVlW/LUbjDuODiLW+X56Bm abHER4tl7U6NYiHDXS3BmprbszzrAFSddqKZuk4Hwe3AbSs5cSPQx8bSFLNrXOnNbBTG ujcg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=V6utdBoArSjP75yC+1U3GRv6m7Z5RTe0msKq4eU8rIc=; b=Lp8GBFYRJMHkwUpB17RDnn0bo9Notn1ZDa7+xntt8mHH8CF1dZSbL/PnqUiDt/KWxW n9YZ7MUvlpy0uvSfWZgON1Fnwpa8euVLiXK3RzrjFOgjKsO+i5vjJUJ8l8/xhOrW566x EdVyMb7Xe1BGfWvv6pw4Pqemi31WxU+c+CUgxpKR8MfOhr7hzslcEXN0GKl+cEyPudj+ wgJAH8aUse89O6TJd9J79EyUZ6wxUoNZ5BAKZHw1MXEbQ2Ip8eTwWNdfEe3fLDPJPry1 zq4flLLTLlZLH/zzM9bhlsfhKpOSnI/r9J1YM+aI4YWCTnJls5WiXcFVkAaRXDU7s/Us UpjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=qzMlilZr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id B935C1FF85; Tue, 5 Feb 2019 19:02:24 +0000 (UTC) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 19:02:23 +0000 Message-Id: <20190205190224.2198-6-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205190224.2198-1-alex.bennee@linaro.org> References: <20190205190224.2198-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::443 Subject: [Qemu-devel] [PATCH v2 5/6] linux-user/elfload: enable HWCAP_CPUID for AArch64 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson , qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Userspace programs should (in theory) query the ELF HWCAP before probing these registers. Now we have implemented them all make it public. Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- linux-user/elfload.c | 1 + 1 file changed, 1 insertion(+) -- 2.20.1 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 775a36ccdd..3a50d587ff 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -580,6 +580,7 @@ static uint32_t get_elf_hwcap(void) hwcaps |= ARM_HWCAP_A64_FP; hwcaps |= ARM_HWCAP_A64_ASIMD; + hwcaps |= ARM_HWCAP_A64_CPUID; /* probe for the extra features */ #define GET_FEATURE_ID(feat, hwcap) \ From patchwork Tue Feb 5 19:02:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 157526 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp5572286jaa; Tue, 5 Feb 2019 11:51:31 -0800 (PST) X-Google-Smtp-Source: AHgI3Ib6+aTnxJNY8x/K2DuIZ3ANhEPX7R/ZIEol/G8htPPaRZ3M0TUfKoHsH+KEK4Gz45L43tTd X-Received: by 2002:a5b:4b:: with SMTP id e11mr2674820ybp.5.1549396291523; Tue, 05 Feb 2019 11:51:31 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549396291; cv=none; d=google.com; s=arc-20160816; b=02KVwb/01UCM7aYOM2XSOK4SXFQVGyBBnmo+JrgebKHNDpLD7W9gPDtwRLEP9e876W 9ffU3CKmqFYqbNr2aH39HYiTXKO5Ow4+7BY9+AGh1zgF+NVjXozcoHs2PMv/DmfrQ+vs s683UwP5WsicTze7/721l290rORTq4Hx7HYzuU9EfouDzNpJn/x2EOmc32+gRHmTz8qi 3B0tXn35tz0bAUSOXnqFjkRuelhkYPKER36OpMUu6nYbeb+WNRimbEyHIG2HnVNBbo3S x2G1R5Xgl3jhBdL1byrIlLSg7s5BYYfMjLOwzab+xVyDIHLWX+Ywo/qMK+I3r9BkPXz6 VcDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject :content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=BNzh66bB0nnDDrV+CbNUUVwPZKwG8xcxSjnQQStKqsw=; b=HURJasZJGYlSqn29op+vj3cYTC2nXFsra+YgczCIPG4Me3vLYzjmKb+W3FnKf9JMcx 2SaJqUU0LTcvgWtB5shvvnxRfWwp5pc1YsB0ARBIJLrO6KnsnOlis7TaWGS97cwJvrhR utsPh+n1BQoKO4DLiDcdcXfUfMexYivXxkqYuoM3qFeCoifutlMFHZapbx4uPz8lahN9 lFspd0XrWFAYXH+c2bsKRhU60FRsmUDc1aS7akojEoNxE0wDvEgqLHAWp6D9FG4/f0nz iwNKNhEE7ssMmUDImygMgbbzKUiNDO9pfNgc+Sjpw0VyB5pHQq9Gv6JktjlXyyYzKmYb NqGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=BPSbXE2x; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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(localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id C4F1C1FF86; Tue, 5 Feb 2019 19:02:24 +0000 (UTC) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Date: Tue, 5 Feb 2019 19:02:24 +0000 Message-Id: <20190205190224.2198-7-alex.bennee@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190205190224.2198-1-alex.bennee@linaro.org> References: <20190205190224.2198-1-alex.bennee@linaro.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 Subject: [Qemu-devel] [PATCH v2 6/6] tests/tcg/aarch64: userspace system register test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This tests a bunch of registers that the kernel allows userspace to read including the CPUID registers. Signed-off-by: Alex Bennée --- v4 - also test for extra bits that shouldn't be exposed v5 - work around missing HWCAP_CPUID on older compilers - add more registers to test and some aarch32 regs - add more details commentary - fix up the masks (add a helper to help keep track) - add copyright header --- tests/tcg/aarch64/Makefile.target | 4 +- tests/tcg/aarch64/sysregs.c | 172 ++++++++++++++++++++++++++++++ 2 files changed, 175 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/sysregs.c -- 2.20.1 diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 08c45b8470..fb40896e7b 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -7,11 +7,13 @@ VPATH += $(AARCH64_SRC) # we don't build any of the ARM tests AARCH64_TESTS=$(filter-out $(ARM_TESTS), $(TESTS)) -AARCH64_TESTS+=fcvt +AARCH64_TESTS+=fcvt sysregs TESTS:=$(AARCH64_TESTS) fcvt: LDFLAGS+=-lm +sysregs: CFLAGS+=-march=armv8.1-a+sve + run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) diff --git a/tests/tcg/aarch64/sysregs.c b/tests/tcg/aarch64/sysregs.c new file mode 100644 index 0000000000..40cf8d2877 --- /dev/null +++ b/tests/tcg/aarch64/sysregs.c @@ -0,0 +1,172 @@ +/* + * Check emulated system register access for linux-user mode. + * + * See: https://www.kernel.org/doc/Documentation/arm64/cpu-feature-registers.txt + * + * Copyright (c) 2019 Linaro + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include + +#ifndef HWCAP_CPUID +#define HWCAP_CPUID (1 << 11) +#endif + +int failed_bit_count; + +/* Read and print system register `id' value */ +#define get_cpu_reg(id) ({ \ + unsigned long __val = 0xdeadbeef; \ + asm("mrs %0, "#id : "=r" (__val)); \ + printf("%-20s: 0x%016lx\n", #id, __val); \ + __val; \ + }) + +/* As above but also check no bits outside of `mask' are set*/ +#define get_cpu_reg_check_mask(id, mask) ({ \ + unsigned long __cval = get_cpu_reg(id); \ + unsigned long __extra = __cval & ~mask; \ + if (__extra) { \ + printf("%-20s: 0x%016lx\n", " !!extra bits!!", __extra); \ + failed_bit_count++; \ + } \ +}) + +/* As above but check RAZ */ +#define get_cpu_reg_check_zero(id) ({ \ + unsigned long __val = 0xdeadbeef; \ + asm("mrs %0, "#id : "=r" (__val)); \ + if (__val) { \ + printf("%-20s: 0x%016lx (not RAZ!)\n", #id, __val); \ + failed_bit_count++; \ + } \ +}) + +/* Chunk up mask into 63:48, 47:32, 31:16, 15:0 to ease counting */ +#define _m(a, b, c, d) (0x ## a ## b ## c ## d ##ULL) + +bool should_fail; +int should_fail_count; +int should_not_fail_count; +uintptr_t failed_pc[10]; + +void sigill_handler(int signo, siginfo_t *si, void *data) +{ + ucontext_t *uc = (ucontext_t *)data; + + if (should_fail) { + should_fail_count++; + } else { + uintptr_t pc = (uintptr_t) uc->uc_mcontext.pc; + failed_pc[should_not_fail_count++] = pc; + } + uc->uc_mcontext.pc += 4; +} + +int main(void) +{ + struct sigaction sa; + + /* Hook in a SIGILL handler */ + memset(&sa, 0, sizeof(struct sigaction)); + sa.sa_flags = SA_SIGINFO; + sa.sa_sigaction = &sigill_handler; + sigemptyset(&sa.sa_mask); + + if (sigaction(SIGILL, &sa, 0) != 0) { + perror("sigaction"); + return 1; + } + + /* Counter values have been exposed since Linux 4.12 */ + printf("Checking Counter registers\n"); + + get_cpu_reg(ctr_el0); + get_cpu_reg(cntvct_el0); + get_cpu_reg(cntfrq_el0); + + /* HWCAP_CPUID indicates we can read feature registers, since Linux 4.11 */ + if (!(getauxval(AT_HWCAP) & HWCAP_CPUID)) { + printf("CPUID registers unavailable\n"); + return 1; + } else { + printf("Checking CPUID registers\n"); + } + + /* + * Some registers only expose some bits to user-space. Anything + * that is IMPDEF is exported as 0 to user-space. The _mask checks + * assert no extra bits are set. + * + * This check is *not* comprehensive as some fields are set to + * minimum valid fields - for the purposes of this check allowed + * to have non-zero values. + */ + get_cpu_reg_check_mask(id_aa64isar0_el1, _m(00ff,ffff,f0ff,fff0)); + get_cpu_reg_check_mask(id_aa64isar1_el1, _m(0000,00f0,ffff,ffff)); + /* TGran4 & TGran64 as pegged to -1 */ + get_cpu_reg_check_mask(id_aa64mmfr0_el1, _m(0000,0000,ff00,0000)); + get_cpu_reg_check_zero(id_aa64mmfr1_el1); + /* EL1/EL0 reported as AA64 only */ + get_cpu_reg_check_mask(id_aa64pfr0_el1, _m(000f,000f,00ff,0011)); + get_cpu_reg_check_mask(id_aa64pfr1_el1, _m(0000,0000,0000,00f0)); + /* all hidden, DebugVer fixed to 0x6 (ARMv8 debug architecture) */ + get_cpu_reg_check_mask(id_aa64dfr0_el1, _m(0000,0000,0000,0006)); + get_cpu_reg_check_zero(id_aa64dfr1_el1); + get_cpu_reg_check_zero(id_aa64zfr0_el1); + + get_cpu_reg_check_zero(id_aa64afr0_el1); + get_cpu_reg_check_zero(id_aa64afr1_el1); + + get_cpu_reg_check_mask(midr_el1, _m(0000,0000,ffff,ffff)); + /* mpidr sets bit 31, everything else hidden */ + get_cpu_reg_check_mask(mpidr_el1, _m(0000,0000,8000,0000)); + /* REVIDR is all IMPDEF so should be all zeros to user-space */ + get_cpu_reg_check_zero(revidr_el1); + + /* + * There are a block of more registers that are RAZ in the rest of + * the Op0=3, Op1=0, CRn=0, CRm=0,4,5,6,7 space. However for + * brevity we don't check stuff that is currently un-allocated + * here. Feel free to add them ;-) + */ + + printf("Remaining registers should fail\n"); + should_fail = true; + + /* Unexposed register access causes SIGILL */ + get_cpu_reg(id_mmfr0_el1); + get_cpu_reg(id_mmfr1_el1); + get_cpu_reg(id_mmfr2_el1); + get_cpu_reg(id_mmfr3_el1); + + get_cpu_reg(mvfr0_el1); + get_cpu_reg(mvfr1_el1); + + if (should_not_fail_count > 0) { + int i; + for (i = 0; i < should_not_fail_count; i++) { + uintptr_t pc = failed_pc[i]; + uint32_t insn = *(uint32_t *) pc; + printf("insn %#x @ %#lx unexpected FAIL\n", insn, pc); + } + return 1; + } + + if (failed_bit_count > 0) { + printf("Extra information leaked to user-space!\n"); + return 1; + } + + return should_fail_count == 6 ? 0 : 1; +}