From patchwork Wed Aug 17 07:55:14 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 598415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6AC71C25B08 for ; Wed, 17 Aug 2022 08:03:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233371AbiHQIDS (ORCPT ); Wed, 17 Aug 2022 04:03:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52360 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233370AbiHQIDQ (ORCPT ); Wed, 17 Aug 2022 04:03:16 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BC1572721; Wed, 17 Aug 2022 01:03:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660723395; x=1692259395; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=O8uhz61dtWlrbycaCD8YirLLMtkR4Pp1tikfdlsPbqU=; b=FSx6/oFNlo9Ts4VYO2o8lYPVwJBbFnLv6+UG+49fKI8wtOdlBnz7pUac chZ7v0LhrxDQHukbfb52jM9jNbzUECTUaNPAb6yuouCwpkiIkxkOVlt9p p20fQj6+04O2WMwdXlBd866kRtigxnFR6pvD9pd6/ykjv+YrxvrRfF5/S nqAmNbawN2YVqoyestDA8yGNdiju/YpJCFp1xpXYS8KUu/oC2ygUZO9S3 cgthtNu7d8arD5YWYYcrjvb/8u7iABB3AoQNHk/UdhnlcUPev4SlrjodJ R0nZeXd8GUouL2byF1iGjUYFlw7xv4mZinrQSY/PCYYMFcgO3KkEnbs3w Q==; X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="109399553" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Aug 2022 01:03:12 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 17 Aug 2022 01:03:08 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 17 Aug 2022 01:03:03 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , CC: , , , , , , Sergiu Moga Subject: [PATCH 1/5] dt-bindings: mfd: atmel,sama5d2-flexcom: Add SPI child node ref binding Date: Wed, 17 Aug 2022 10:55:14 +0300 Message-ID: <20220817075517.49575-2-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220817075517.49575-1-sergiu.moga@microchip.com> References: <20220817075517.49575-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Another functionality of FLEXCOM is that of SPI. In order for the proper validation of the SPI children nodes through the binding to occur, the proper binding for SPI must be referenced. Signed-off-by: Sergiu Moga --- .../devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index 568da7cb630c..e158af47c326 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -78,10 +78,9 @@ patternProperties: of USART bindings. "^spi@[0-9a-f]+$": - type: object + $ref: ../spi/atmel,at91rm9200-spi.yaml description: - Child node describing SPI. See ../spi/spi_atmel.txt for details - of SPI bindings. + Child node describing SPI. "^i2c@[0-9a-f]+$": $ref: ../i2c/atmel,at91sam-i2c.yaml From patchwork Wed Aug 17 07:55:15 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 598068 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29A7EC32772 for ; Wed, 17 Aug 2022 08:03:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233889AbiHQID2 (ORCPT ); Wed, 17 Aug 2022 04:03:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52532 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233687AbiHQIDT (ORCPT ); Wed, 17 Aug 2022 04:03:19 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F3120E0D0; Wed, 17 Aug 2022 01:03:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660723397; x=1692259397; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fqZU+lOemIX/omn3Ka+GnYknomKYKw8v51G1/iVYc+4=; b=Kp4YolbYW+0PEW8M2wHr7hMLWfS8h6rzvqiCuGMiEdEDJnWVoQMLCFr0 r+1mJId4eoyRYL4XpiR00KN+T3TARVkCiCyuUHgrbR99gML4o+Rvli3/6 8Wwxnj2/JjyvlFPIxYdJ+hcpAhJ77oC072iyvogkamS1f+weDnLqxK7DE 8s9t9jHVAub0QqfSk4z2KboZI98eSd1F4Zndlxjiqq/qgc0lhMHyxJJ8R w0c8eKBMs/78vQ1scY44W2wb7YjW8me5n/760Sq+GnS2w/V8VDsAWcQyb Y5jq+N8n0KExsi11BIRayyLNaEmg06WEv55XDiesXJPdWyN+cBhRFWPu7 Q==; X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="109399576" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Aug 2022 01:03:13 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 17 Aug 2022 01:03:13 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 17 Aug 2022 01:03:08 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , CC: , , , , , , Sergiu Moga Subject: [PATCH 2/5] dt-bindings: mfd: atmel,at91-usart: convert to json-schema Date: Wed, 17 Aug 2022 10:55:15 +0300 Message-ID: <20220817075517.49575-3-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220817075517.49575-1-sergiu.moga@microchip.com> References: <20220817075517.49575-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Convert at91 USART DT Binding for Atmel/Microchip SoCs to json-schema format. Signed-off-by: Sergiu Moga --- .../bindings/mfd/atmel,at91-usart.yaml | 190 ++++++++++++++++++ .../devicetree/bindings/mfd/atmel-usart.txt | 98 --------- 2 files changed, 190 insertions(+), 98 deletions(-) create mode 100644 Documentation/devicetree/bindings/mfd/atmel,at91-usart.yaml delete mode 100644 Documentation/devicetree/bindings/mfd/atmel-usart.txt diff --git a/Documentation/devicetree/bindings/mfd/atmel,at91-usart.yaml b/Documentation/devicetree/bindings/mfd/atmel,at91-usart.yaml new file mode 100644 index 000000000000..cf15d73fa1e8 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/atmel,at91-usart.yaml @@ -0,0 +1,190 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/atmel,at91-usart.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) + +maintainers: + - Richard Genoud + +properties: + compatible: + oneOf: + - const: atmel,at91rm9200-usart + - const: atmel,at91sam9260-usart + - const: microchip,sam9x60-usart + - items: + - const: atmel,at91rm9200-dbgu + - const: atmel,at91rm9200-usart + - items: + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x60-dbgu + - const: microchip,sam9x60-usart + - items: + - const: microchip,sam9x60-usart + - const: atmel,at91sam9260-usart + - items: + - const: microchip,sam9x60-dbgu + - const: microchip,sam9x60-usart + - const: atmel,at91sam9260-dbgu + - const: atmel,at91sam9260-usart + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clock-names: + contains: + const: usart + + clocks: + minItems: 1 + maxItems: 2 + + dmas: + items: + - description: TX DMA Channel + - description: RX DMA Channel + + dma-names: + items: + - const: tx + - const: rx + + atmel,usart-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Must be either 1 for SPI or 0 for USART. + enum: [ 0, 1 ] + +required: + - compatible + - reg + - interrupts + - clock-names + - clocks + +if: + properties: + $nodename: + pattern: "^serial@[0-9a-f]+$" +then: + allOf: + - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/serial/rs485.yaml# + + properties: + atmel,use-dma-rx: + type: boolean + description: use of PDC or DMA for receiving data + + atmel,use-dma-tx: + type: boolean + description: use of PDC or DMA for transmitting data + + atmel,fifo-size: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Maximum number of data the RX and TX FIFOs can store for FIFO + capable USARTS. + enum: [ 16, 32 ] + +else: + if: + properties: + $nodename: + pattern: "^spi@[0-9a-f]+$" + then: + allOf: + - $ref: /schemas/spi/spi-controller.yaml# + + properties: + atmel,usart-mode: + const: 1 + + "#size-cells": + const: 0 + + "#address-cells": + const: 1 + + required: + - atmel,usart-mode + - "#size-cells" + - "#address-cells" + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + + /* use PDC */ + usart0: serial@fff8c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xfff8c000 0x4000>; + interrupts = <7>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; + cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; + dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; + dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; + dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; + rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; + }; + + - | + #include + #include + #include + #include + + /* use DMA */ + usart1: serial@f001c000 { + compatible = "atmel,at91sam9260-usart"; + reg = <0xf001c000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + atmel,use-dma-rx; + atmel,use-dma-tx; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + atmel,fifo-size = <32>; + }; + + - | + #include + #include + #include + #include + + /* SPI mode */ + spi0: spi@f001c000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "atmel,at91sam9260-usart"; + atmel,usart-mode = ; + reg = <0xf001c000 0x100>; + interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; + clocks = <&usart0_clk>; + clock-names = "usart"; + dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, + <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; + dma-names = "tx", "rx"; + cs-gpios = <&pioB 3 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/mfd/atmel-usart.txt b/Documentation/devicetree/bindings/mfd/atmel-usart.txt deleted file mode 100644 index a09133066aff..000000000000 --- a/Documentation/devicetree/bindings/mfd/atmel-usart.txt +++ /dev/null @@ -1,98 +0,0 @@ -* Atmel Universal Synchronous Asynchronous Receiver/Transmitter (USART) - -Required properties for USART: -- compatible: Should be one of the following: - - "atmel,at91rm9200-usart" - - "atmel,at91sam9260-usart" - - "microchip,sam9x60-usart" - - "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart" - - "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart" - - "microchip,sam9x60-dbgu", "microchip,sam9x60-usart" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt -- clock-names: tuple listing input clock names. - Required elements: "usart" -- clocks: phandles to input clocks. - -Required properties for USART in SPI mode: -- #size-cells : Must be <0> -- #address-cells : Must be <1> -- cs-gpios: chipselects (internal cs not supported) -- atmel,usart-mode : Must be (found in dt-bindings/mfd/at91-usart.h) - -Optional properties in serial and SPI mode: -- dma bindings for dma transfer: - - dmas: DMA specifier, consisting of a phandle to DMA controller node, - memory peripheral interface and USART DMA channel ID, FIFO configuration. - The order of DMA channels is fixed. The first DMA channel must be TX - associated channel and the second one must be RX associated channel. - Refer to dma.txt and atmel-dma.txt for details. - - dma-names: "tx" for TX channel. - "rx" for RX channel. - The order of dma-names is also fixed. The first name must be "tx" - and the second one must be "rx" as in the examples below. - -Optional properties in serial mode: -- atmel,use-dma-rx: use of PDC or DMA for receiving data -- atmel,use-dma-tx: use of PDC or DMA for transmitting data -- {rts,cts,dtr,dsr,rng,dcd}-gpios: specify a GPIO for RTS/CTS/DTR/DSR/RI/DCD line respectively. - It will use specified PIO instead of the peripheral function pin for the USART feature. - If unsure, don't specify this property. -- atmel,fifo-size: maximum number of data the RX and TX FIFOs can store for FIFO - capable USARTs. -- rs485-rts-delay, rs485-rx-during-tx, linux,rs485-enabled-at-boot-time: see rs485.txt - - compatible description: -- at91rm9200: legacy USART support -- at91sam9260: generic USART implementation for SAM9 SoCs - -Example: -- use PDC: - usart0: serial@fff8c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xfff8c000 0x4000>; - interrupts = <7>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - rts-gpios = <&pioD 15 GPIO_ACTIVE_LOW>; - cts-gpios = <&pioD 16 GPIO_ACTIVE_LOW>; - dtr-gpios = <&pioD 17 GPIO_ACTIVE_LOW>; - dsr-gpios = <&pioD 18 GPIO_ACTIVE_LOW>; - dcd-gpios = <&pioD 20 GPIO_ACTIVE_LOW>; - rng-gpios = <&pioD 19 GPIO_ACTIVE_LOW>; - }; - -- use DMA: - usart0: serial@f001c000 { - compatible = "atmel,at91sam9260-usart"; - reg = <0xf001c000 0x100>; - interrupts = <12 4 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - atmel,use-dma-rx; - atmel,use-dma-tx; - dmas = <&dma0 2 0x3>, - <&dma0 2 0x204>; - dma-names = "tx", "rx"; - atmel,fifo-size = <32>; - }; - -- SPI mode: - #include - - spi0: spi@f001c000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "atmel,at91rm9200-usart", "atmel,at91sam9260-usart"; - atmel,usart-mode = ; - reg = <0xf001c000 0x100>; - interrupts = <12 IRQ_TYPE_LEVEL_HIGH 5>; - clocks = <&usart0_clk>; - clock-names = "usart"; - dmas = <&dma0 2 AT91_DMA_CFG_PER_ID(3)>, - <&dma0 2 (AT91_DMA_CFG_PER_ID(4) | AT91_DMA_CFG_FIFOCFG_ASAP)>; - dma-names = "tx", "rx"; - cs-gpios = <&pioB 3 0>; - }; From patchwork Wed Aug 17 07:55:16 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 598414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id F27DBC32773 for ; Wed, 17 Aug 2022 08:03:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234076AbiHQIDa (ORCPT ); Wed, 17 Aug 2022 04:03:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52700 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233768AbiHQIDV (ORCPT ); Wed, 17 Aug 2022 04:03:21 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A00FF13E06; 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Wed, 17 Aug 2022 01:03:18 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 17 Aug 2022 01:03:13 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , CC: , , , , , , Sergiu Moga Subject: [PATCH 3/5] dt-bindings: mfd: atmel, sama5d2-flexcom: Add USART child node ref binding Date: Wed, 17 Aug 2022 10:55:16 +0300 Message-ID: <20220817075517.49575-4-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220817075517.49575-1-sergiu.moga@microchip.com> References: <20220817075517.49575-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org FLEXCOM, among other functionalities, has the ability to offer the USART serial communication protocol. To have the FLEXCOM binding properly validate its USART children nodes, we must reference the correct binding. To differentiate between the SPI of FLEXCOM and the SPI of USART in SPI mode, use the clock-names property, since the latter's respective property is supposed to contain the "usart" string. Signed-off-by: Sergiu Moga --- .../bindings/mfd/atmel,sama5d2-flexcom.yaml | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml index e158af47c326..617331a5e66e 100644 --- a/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml +++ b/Documentation/devicetree/bindings/mfd/atmel,sama5d2-flexcom.yaml @@ -72,13 +72,20 @@ properties: patternProperties: "^serial@[0-9a-f]+$": - type: object + $ref: atmel,at91-usart.yaml description: - Child node describing USART. See atmel-usart.txt for details - of USART bindings. + Child node describing USART. "^spi@[0-9a-f]+$": - $ref: ../spi/atmel,at91rm9200-spi.yaml + if: + properties: + clock-names: + contains: + const: usart + then: + $ref: atmel,at91-usart.yaml + else: + $ref: ../spi/atmel,at91rm9200-spi.yaml description: Child node describing SPI. From patchwork Wed Aug 17 07:55:17 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 598413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96F88C32789 for ; Wed, 17 Aug 2022 08:03:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234342AbiHQIDy (ORCPT ); Wed, 17 Aug 2022 04:03:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53096 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233927AbiHQIDq (ORCPT ); Wed, 17 Aug 2022 04:03:46 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 456EA3CBD2; Wed, 17 Aug 2022 01:03:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660723413; x=1692259413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=vcTzOtyWjobS5W/aThT1AJ1c0537v1+hlKeSaS5KGas=; b=Fu1ZdGK6Z9My3yY8fqVcsHXz8FUsGzEy+o0EADakMizw43iGU/v6nKrf qUoCXJQpT0Q/rWkL7owEtBpjawIyv3+dO3u53jbtApf/MP1+R+oCLsnEB Qb6tc0/BH0W+2hUQaSP3o5Bfdfx/6lKFTee7l06ZRU0mGOZM4jW/5nwX+ ra4ypcY0YOGyfnKPeoVWQwhTDXFKXYZ9HSJIYNc2tvTktjsaKFQoN3TSw OoXm06sqahpQY4vcQuGJ4D/ehZ7DhWAKNJkCmUFtgFdTPao9IOIe85/l2 7v/lXdql3AuJuSkFa3n48XQiVPuHfEPJeLyznUntQFIqS15fT3h1kvlLF Q==; X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="176721251" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa3.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Aug 2022 01:03:32 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 17 Aug 2022 01:03:23 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 17 Aug 2022 01:03:18 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , CC: , , , , , , Sergiu Moga Subject: [PATCH 4/5] clk: at91: sama5d2: Add Generic Clocks for UART/USART Date: Wed, 17 Aug 2022 10:55:17 +0300 Message-ID: <20220817075517.49575-5-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220817075517.49575-1-sergiu.moga@microchip.com> References: <20220817075517.49575-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Add the generic clocks for UART/USART in the sama5d2 driver to allow them to be registered in the Common Clock Framework. Signed-off-by: Sergiu Moga --- drivers/clk/at91/sama5d2.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/clk/at91/sama5d2.c b/drivers/clk/at91/sama5d2.c index cfd0f5e23b99..84156dc52bff 100644 --- a/drivers/clk/at91/sama5d2.c +++ b/drivers/clk/at91/sama5d2.c @@ -120,6 +120,16 @@ static const struct { struct clk_range r; int chg_pid; } sama5d2_gck[] = { + { .n = "flx0_gclk", .id = 19, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx1_gclk", .id = 20, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx2_gclk", .id = 21, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx3_gclk", .id = 22, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "flx4_gclk", .id = 23, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart0_gclk", .id = 24, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart1_gclk", .id = 25, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart2_gclk", .id = 26, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart3_gclk", .id = 27, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, + { .n = "uart4_gclk", .id = 28, .chg_pid = INT_MIN, .r = { .min = 0, .max = 27666666 }, }, { .n = "sdmmc0_gclk", .id = 31, .chg_pid = INT_MIN, }, { .n = "sdmmc1_gclk", .id = 32, .chg_pid = INT_MIN, }, { .n = "tcb0_gclk", .id = 35, .chg_pid = INT_MIN, .r = { .min = 0, .max = 83000000 }, }, From patchwork Wed Aug 17 07:55:18 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sergiu Moga X-Patchwork-Id: 598067 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 12C6BC25B08 for ; Wed, 17 Aug 2022 08:03:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234266AbiHQIDx (ORCPT ); Wed, 17 Aug 2022 04:03:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:53942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233768AbiHQIDo (ORCPT ); Wed, 17 Aug 2022 04:03:44 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DB12239B85; Wed, 17 Aug 2022 01:03:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1660723413; x=1692259413; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=2Pv7hkZ6hWMmBycZ4+WnhfRT5RtAh4O9ymOlESkLyAQ=; b=el0TvXszO1vTR/oJ4s3T7tAyOfh1G7cxN23l/qhLRconxkhmU+GjsnqG r10We7N5ZkQCB3Blm7q5LlEaeacyDSvP2nP+zIA5nXBw83oX9HbkGBrdc mal3sUly/xz4ef14ry4+aeN5JoXS2TGOCXQ0QeOlbqLPTW221GzBQ3UoT Ymfr6jYb5ouY1xU2IoEue8bNYJMqr9Nw9Hh5b32iRDT+adcm55MzE3Mma V7zDyixCVn3i192NO1oi2h/sOWti5ePFc15793g+bXlp1S6Y6i3ZiKBo8 rM97qwGtQ3dRlWnDlmGNmzWGNeaoGsYxiBxRXxxhYFQ4QiYOR19taKWiM A==; X-IronPort-AV: E=Sophos;i="5.93,242,1654585200"; d="scan'208";a="109399692" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 17 Aug 2022 01:03:31 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Wed, 17 Aug 2022 01:03:27 -0700 Received: from ROB-ULT-M68701.microchip.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Wed, 17 Aug 2022 01:03:23 -0700 From: Sergiu Moga To: , , , , , , , , , , , , , CC: , , , , , , Sergiu Moga Subject: [PATCH 5/5] tty: serial: atmel: Make the driver aware of the existence of GCLK Date: Wed, 17 Aug 2022 10:55:18 +0300 Message-ID: <20220817075517.49575-6-sergiu.moga@microchip.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220817075517.49575-1-sergiu.moga@microchip.com> References: <20220817075517.49575-1-sergiu.moga@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org Previously, the atmel serial driver did not take into account the possibility of using the more customizable generic clock as its baudrate generator. Unless there is a Fractional Part available to increase accuracy, there is a high chance that we may be able to generate a baudrate closer to the desired one by using the GCLK as the clock source. Now, depending on the error rate between the desired baudrate and the actual baudrate, the serial driver will fallback on the generic clock. The generic clock must be provided in the DT node of the serial that may need a more flexible clock source. Signed-off-by: Sergiu Moga --- drivers/tty/serial/atmel_serial.c | 52 ++++++++++++++++++++++++++++++- drivers/tty/serial/atmel_serial.h | 1 + 2 files changed, 52 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/atmel_serial.c b/drivers/tty/serial/atmel_serial.c index 30ba9eef7b39..0a0b46ee0955 100644 --- a/drivers/tty/serial/atmel_serial.c +++ b/drivers/tty/serial/atmel_serial.c @@ -15,6 +15,7 @@ #include #include #include +#include #include #include #include @@ -77,6 +78,8 @@ static void atmel_stop_rx(struct uart_port *port); #endif #define ATMEL_ISR_PASS_LIMIT 256 +#define ERROR_RATE(desired_value, actual_value) \ + ((int)(100 - ((desired_value) * 100) / (actual_value))) struct atmel_dma_buffer { unsigned char *buf; @@ -110,6 +113,7 @@ struct atmel_uart_char { struct atmel_uart_port { struct uart_port uart; /* uart */ struct clk *clk; /* uart clock */ + struct clk *gclk; /* uart generic clock */ int may_wakeup; /* cached value of device_may_wakeup for times we need to disable it */ u32 backup_imr; /* IMR saved during suspend */ int break_active; /* break being received */ @@ -2115,6 +2119,8 @@ static void atmel_serial_pm(struct uart_port *port, unsigned int state, * This is called on uart_close() or a suspend event. */ clk_disable_unprepare(atmel_port->clk); + if (atmel_port->gclk && __clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); break; default: dev_err(port->dev, "atmel_serial: unknown pm %d\n", state); @@ -2129,7 +2135,8 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, { struct atmel_uart_port *atmel_port = to_atmel_uart_port(port); unsigned long flags; - unsigned int old_mode, mode, imr, quot, baud, div, cd, fp = 0; + unsigned int old_mode, mode, imr, quot, div, cd, fp = 0; + unsigned int baud, actual_baud, gclk_rate; /* save the current mode register */ mode = old_mode = atmel_uart_readl(port, ATMEL_US_MR); @@ -2288,6 +2295,37 @@ static void atmel_set_termios(struct uart_port *port, struct ktermios *termios, cd /= 8; mode |= ATMEL_US_USCLKS_MCK_DIV8; } + + /* + * If there is no Fractional Part, there is a high chance that + * we may be able to generate a baudrate closer to the desired one + * if we use the GCLK as the clock source driving the baudrate + * generator. + */ + if (!fp && atmel_port->gclk) { + if (__clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); + clk_set_rate(atmel_port->gclk, 16 * baud); + gclk_rate = clk_get_rate(atmel_port->gclk); + actual_baud = clk_get_rate(atmel_port->clk) / (16 * cd); + if (abs(ERROR_RATE(baud, actual_baud)) > + abs(ERROR_RATE(baud, gclk_rate / 16))) { + mode |= ATMEL_US_GCLK; + + /* + * Set the Clock Divisor for GCLK to 1. + * Since we were able to generate the smallest + * multiple of the desired baudrate times 16, + * then we surely can generate a bigger multiple + * with the exact error rate for an equally increased + * CD. Thus no need to take into account + * a higher value for CD. + */ + cd = 1; + clk_prepare_enable(atmel_port->gclk); + } + } + quot = cd | fp << ATMEL_US_FP_OFFSET; if (!(port->iso7816.flags & SER_ISO7816_ENABLED)) @@ -2883,6 +2921,16 @@ static int atmel_serial_probe(struct platform_device *pdev) if (ret) goto err; + atmel_port->gclk = devm_clk_get_optional(&pdev->dev, "gclk"); + if (atmel_port->gclk) { + ret = clk_prepare_enable(atmel_port->gclk); + if (ret) { + atmel_port->gclk = NULL; + return ret; + } + clk_disable_unprepare(atmel_port->gclk); + } + ret = atmel_init_port(atmel_port, pdev); if (ret) goto err_clk_disable_unprepare; @@ -2929,6 +2977,8 @@ static int atmel_serial_probe(struct platform_device *pdev) * is used */ clk_disable_unprepare(atmel_port->clk); + if (atmel_port->gclk && __clk_is_enabled(atmel_port->gclk)) + clk_disable_unprepare(atmel_port->gclk); return 0; diff --git a/drivers/tty/serial/atmel_serial.h b/drivers/tty/serial/atmel_serial.h index 0d8a0f9cc5c3..fb718972f81a 100644 --- a/drivers/tty/serial/atmel_serial.h +++ b/drivers/tty/serial/atmel_serial.h @@ -63,6 +63,7 @@ #define ATMEL_US_PAR_MARK (3 << 9) #define ATMEL_US_PAR_NONE (4 << 9) #define ATMEL_US_PAR_MULTI_DROP (6 << 9) +#define ATMEL_US_GCLK BIT(12) #define ATMEL_US_NBSTOP GENMASK(13, 12) /* Number of Stop Bits */ #define ATMEL_US_NBSTOP_1 (0 << 12) #define ATMEL_US_NBSTOP_1_5 (1 << 12)