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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a54d610e5fsm1391992wmq.26.2022.08.17.01.08.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 01:08:35 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v9,1/7] thermal: mediatek: Relocate driver to mediatek folder Date: Wed, 17 Aug 2022 10:07:51 +0200 Message-Id: <20220817080757.352021-2-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220817080757.352021-1-bchihi@baylibre.com> References: <20220817080757.352021-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Michael Kao Add MediaTek proprietary folder to upstream more thermal zone and cooler drivers, relocate the original thermal controller driver to it, and rename it as "auxadc_thermal.c" to show its purpose more clearly. Signed-off-by: Michael Kao Co-developed-by: Ben Tseng Signed-off-by: Ben Tseng Co-developed-by: Balsam CHIHI Signed-off-by: Balsam CHIHI --- drivers/thermal/Kconfig | 14 ++++-------- drivers/thermal/Makefile | 2 +- drivers/thermal/mediatek/Kconfig | 22 +++++++++++++++++++ drivers/thermal/mediatek/Makefile | 1 + .../auxadc_thermal.c} | 2 +- 5 files changed, 29 insertions(+), 12 deletions(-) create mode 100644 drivers/thermal/mediatek/Kconfig create mode 100644 drivers/thermal/mediatek/Makefile rename drivers/thermal/{mtk_thermal.c => mediatek/auxadc_thermal.c} (99%) diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig index e052dae614eb..d35f63daca3b 100644 --- a/drivers/thermal/Kconfig +++ b/drivers/thermal/Kconfig @@ -412,16 +412,10 @@ config DA9062_THERMAL zone. Compatible with the DA9062 and DA9061 PMICs. -config MTK_THERMAL - tristate "Temperature sensor driver for mediatek SoCs" - depends on ARCH_MEDIATEK || COMPILE_TEST - depends on HAS_IOMEM - depends on NVMEM || NVMEM=n - depends on RESET_CONTROLLER - default y - help - Enable this option if you want to have support for thermal management - controller present in Mediatek SoCs +menu "Mediatek thermal drivers" +depends on ARCH_MEDIATEK || COMPILE_TEST +source "drivers/thermal/mediatek/Kconfig" +endmenu config AMLOGIC_THERMAL tristate "Amlogic Thermal Support" diff --git a/drivers/thermal/Makefile b/drivers/thermal/Makefile index def8e1a0399c..f7daeb8056c4 100644 --- a/drivers/thermal/Makefile +++ b/drivers/thermal/Makefile @@ -55,7 +55,7 @@ obj-y += st/ obj-$(CONFIG_QCOM_TSENS) += qcom/ obj-y += tegra/ obj-$(CONFIG_HISI_THERMAL) += hisi_thermal.o -obj-$(CONFIG_MTK_THERMAL) += mtk_thermal.o +obj-y += mediatek/ obj-$(CONFIG_GENERIC_ADC_THERMAL) += thermal-generic-adc.o obj-$(CONFIG_UNIPHIER_THERMAL) += uniphier_thermal.o obj-$(CONFIG_AMLOGIC_THERMAL) += amlogic_thermal.o diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kconfig new file mode 100644 index 000000000000..8ff32370b591 --- /dev/null +++ b/drivers/thermal/mediatek/Kconfig @@ -0,0 +1,22 @@ +config MTK_THERMAL + tristate "MediaTek thermal drivers" + depends on THERMAL_OF + help + This is the option for MediaTek thermal software solutions. + Please enable corresponding options to get temperature + information from thermal sensors or turn on throttle + mechaisms for thermal mitigation. + +if MTK_THERMAL + +config MTK_SOC_THERMAL + tristate "AUXADC temperature sensor driver for MediaTek SoCs" + depends on HAS_IOMEM + depends on NVMEM + depends on RESET_CONTROLLER + help + Enable this option if you want to get SoC temperature + information for MediaTek platforms. This driver configures + thermal controllers to collect temperature via AUXADC interface. + +endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/Makefile new file mode 100644 index 000000000000..bec325f06a46 --- /dev/null +++ b/drivers/thermal/mediatek/Makefile @@ -0,0 +1 @@ +obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mediatek/auxadc_thermal.c similarity index 99% rename from drivers/thermal/mtk_thermal.c rename to drivers/thermal/mediatek/auxadc_thermal.c index ede94eadddda..60924f8f98e9 100644 --- a/drivers/thermal/mtk_thermal.c +++ b/drivers/thermal/mediatek/auxadc_thermal.c @@ -23,7 +23,7 @@ #include #include -#include "thermal_hwmon.h" +#include "../thermal_hwmon.h" /* AUXADC Registers */ #define AUXADC_CON1_SET_V 0x008 From patchwork Wed Aug 17 08:07:52 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balsam CHIHI X-Patchwork-Id: 598396 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8AAC5C32773 for ; Wed, 17 Aug 2022 08:08:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229658AbiHQIIr (ORCPT ); Wed, 17 Aug 2022 04:08:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230297AbiHQIIp (ORCPT ); Wed, 17 Aug 2022 04:08:45 -0400 Received: from mail-wr1-x42f.google.com (mail-wr1-x42f.google.com [IPv6:2a00:1450:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4097B4D4FF for ; Wed, 17 Aug 2022 01:08:39 -0700 (PDT) Received: by mail-wr1-x42f.google.com with SMTP id n4so15266124wrp.10 for ; Wed, 17 Aug 2022 01:08:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=VWXG1e9/DRSLvY5QEUtPtlLQfPC+KRrU45gKoV7pXAc=; b=NmM9L1PaffPpCsm/C4/QFhphpWYhLPEMeeIXMsHVx+Gx6cwHyUbPB+W5EQHS5EJ82y X/wINA6ev0mpTwDayZwDE6yvvRlTgM1lbaWx8aHtMnHbFEKSMDWQ0ReaD4GMoRNh4naT 3WNlCO7ZqEOehjoUs2RHdyj/jHRF/5wCPuOum7W8n+mwDwGQTsAYo/4WyPgBN1DlHohP JPqcaJ+/Gt3ntySPDCiXHkJiMCsSwaoblu88SOG4VmJn4Kgr/ZXn0XOoMCS3p60ogBnl D5LL0QVWUWn/cKMzPW/Oj+PqUtsyrgBgf/fqpBOSX783sp9tUInUxHELxusOUgt7etgL BoYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=VWXG1e9/DRSLvY5QEUtPtlLQfPC+KRrU45gKoV7pXAc=; b=Up+6hejbOfHQAB1Et/w2e05c8a4qomerGVLokwZlwnvEFP+eXPY+Qatus1jT8Oj//j 7o1hkGtZ02ATgqPdw/YqWLjDOwueXJ4ydg9lHf/D6DcK3ZFyKliZ/AoqhNPFIiiiiA49 fjBLrz35JpNejBZFq4V0ummiIc42glXoupadZd8kSKE8JDsB2gVxALXgllKFyOMEsyDK ahjgWS9sBodVNQcmD59Wy0rgps5D0ZJ7k4enYznRB5XDXpvGCNZcxmJd9dUh+pH/Bd0K HqSo1iFCzBmdy/zkE3aq51d5FoMovZWkO9NBf0EgEOsYi6yekgrumctNuqC113hNztUw Y+gQ== X-Gm-Message-State: ACgBeo2ORaBA2Xvdr1FJkphQw/UhdAhYPUEPTvEsS87gLd+4mLfnl6Me D48/VWaUopmzpQLUvYsSXpnNdQ== X-Google-Smtp-Source: AA6agR7KY4TOelp2cDbEEwT9aNbQBHNA36aSrdAhKK+734vr4aWgVXADl++KkjH3cOTyGim9KWp26Q== X-Received: by 2002:adf:e44b:0:b0:220:5bc5:e942 with SMTP id t11-20020adfe44b000000b002205bc5e942mr13366911wrm.179.1660723717790; Wed, 17 Aug 2022 01:08:37 -0700 (PDT) Received: from Balsam-ThinkPad-T480.civfrance.com (58.188.158.77.rev.sfr.net. [77.158.188.58]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a54d610e5fsm1391992wmq.26.2022.08.17.01.08.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 01:08:37 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v9, 2/7] dt-bindings: thermal: Add dt-binding document for LVTS thermal controllers Date: Wed, 17 Aug 2022 10:07:52 +0200 Message-Id: <20220817080757.352021-3-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220817080757.352021-1-bchihi@baylibre.com> References: <20220817080757.352021-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Alexandre Bailon Add dt-binding document for mt8192 and mt8195 LVTS thermal controllers. Signed-off-by: Alexandre Bailon Co-developed-by: Balsam CHIHI Signed-off-by: Balsam CHIHI --- .../thermal/mediatek,lvts-thermal.yaml | 152 ++++++++++++++++++ 1 file changed, 152 insertions(+) create mode 100644 Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml diff --git a/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml new file mode 100644 index 000000000000..31d9e220513a --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/mediatek,lvts-thermal.yaml @@ -0,0 +1,152 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/mediatek,lvts-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek SoC LVTS thermal controller + +maintainers: + - Yu-Chia Chang + - Ben Tseng + +description: | + LVTS (Low Voltage Thermal Sensor). + The architecture will be first used on mt8192 and mt8195. + +properties: + compatible: + enum: + - mediatek,mt8192-lvts-ap + - mediatek,mt8192-lvts-mcu + - mediatek,mt8195-lvts-ap + - mediatek,mt8195-lvts-mcu + + "#thermal-sensor-cells": + const: 1 + + reg: + maxItems: 1 + description: LVTS instance registers. + + interrupts: + maxItems: 1 + description: LVTS instance interrupts. + + clocks: + maxItems: 1 + description: LVTS instance clock. + + resets: + maxItems: 1 + description: | + LVTS instance SW reset for HW AP/MCU domain to clean temporary data + on HW initialization/resume. + + nvmem-cells: + minItems: 1 + maxItems: 2 + description: Calibration efuse data for LVTS + + nvmem-cell-names: + minItems: 1 + maxItems: 2 + description: Calibration efuse cell names for LVTS + +allOf: + - $ref: thermal-sensor.yaml# + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8192-lvts-ap + - mediatek,mt8192-lvts-mcu + then: + properties: + nvmem-cells: + items: + - description: Calibration efuse data for LVTS + + nvmem-cell-names: + items: + - const: lvts_calib_data1 + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8195-lvts-ap + - mediatek,mt8195-lvts-mcu + then: + properties: + nvmem-cells: + items: + - description: Calibration efuse data 1 for LVTS + - description: Calibration efuse data 2 for LVTS + + nvmem-cell-names: + items: + - const: lvts_calib_data1 + - const: lvts_calib_data2 + +required: + - compatible + - '#thermal-sensor-cells' + - reg + - interrupts + - clocks + - resets + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +examples: + - | + #include + #include + #include + + soc { + #address-cells = <2>; + #size-cells = <2>; + + lvts_ap: thermal-sensor@1100b000 { + compatible = "mediatek,mt8192-lvts-ap"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells = <&lvts_e_data1>; + nvmem-cell-names = "lvts_calib_data1"; + }; + + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8192-lvts-mcu"; + #thermal-sensor-cells = <1>; + reg = <0 0x11278000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_e_data1>; + nvmem-cell-names = "lvts_calib_data1"; + }; + }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 0>; + }; + + vpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 0>; + }; + }; From patchwork Wed Aug 17 08:07:53 2022 Content-Type: text/plain; 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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a54d610e5fsm1391992wmq.26.2022.08.17.01.08.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 01:08:39 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v9,3/7] arm64: dts: mt8192: Add thermal zones and thermal nodes Date: Wed, 17 Aug 2022 10:07:53 +0200 Message-Id: <20220817080757.352021-4-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220817080757.352021-1-bchihi@baylibre.com> References: <20220817080757.352021-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Balsam CHIHI Add thermal zones and thermal nodes for the mt8192. Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8192.dtsi | 111 +++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index cbae5a5ee4a0..59ef4da06a70 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -12,6 +12,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8192"; @@ -599,6 +600,28 @@ spi0: spi@1100a000 { status = "disabled"; }; + lvts_ap: thermal-sensor@1100b000 { + compatible = "mediatek,mt8192-lvts-ap"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + resets = <&infracfg MT8192_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells = <&lvts_e_data1>; + nvmem-cell-names = "lvts_calib_data1"; + }; + + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8192-lvts-mcu"; + #thermal-sensor-cells = <1>; + reg = <0 0x11278000 0 0x1000>; + interrupts = ; + clocks = <&infracfg CLK_INFRA_THERM>; + resets = <&infracfg MT8192_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_e_data1>; + nvmem-cell-names = "lvts_calib_data1"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8192-spi", "mediatek,mt6765-spi"; @@ -1457,4 +1480,92 @@ larb2: larb@1f002000 { power-domains = <&spm MT8192_POWER_DOMAIN_MDP>; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 0>; + }; + cpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 1>; + }; + cpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 2>; + }; + cpu3-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 3>; + }; + cpu4-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 4>; + }; + cpu5-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 5>; + }; + cpu6-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 6>; + }; + cpu7-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 7>; + }; + vpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 0>; + }; + vpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 1>; + }; + gpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 2>; + }; + gpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 3>; + }; + infra-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 4>; + }; + cam-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 5>; + }; + md1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 6>; + }; + md2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 7>; + }; + md3-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 8>; + }; + }; }; From patchwork Wed Aug 17 08:07:54 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balsam CHIHI X-Patchwork-Id: 598394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 83289C3F6B0 for ; Wed, 17 Aug 2022 08:08:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233969AbiHQII4 (ORCPT ); Wed, 17 Aug 2022 04:08:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58346 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233482AbiHQIIy (ORCPT ); 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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a54d610e5fsm1391992wmq.26.2022.08.17.01.08.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 01:08:48 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v9, 4/7] thermal: mediatek: Add LVTS driver for mt8192 thermal zones Date: Wed, 17 Aug 2022 10:07:54 +0200 Message-Id: <20220817080757.352021-5-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220817080757.352021-1-bchihi@baylibre.com> References: <20220817080757.352021-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Michael Kao Add LVTS v4 (Low Voltage Thermal Sensor) driver to report junction temperatures in MediaTek SoC mt8192 and register the maximum temperature of sensors and each sensor as a thermal zone. Co-developed-by: Yu-Chia Chang Signed-off-by: Yu-Chia Chang Signed-off-by: Michael Kao Co-developed-by: Ben Tseng Signed-off-by: Ben Tseng Co-developed-by: Alexandre Bailon Signed-off-by: Alexandre Bailon Co-developed-by: Balsam CHIHI Signed-off-by: Balsam CHIHI --- drivers/thermal/mediatek/Kconfig | 21 + drivers/thermal/mediatek/Makefile | 2 + drivers/thermal/mediatek/lvts_thermal.c | 861 ++++++++++++++++++++++++ drivers/thermal/mediatek/lvts_thermal.h | 385 +++++++++++ drivers/thermal/mediatek/lvts_v4.c | 249 +++++++ 5 files changed, 1518 insertions(+) create mode 100644 drivers/thermal/mediatek/lvts_thermal.c create mode 100644 drivers/thermal/mediatek/lvts_thermal.h create mode 100644 drivers/thermal/mediatek/lvts_v4.c diff --git a/drivers/thermal/mediatek/Kconfig b/drivers/thermal/mediatek/Kconfig index 8ff32370b591..02a1b3b42ce0 100644 --- a/drivers/thermal/mediatek/Kconfig +++ b/drivers/thermal/mediatek/Kconfig @@ -19,4 +19,25 @@ config MTK_SOC_THERMAL information for MediaTek platforms. This driver configures thermal controllers to collect temperature via AUXADC interface. +config MTK_LVTS_THERMAL + tristate "LVTS temperature sensor driver for MediaTek SoCs" + depends on HAS_IOMEM + depends on NVMEM + depends on RESET_CONTROLLER + help + Enable this option if you want to get SoC temperature information + for MediaTek platforms. This driver configures LVTS + (Low Voltage Thermal Sensor) thermal controllers to collect + temperatures via ASIF (Analog Serial Interface). + +if MTK_LVTS_THERMAL + +config MTK_LVTS_V4 + tristate "LVTS v4 driver for MediaTek SoCs" + help + Enable this option if you want to get temperature information + for LVTS v4 SoCs. + +endif + endif diff --git a/drivers/thermal/mediatek/Makefile b/drivers/thermal/mediatek/Makefile index bec325f06a46..e4e62d726776 100644 --- a/drivers/thermal/mediatek/Makefile +++ b/drivers/thermal/mediatek/Makefile @@ -1 +1,3 @@ obj-$(CONFIG_MTK_SOC_THERMAL) += auxadc_thermal.o +obj-$(CONFIG_MTK_LVTS_THERMAL) += lvts_thermal.o +obj-$(CONFIG_MTK_LVTS_V4) += lvts_v4.o diff --git a/drivers/thermal/mediatek/lvts_thermal.c b/drivers/thermal/mediatek/lvts_thermal.c new file mode 100644 index 000000000000..a1681b914c69 --- /dev/null +++ b/drivers/thermal/mediatek/lvts_thermal.c @@ -0,0 +1,861 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "lvts_thermal.h" + +static int lvts_raw_to_temp(struct lvts_formula_coeff *co, unsigned int msr_raw) +{ + /* This function returns degree mC */ + + int temp; + + temp = (co->a * ((unsigned long long)msr_raw)) >> 14; + temp = temp + co->golden_temp * 500 + co->b; + + return temp; +} + +static unsigned int lvts_temp_to_raw(struct lvts_formula_coeff *co, int temp) +{ + unsigned int msr_raw; + + msr_raw = div_s64((s64)((co->golden_temp * 500 + co->b - temp)) << 14, (-1 * co->a)); + + return msr_raw; +} + +static int soc_temp_lvts_read_temp(void *data, int *temperature) +{ + struct soc_temp_tz *lvts_tz = (struct soc_temp_tz *)data; + struct lvts_data *lvts_data = lvts_tz->lvts_data; + struct device *dev = lvts_data->dev; + unsigned int msr_raw; + + msr_raw = readl(lvts_data->reg[lvts_tz->id]) & MRS_RAW_MASK; + if (msr_raw == 0) { + /* Prevents a false critical temperature trap */ + *temperature = 0; + dev_dbg(dev, "LVTS not yet ready\n"); + + } else + *temperature = lvts_raw_to_temp(&lvts_data->coeff, msr_raw); + + return 0; +} + +static const struct thermal_zone_of_device_ops soc_temp_lvts_ops = { + .get_temp = soc_temp_lvts_read_temp, +}; + +static void lvts_write_device(struct lvts_data *lvts_data, unsigned int data, int tc_id) +{ + void __iomem *base = GET_BASE_ADDR(lvts_data, tc_id); + + writel(DEVICE_WRITE(lvts_data) | data, LVTS_CONFIG_0 + base); + usleep_range(20, 30); +} + +static unsigned int lvts_read_device(struct lvts_data *lvts_data, unsigned int reg_idx, int tc_id) +{ + void __iomem *base = GET_BASE_ADDR(lvts_data, tc_id); + struct device *dev = lvts_data->dev; + unsigned int data; + int ret; + + writel(READ_DEVICE_REG(lvts_data, reg_idx), LVTS_CONFIG_0 + base); + usleep_range(20, 30); + ret = readl_poll_timeout(LVTS_CONFIG_0 + base, data, !(data & DEVICE_ACCESS_STARTUS), 2, 200); + if (ret) + dev_err(dev, "LVTS_TC_%d DEVICE_ACCESS_START is not ready\n", tc_id); + + data = readl(LVTSRDATA0_0 + base); + + return data; +} + +static const char * const lvts_error_table[] = { + "Idle", + "Write transaction", + "Waiting for read after write", + "Disable continue fetching on device", + "Read transaction", + "Set device special register for voltage threshold", + "Set TSMCU number for fetch" +}; + +static void wait_all_tc_sensing_point_idle(struct lvts_data *lvts_data) +{ + void __iomem *base; + struct device *dev = lvts_data->dev; + unsigned int error_code, is_error; + int i, cnt, ret; + + for (cnt = 0; cnt < 2; cnt++) { + is_error = 0; + + for (i = 0; i < lvts_data->num_tc; i++) { + base = GET_BASE_ADDR(lvts_data, i); + ret = readl_poll_timeout(LVTSMSRCTL1_0 + base, error_code, + !(error_code & ALL_TC_SENSING_POINT_STATUS), 2, 200); + error_code = ((error_code & TC_SENSING_POINT_10) >> 8) + + ((error_code & TC_SENSING_POINT_7) >> 6) + (error_code & TC_SENSING_POINT_0); + if (ret) + dev_err(dev, "LVTS_TC_%d Error Code : %s\n", i, lvts_error_table[error_code]); + + if (error_code != 0) + is_error = 1; + } + + if (is_error == 0) + break; + } +} + +static void lvts_reset(struct lvts_data *lvts_data) +{ + if (lvts_data->reset) + reset_control_assert(lvts_data->reset); + + if (lvts_data->reset) + reset_control_deassert(lvts_data->reset); +} + +static void device_identification(struct lvts_data *lvts_data) +{ + void __iomem *base; + struct device *dev = lvts_data->dev; + unsigned int i, data; + + for (i = 0; i < lvts_data->num_tc; i++) { + base = GET_BASE_ADDR(lvts_data, i); + writel(ENABLE_LVTS_CTRL_CLK, LVTSCLKEN_0 + base); + lvts_write_device(lvts_data, RESET_ALL_DEVICES(lvts_data), i); + writel(READ_BACK_DEVICE_ID(lvts_data), LVTS_CONFIG_0 + base); + usleep_range(20, 30); + /* Check LVTS device ID */ + data = (readl(LVTS_ID_0 + base) & DEVICE_REG_DATA); + if (data != (lvts_data->tc->dev_id + i)) + dev_err(dev, "LVTS_TC_%d, Device ID should be 0x%x, but 0x%x\n", + i, (lvts_data->tc->dev_id + i), data); + } +} + +static void disable_all_sensing_points(struct lvts_data *lvts_data) +{ + void __iomem *base; + unsigned int i; + + for (i = 0; i < lvts_data->num_tc; i++) { + base = GET_BASE_ADDR(lvts_data, i); + writel(DISABLE_SENSING_POINT, LVTSMONCTL0_0 + base); + } +} + +static void enable_all_sensing_points(struct lvts_data *lvts_data) +{ + void __iomem *base; + struct device *dev = lvts_data->dev; + const struct lvts_tc_settings *tc = lvts_data->tc; + unsigned int i, num; + + for (i = 0; i < lvts_data->num_tc; i++) { + base = GET_BASE_ADDR(lvts_data, i); + num = tc[i].num_sensor; + if (num > ALL_SENSING_POINTS) { + dev_err(dev, "LVTS_TC_%d, illegal number of sensors: %d\n", i, tc[i].num_sensor); + + continue; + } + + if ((tc[i].ts_offset == 1) && (num == 1)) + writel(LVTS_SINGLE_SENSE | (0x1 << tc[i].ts_offset), LVTSMONCTL0_0 + base); + + else + writel(ENABLE_SENSING_POINT(num), LVTSMONCTL0_0 + base); + } +} + +static void set_polling_speed(struct lvts_data *lvts_data, int tc_id) +{ + void __iomem *base = GET_BASE_ADDR(lvts_data, tc_id); + struct device *dev = lvts_data->dev; + const struct lvts_tc_settings *tc = lvts_data->tc; + unsigned int lvts_mon_ctl_1, lvts_mon_ctl_2; + + lvts_mon_ctl_1 = ((tc[tc_id].tc_speed->group_interval_delay << 20) & + GROUP_INTERVAL_DELAY_MASK) | (tc[tc_id].tc_speed->period_unit & PERIOD_UNIT_MASK); + lvts_mon_ctl_2 = ((tc[tc_id].tc_speed->filter_interval_delay << 16) & + FILTER_INTERVAL_DELAY_MASK) | (tc[tc_id].tc_speed->sensor_interval_delay & + SENSOR_INTERVAL_DELAY_MASK); + /* + * Clock source of LVTS thermal controller is 26MHz. + * Period unit is a base for all interval delays + * All interval delays must multiply it to convert a setting to time. + * Filter interval delay is a delay between two samples of the same sensor + * Sensor interval delay is a delay between two samples of differnet sensors + * Group interval delay is a delay between different rounds. + * For example: + * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, + * and two sensors, TS1 and TS2, are in a LVTS thermal controller + * and then + * Period unit = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us + * Filter interval delay = 1 * Period unit = 118.149us + * Sensor interval delay = 2 * Period unit = 236.298us + * Group interval delay = 1 * Period unit = 118.149us + * + * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... + * <--> Filter interval delay + * <--> Sensor interval delay + * <--> Group interval delay + */ + writel(lvts_mon_ctl_1, LVTSMONCTL1_0 + base); + writel(lvts_mon_ctl_2, LVTSMONCTL2_0 + base); + dev_dbg(dev, "lvts_tc_%d, LVTSMONCTL1_0= 0x%x, LVTSMONCTL2_0= 0x%x\n", + tc_id, readl(LVTSMONCTL1_0 + base), readl(LVTSMONCTL2_0 + base)); +} + +static void set_hw_filter(struct lvts_data *lvts_data, int tc_id) +{ + void __iomem *base = GET_BASE_ADDR(lvts_data, tc_id); + struct device *dev = lvts_data->dev; + const struct lvts_tc_settings *tc = lvts_data->tc; + unsigned int option = tc[tc_id].hw_filter & 0x7; + + /* + * hw filter + * 000: Get one sample + * 001: Get 2 samples and average them + * 010: Get 4 samples, drop max and min, then average the rest of 2 samples + * 011: Get 6 samples, drop max and min, then average the rest of 4 samples + * 100: Get 10 samples, drop max and min, then average the rest of 8 samples + * 101: Get 18 samples, drop max and min, then average the rest of 16 samples + */ + option = (option << 9) | (option << 6) | (option << 3) | option; + writel(option, LVTSMSRCTL0_0 + base); + dev_dbg(dev, "lvts_tc_%d, LVTSMSRCTL0_0= 0x%x\n", tc_id, readl(LVTSMSRCTL0_0 + base)); +} + +static int get_dominator_index(struct lvts_data *lvts_data, int tc_id) +{ + struct device *dev = lvts_data->dev; + const struct lvts_tc_settings *tc = lvts_data->tc; + int d_index; + + if (tc[tc_id].dominator_sensing_point == ALL_SENSING_POINTS) { + d_index = ALL_SENSING_POINTS; + + } else if ((tc[tc_id].dominator_sensing_point < tc[tc_id].num_sensor) || + (tc[tc_id].ts_offset != 0)) { + d_index = tc[tc_id].dominator_sensing_point; + + } else { + dev_err(dev, "LVTS_TC_%d: dominator sensing point = %d. \ + It should be smaller than num_sensor %d\n", + tc_id, tc[tc_id].dominator_sensing_point, tc[tc_id].num_sensor); + dev_err(dev, "Using the sensing point 0 as the dominated sensor\n"); + d_index = SENSING_POINT0; + } + + return d_index; +} + +static void disable_hw_reboot_interrupt(struct lvts_data *lvts_data, int tc_id) +{ + void __iomem *base = GET_BASE_ADDR(lvts_data, tc_id); + unsigned int temp; + + /* + * LVTS thermal controller has two interrupts for thermal HW reboot. + * One is for AP SW and the other is for RGU. + * The interrupt of AP SW can be turned off by a bit of a register, + * but the other for RGU cannot. + * To prevent rebooting device accidentally, we are going to add + * a huge offset 0x3FFF to LVTS and make it always report extremely low temperature. + * LVTS always adds the offset 0x3FFF to MSR_RAW. + * When MSR_RAW is larger, SW will convert lower temperature. + */ + temp = readl(LVTSPROTCTL_0 + base); + writel(temp | 0x3FFF, LVTSPROTCTL_0 + base); + + /* Disable the interrupt of AP SW */ + temp = readl(LVTSMONINT_0 + base); + writel(temp & ~(STAGE3_INT_EN), LVTSMONINT_0 + base); +} + +static void enable_hw_reboot_interrupt(struct lvts_data *lvts_data, int tc_id) +{ + void __iomem *base = GET_BASE_ADDR(lvts_data, tc_id); + unsigned int temp; + + /* Enable the interrupt of AP SW */ + temp = readl(LVTSMONINT_0 + base); + writel(temp | STAGE3_INT_EN, LVTSMONINT_0 + base); + + /* Clear the offset */ + temp = readl(LVTSPROTCTL_0 + base); + writel(temp & ~PROTOFFSET, LVTSPROTCTL_0 + base); +} + +static void set_tc_hw_reboot_threshold(struct lvts_data *lvts_data, int trip_point, int tc_id) +{ + void __iomem *base = GET_BASE_ADDR(lvts_data, tc_id); + struct device *dev = lvts_data->dev; + unsigned int msr_raw, temp, config, d_index; + + d_index = get_dominator_index(lvts_data, tc_id); + + dev_dbg(dev, "lvts_tc_%d: dominator sensing point = %d\n", tc_id, d_index); + + disable_hw_reboot_interrupt(lvts_data, tc_id); + temp = readl(LVTSPROTCTL_0 + base); + if (d_index == ALL_SENSING_POINTS) { + /* Maximum of 4 sensing points */ + config = (0x1 << 16); + writel(config | temp, LVTSPROTCTL_0 + base); + + } else { + /* Select protection sensor */ + config = ((d_index << 2) + 0x2) << 16; + writel(config | temp, LVTSPROTCTL_0 + base); + } + + msr_raw = lvts_temp_to_raw(&lvts_data->coeff, trip_point); + writel(msr_raw, LVTSPROTTC_0 + base); + enable_hw_reboot_interrupt(lvts_data, tc_id); +} + +static void set_all_tc_hw_reboot(struct lvts_data *lvts_data) +{ + const struct lvts_tc_settings *tc = lvts_data->tc; + int i, trip_point; + + for (i = 0; i < lvts_data->num_tc; i++) { + trip_point = tc[i].hw_reboot_trip_point; + + if (tc[i].num_sensor == 0) + continue; + + if (trip_point == THERMAL_TEMP_INVALID) + continue; + + set_tc_hw_reboot_threshold(lvts_data, trip_point, i); + } +} + +static int lvts_init(struct lvts_data *lvts_data) +{ + struct platform_ops *ops = &lvts_data->ops; + struct device *dev = lvts_data->dev; + int ret; + + ret = clk_prepare_enable(lvts_data->clk); + if (ret) { + dev_err(dev, "Failed to enable lvts controller clock: %d\n", ret); + + return ret; + } + + lvts_reset(lvts_data); + device_identification(lvts_data); + if (ops->device_enable_and_init) + ops->device_enable_and_init(lvts_data); + + if (HAS_FEATURE(lvts_data, FEATURE_DEVICE_AUTO_RCK) && (ops->device_enable_auto_rck)) + ops->device_enable_auto_rck(lvts_data); + + else if (ops->device_read_count_rc_n) + ops->device_read_count_rc_n(lvts_data); + + if (ops->set_cal_data) + ops->set_cal_data(lvts_data); + + disable_all_sensing_points(lvts_data); + wait_all_tc_sensing_point_idle(lvts_data); + if (ops->init_controller) + ops->init_controller(lvts_data); + + enable_all_sensing_points(lvts_data); + set_all_tc_hw_reboot(lvts_data); + + return 0; +} + +static int prepare_calibration_data(struct lvts_data *lvts_data) +{ + struct device *dev = lvts_data->dev; + struct lvts_sensor_cal_data *cal_data = &lvts_data->cal_data; + struct platform_ops *ops = &lvts_data->ops; + int i; + + cal_data->count_r = devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*cal_data->count_r), GFP_KERNEL); + if (!cal_data->count_r) + return -ENOMEM; + + cal_data->count_rc = devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*cal_data->count_rc), GFP_KERNEL); + if (!cal_data->count_rc) + return -ENOMEM; + + if (ops->efuse_to_cal_data && !cal_data->use_fake_efuse) + ops->efuse_to_cal_data(lvts_data); + + if (cal_data->golden_temp == 0 || cal_data->golden_temp > GOLDEN_TEMP_MAX) + cal_data->use_fake_efuse = 1; + + if (cal_data->use_fake_efuse) { + /* It means all efuse data are equal to 0 */ + dev_err(dev, "This sample is not calibrated, fake !!\n"); + cal_data->golden_temp = cal_data->default_golden_temp; + for (i = 0; i < lvts_data->num_sensor; i++) { + cal_data->count_r[i] = cal_data->default_count_r; + cal_data->count_rc[i] = cal_data->default_count_rc; + } + } + + lvts_data->coeff.golden_temp = cal_data->golden_temp; + dev_dbg(dev, "golden_temp = %d\n", cal_data->golden_temp); + + return 0; +} + +static int get_calibration_data(struct lvts_data *lvts_data) +{ + struct device *dev = lvts_data->dev; + char cell_name[32]; + struct nvmem_cell *cell; + u32 *buf; + size_t len; + int i, j, index = 0, ret; + + lvts_data->efuse = devm_kcalloc(dev, lvts_data->num_efuse_addr, + sizeof(*lvts_data->efuse), GFP_KERNEL); + if (!lvts_data->efuse) + return -ENOMEM; + + for (i = 0; i < lvts_data->num_efuse_block; i++) { + snprintf(cell_name, sizeof(cell_name), "lvts_calib_data%d", i + 1); + cell = nvmem_cell_get(dev, cell_name); + if (IS_ERR(cell)) { + dev_err(dev, "Failed to get nvmem cell %s\n", cell_name); + + return PTR_ERR(cell); + } + + buf = (u32 *)nvmem_cell_read(cell, &len); + nvmem_cell_put(cell); + if (IS_ERR(buf)) + return PTR_ERR(buf); + + for (j = 0; j < (len / sizeof(u32)); j++) { + if (index >= lvts_data->num_efuse_addr) { + dev_err(dev, "Array efuse is going to overflow"); + kfree(buf); + + return -EINVAL; + } + + lvts_data->efuse[index] = buf[j]; + index++; + } + + kfree(buf); + } + + ret = prepare_calibration_data(lvts_data); + + return ret; +} + +static int lvts_init_tc_regs(struct device *dev, struct lvts_data *lvts_data) +{ + void __iomem *base; + const struct lvts_tc_settings *tc = lvts_data->tc; + unsigned int i, j, s_index, x; + + lvts_data->reg = devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*lvts_data->reg), GFP_KERNEL); + if (!lvts_data->reg) + return -ENOMEM; + + for (i = 0; i < lvts_data->num_tc; i++) { + base = GET_BASE_ADDR(lvts_data, i); + for (j = 0; j < tc[i].num_sensor; j++) { + s_index = tc[i].sensor_map[j]; + x = j + tc[i].ts_offset; + lvts_data->reg[s_index] = LVTSMSR0_0 + base + 0x4 * x; + } + } + + return 0; +} + +static int of_update_lvts_data(struct lvts_data *lvts_data, struct platform_device *pdev) +{ + struct device *dev = lvts_data->dev; + struct resource *res; + int ret; + + lvts_data->clk = devm_clk_get(dev, NULL); + if (IS_ERR(lvts_data->clk)) + return PTR_ERR(lvts_data->clk); + + /* Get base address */ + res = platform_get_mem_or_io(pdev, 0); + if (!res) { + dev_err(dev, "No IO resource\n"); + + return -ENXIO; + } + + lvts_data->base = devm_ioremap_resource(dev, res); + if (IS_ERR(lvts_data->base)) { + dev_err(dev, "Failed to remap io\n"); + + return PTR_ERR(lvts_data->base); + } + + /* Get interrupt number */ + ret = platform_get_irq(pdev, 0); + if (ret < 0) { + dev_err(dev, "No irq resource\n"); + + return ret; + } + + lvts_data->irq_num = ret; + /* Get reset control */ + lvts_data->reset = devm_reset_control_get_by_index(dev, 0); + if (IS_ERR(lvts_data->reset)) { + dev_err(dev, "Failed to get reset control\n"); + + return PTR_ERR(lvts_data->reset); + } + + ret = lvts_init_tc_regs(dev, lvts_data); + if (ret) + return ret; + + ret = get_calibration_data(lvts_data); + if (ret) + return ret; + + return 0; +} + +static void lvts_device_close(struct lvts_data *lvts_data) +{ + void __iomem *base; + unsigned int i; + + for (i = 0; i < lvts_data->num_tc; i++) { + base = GET_BASE_ADDR(lvts_data, i); + lvts_write_device(lvts_data, RESET_ALL_DEVICES(lvts_data), i); + writel(DISABLE_LVTS_CTRL_CLK, LVTSCLKEN_0 + base); + } +} + +static void lvts_close(struct lvts_data *lvts_data) +{ + disable_all_sensing_points(lvts_data); + wait_all_tc_sensing_point_idle(lvts_data); + lvts_device_close(lvts_data); + clk_disable_unprepare(lvts_data->clk); +} + +static void tc_irq_handler(struct lvts_data *lvts_data, int tc_id) +{ + void __iomem *base = GET_BASE_ADDR(lvts_data, tc_id); + const struct device *dev = lvts_data->dev; + unsigned int ret = readl(LVTSMONINTSTS_0 + base); + + /* Write back to clear interrupt status */ + writel(ret, LVTSMONINTSTS_0 + base); + dev_dbg(dev, "LVTS thermal controller %d, LVTSMONINTSTS=0x%08x\n", tc_id, ret); + if (ret & THERMAL_PROTECTION_STAGE_3) + dev_dbg(dev, "Thermal protection stage 3 interrupt triggered\n"); +} + +static irqreturn_t irq_handler(int irq, void *dev_id) +{ + void __iomem *base; + struct lvts_data *lvts_data = (struct lvts_data *)dev_id; + struct device *dev = lvts_data->dev; + const struct lvts_tc_settings *tc = lvts_data->tc; + unsigned int i, irq_bitmap; + + base = lvts_data->base; + irq_bitmap = readl(THERMINTST + base); + dev_dbg(dev, "THERMINTST = 0x%x\n", irq_bitmap); + for (i = 0; i < lvts_data->num_tc; i++) { + if (tc[i].irq_bit == 0) + tc_irq_handler(lvts_data, i); + } + + return IRQ_HANDLED; +} + +static int lvts_register_irq_handler(struct lvts_data *lvts_data) +{ + struct device *dev = lvts_data->dev; + int ret; + + ret = devm_request_irq(dev, lvts_data->irq_num, irq_handler, IRQF_TRIGGER_NONE, + "mtk_lvts", lvts_data); + if (ret) { + dev_err(dev, "Failed to register LVTS IRQ, ret %d, irq_num %d\n", + ret, lvts_data->irq_num); + lvts_close(lvts_data); + + return ret; + } + + return 0; +} + +static int lvts_register_thermal_zones(struct lvts_data *lvts_data) +{ + struct device *dev = lvts_data->dev; + struct thermal_zone_device *tzdev; + struct soc_temp_tz *lvts_tz; + int i, ret; + + for (i = 0; i < lvts_data->num_sensor; i++) { + lvts_tz = devm_kzalloc(dev, sizeof(*lvts_tz), GFP_KERNEL); + if (!lvts_tz) { + lvts_close(lvts_data); + + return -ENOMEM; + } + + lvts_tz->id = i; + lvts_tz->lvts_data = lvts_data; + tzdev = devm_thermal_zone_of_sensor_register(dev, lvts_tz->id, lvts_tz, + &soc_temp_lvts_ops); + if (IS_ERR(tzdev)) { + if (lvts_tz->id != 0) + return 0; + + ret = PTR_ERR(tzdev); + dev_err(dev, "Failed to register lvts tz %d, ret = %d\n", lvts_tz->id, ret); + lvts_close(lvts_data); + + return ret; + } + } + + return 0; +} + +void lvts_device_enable_and_init(struct lvts_data *lvts_data) +{ + unsigned int i; + + for (i = 0; i < lvts_data->num_tc; i++) { + lvts_write_device(lvts_data, STOP_COUNTING_V4, i); + lvts_write_device(lvts_data, SET_RG_TSFM_LPDLY_V4, i); + lvts_write_device(lvts_data, SET_COUNTING_WINDOW_20US1_V4, i); + lvts_write_device(lvts_data, SET_COUNTING_WINDOW_20US2_V4, i); + lvts_write_device(lvts_data, TSV2F_CHOP_CKSEL_AND_TSV2F_EN_V4, i); + lvts_write_device(lvts_data, TSBG_DEM_CKSEL_X_TSBG_CHOP_EN_V4, i); + lvts_write_device(lvts_data, SET_TS_RSV_V4, i); + lvts_write_device(lvts_data, SET_TS_EN_V4, i); + lvts_write_device(lvts_data, TOGGLE_RG_TSV2F_VCO_RST1_V4, i); + lvts_write_device(lvts_data, TOGGLE_RG_TSV2F_VCO_RST2_V4, i); + } + + lvts_data->counting_window_us = 20; +} +EXPORT_SYMBOL_GPL(lvts_device_enable_and_init); + +void lvts_device_enable_auto_rck_v4(struct lvts_data *lvts_data) +{ + unsigned int i; + + for (i = 0; i < lvts_data->num_tc; i++) + lvts_write_device(lvts_data, SET_LVTS_AUTO_RCK_V4, i); +} +EXPORT_SYMBOL_GPL(lvts_device_enable_auto_rck_v4); + +int lvts_device_read_count_rc_n_v4(struct lvts_data *lvts_data) +{ + void __iomem *base; + struct device *dev = lvts_data->dev; + const struct lvts_tc_settings *tc = lvts_data->tc; + struct lvts_sensor_cal_data *cal_data = &lvts_data->cal_data; + unsigned int s_index, data; + int ret, i, j; + + cal_data->count_rc_now = devm_kcalloc(dev, lvts_data->num_sensor, + sizeof(*cal_data->count_rc_now), GFP_KERNEL); + if (!cal_data->count_rc_now) + return -ENOMEM; + + for (i = 0; i < lvts_data->num_tc; i++) { + base = GET_BASE_ADDR(lvts_data, i); + for (j = 0; j < tc[i].num_sensor; j++) { + s_index = tc[i].sensor_map[j]; + lvts_write_device(lvts_data, SELECT_SENSOR_RCK_V4(j), i); + lvts_write_device(lvts_data, SET_DEVICE_SINGLE_MODE_V4, i); + lvts_write_device(lvts_data, KICK_OFF_RCK_COUNTING_V4, i); + ret = readl_poll_timeout(LVTS_CONFIG_0 + base, data, + !(data & DEVICE_SENSING_STATUS), 2, 200); + if (ret) + dev_err(dev, "LVTS_TC_%d DEVICE_SENSING_STATUS didn't ready\n", i); + + data = lvts_read_device(lvts_data, 0x00, i); + cal_data->count_rc_now[s_index] = (data & COUNT_RC_NOW_MASK); + } + + /* Recover Setting for Normal Access on + * temperature fetch + */ + lvts_write_device(lvts_data, SET_SENSOR_NO_RCK_V4, i); + lvts_write_device(lvts_data, SET_DEVICE_LOW_POWER_SINGLE_MODE_V4, i); + } + + return 0; +} +EXPORT_SYMBOL_GPL(lvts_device_read_count_rc_n_v4); + +void lvts_set_calibration_data_v4(struct lvts_data *lvts_data) +{ + void __iomem *base; + const struct lvts_tc_settings *tc = lvts_data->tc; + struct lvts_sensor_cal_data *cal_data = &lvts_data->cal_data; + unsigned int i, j, s_index, x; + u32 lvts_calib_data; + + for (i = 0; i < lvts_data->num_tc; i++) { + base = GET_BASE_ADDR(lvts_data, i); + for (j = 0; j < tc[i].num_sensor; j++) { + s_index = tc[i].sensor_map[j]; + x = j + tc[i].ts_offset; + if (HAS_FEATURE(lvts_data, FEATURE_DEVICE_AUTO_RCK)) + lvts_calib_data = cal_data->count_r[s_index]; + + else + lvts_calib_data = (((u32)cal_data->count_rc_now[s_index]) * + cal_data->count_r[s_index]) >> 14; + + writel(lvts_calib_data, LVTSEDATA00_0 + base + 0x4 * x); + } + } +} +EXPORT_SYMBOL_GPL(lvts_set_calibration_data_v4); + +void lvts_init_controller_v4(struct lvts_data *lvts_data) +{ + void __iomem *base; + struct device *dev = lvts_data->dev; + unsigned int i; + + for (i = 0; i < lvts_data->num_tc; i++) { + base = GET_BASE_ADDR(lvts_data, i); + lvts_write_device(lvts_data, SET_DEVICE_LOW_POWER_SINGLE_MODE_V4, i); + writel(SET_SENSOR_INDEX, LVTSTSSEL_0 + base); + writel(SET_CALC_SCALE_RULES, LVTSCALSCALE_0 + base); + set_polling_speed(lvts_data, i); + set_hw_filter(lvts_data, i); + dev_dbg(dev, "lvts_tc_%d: read all %d sensors in %d us, one in %d us\n", + i, GET_TC_SENSOR_NUM(lvts_data, i), GROUP_LATENCY_US(lvts_data, i), + SENSOR_LATENCY_US(lvts_data, i)); + } +} +EXPORT_SYMBOL_GPL(lvts_init_controller_v4); + +int lvts_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct lvts_data *lvts_data; + int ret; + + lvts_data = (struct lvts_data *)of_device_get_match_data(dev); + if (!lvts_data) { + dev_err(dev, "Failed to get lvts platform data\n"); + + return -ENODATA; + } + + lvts_data->dev = &pdev->dev; + ret = of_update_lvts_data(lvts_data, pdev); + if (ret) + return ret; + + platform_set_drvdata(pdev, lvts_data); + ret = lvts_init(lvts_data); + if (ret) + return ret; + + ret = lvts_register_irq_handler(lvts_data); + if (ret) + return ret; + + ret = lvts_register_thermal_zones(lvts_data); + if (ret) + return ret; + + return 0; +} + +int lvts_remove(struct platform_device *pdev) +{ + struct lvts_data *lvts_data; + + lvts_data = (struct lvts_data *)platform_get_drvdata(pdev); + lvts_close(lvts_data); + + return 0; +} + +int lvts_suspend(struct platform_device *pdev, pm_message_t state) +{ + int ret; + + ret = lvts_remove(pdev); + if (ret) + return ret; + + return 0; +} + +int lvts_resume(struct platform_device *pdev) +{ + int ret; + + ret = lvts_probe(pdev); + if (ret) + return ret; + + return 0; +} + +void lvts_shutdown(struct platform_device *pdev) +{ + lvts_remove(pdev); +} + +MODULE_AUTHOR("Yu-Chia Chang "); +MODULE_AUTHOR("Michael Kao "); +MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); +MODULE_LICENSE("GPL"); diff --git a/drivers/thermal/mediatek/lvts_thermal.h b/drivers/thermal/mediatek/lvts_thermal.h new file mode 100644 index 000000000000..a94ce46acccd --- /dev/null +++ b/drivers/thermal/mediatek/lvts_thermal.h @@ -0,0 +1,385 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#ifndef __MTK_SOC_TEMP_LVTS_H__ +#define __MTK_SOC_TEMP_LVTS_H__ + +#define PERIOD_UNIT 12 +#define GROUP_INTERVAL_DELAY 1 +#define FILTER_INTERVAL_DELAY 1 +#define SENSOR_INTERVAL_DELAY 1 + +#define HW_REBOOT_TRIP_POINT 117000 + +#define FEATURE_DEVICE_AUTO_RCK BIT(0) +#define NUM_EFUSE_ADDR 22 +#define NUM_EFUSE_BLOCK_MT8192 1 +#define DEFAULT_GOLDEN_TEMP 50 +#define DEFAULT_CUONT_R 35000 +#define DEFAULT_CUONT_RC 2750 +#define COEFF_A -250460 +#define COEFF_B 250460 + +#define CLOCK_26MHZ_CYCLE_NS 38 +#define BUS_ACCESS_US 2 +#define GOLDEN_TEMP_MAX 62 + +#define LVTS_FILTER_SAMPLES_1 1 +#define LVTS_FILTER_SAMPLES_2 2 +#define LVTS_FILTER_SAMPLES_4 4 +#define LVTS_FILTER_SAMPLES_6 6 +#define LVTS_FILTER_SAMPLES_10 10 +#define LVTS_FILTER_SAMPLES_18 18 + +#define TC_SENSING_POINT_0 BIT(0) +#define TC_SENSING_POINT_7 BIT(7) +#define TC_SENSING_POINT_10 BIT(10) +#define ALL_TC_SENSING_POINT_STATUS (BIT(10) | BIT(7) | BIT(0)) +#define COUNT_RC_NOW_MASK GENMASK(23, 0) +#define PERIOD_UNIT_MASK GENMASK(9, 0) +#define GROUP_INTERVAL_DELAY_MASK GENMASK(29, 20) +#define FILTER_INTERVAL_DELAY_MASK GENMASK(25, 16) +#define SENSOR_INTERVAL_DELAY_MASK GENMASK(9, 0) + +/* LVTS device register */ +#define RG_TSFM_DATA_0 0x00 +#define RG_TSFM_DATA_1 0x01 +#define RG_TSFM_DATA_2 0x02 +#define RG_TSFM_CTRL_0 0x03 +#define RG_TSFM_CTRL_1 0x04 +#define RG_TSFM_CTRL_2 0x05 +#define RG_TSFM_CTRL_3 0x06 +#define RG_TSFM_CTRL_4 0x07 +#define RG_TSV2F_CTRL_0 0x08 +#define RG_TSV2F_CTRL_1 0x09 +#define RG_TSV2F_CTRL_2 0x0A +#define RG_TSV2F_CTRL_3 0x0B +#define RG_TSV2F_CTRL_4 0x0C +#define RG_TSV2F_CTRL_5 0x0D +#define RG_TSV2F_CTRL_6 0x0E +#define RG_TEMP_DATA_0 0x10 +#define RG_TEMP_DATA_1 0x11 +#define RG_TEMP_DATA_2 0x12 +#define RG_TEMP_DATA_3 0x13 +#define RG_RC_DATA_0 0x14 +#define RG_RC_DATA_1 0x15 +#define RG_RC_DATA_2 0x16 +#define RG_RC_DATA_3 0x17 +#define RG_DIV_DATA_0 0x18 +#define RG_DIV_DATA_1 0x19 +#define RG_DIV_DATA_2 0x1A +#define RG_DIV_DATA_3 0x1B +#define RG_TST_DATA_0 0x70 +#define RG_TST_DATA_1 0x71 +#define RG_TST_DATA_2 0x72 +#define RG_TST_CTRL 0x73 +#define RG_DBG_FQMTR 0xF0 +#define RG_DBG_LPSEQ 0xF1 +#define RG_DBG_STATE 0xF2 +#define RG_DBG_CHKSUM 0xF3 +#define RG_DID_LVTS 0xFC +#define RG_DID_REV 0xFD +#define RG_TSFM_RST 0xFF + +/* LVTS controller register */ +#define LVTSMONCTL0_0 0x000 +#define ENABLE_SENSING_POINT(num) (LVTS_SINGLE_SENSE | GENMASK(((num) - 1), 0)) +#define DISABLE_SENSING_POINT (LVTS_SINGLE_SENSE | 0x0) +#define LVTSMONCTL1_0 0x004 +#define LVTSMONCTL2_0 0x008 +#define LVTSMONINT_0 0x00C +#define STAGE3_INT_EN BIT(31) +#define LVTSMONINTSTS_0 0x010 +#define LVTSMONIDET0_0 0x014 +#define LVTSMONIDET1_0 0x018 +#define LVTSMONIDET2_0 0x01C +#define LVTSMONIDET3_0 0x020 +#define LVTSH2NTHRE_0 0x024 +#define LVTSHTHRE_0 0x028 +#define LVTSCTHRE_0 0x02C +#define LVTSOFFSETH_0 0x030 +#define LVTSOFFSETL_0 0x034 +#define LVTSMSRCTL0_0 0x038 +#define LVTSMSRCTL1_0 0x03C +#define LVTSTSSEL_0 0x040 +#define SET_SENSOR_INDEX 0x13121110 +#define LVTSDEVICETO_0 0x044 +#define LVTSCALSCALE_0 0x048 +#define SET_CALC_SCALE_RULES 0x00000300 +#define LVTS_ID_0 0x04C +#define LVTS_CONFIG_0 0x050 + +#define SCK_ONLY BIT(31) +#define BROADCAST_ID_UPDATE BIT(26) +#define DEVICE_SENSING_STATUS BIT(25) +#define DEVICE_ACCESS_STARTUS BIT(24) +#define READ_32BIT_ACCESS BIT(17) +#define WRITE_ACCESS BIT(16) +#define LVTS_SINGLE_SENSE BIT(9) +#define FEATURE_CK26M_ACTIVE BIT(1) +#define DEVICE_REG_DATA GENMASK(7, 0) + +#define LVTSEDATA00_0 0x054 +#define LVTSEDATA01_0 0x058 +#define LVTSEDATA02_0 0x05C +#define LVTSEDATA03_0 0x060 +#define LVTSMSR0_0 0x090 +#define MRS_RAW_MASK GENMASK(15, 0) +#define MRS_RAW_VALID_BIT BIT(16) +#define LVTSMSR1_0 0x094 +#define LVTSMSR2_0 0x098 +#define LVTSMSR3_0 0x09C +#define LVTSIMMD0_0 0x0A0 +#define LVTSIMMD1_0 0x0A4 +#define LVTSIMMD2_0 0x0A8 +#define LVTSIMMD3_0 0x0AC +#define LVTSRDATA0_0 0x0B0 +#define LVTSRDATA1_0 0x0B4 +#define LVTSRDATA2_0 0x0B8 +#define LVTSRDATA3_0 0x0BC +#define LVTSPROTCTL_0 0x0C0 +#define PROTOFFSET GENMASK(15, 0) +#define LVTSPROTTA_0 0x0C4 +#define LVTSPROTTB_0 0x0C8 +#define LVTSPROTTC_0 0x0CC +#define LVTSCLKEN_0 0x0E4 +#define ENABLE_LVTS_CTRL_CLK (1) +#define DISABLE_LVTS_CTRL_CLK (0) +#define LVTSDBGSEL_0 0x0E8 +#define LVTSDBGSIG_0 0x0EC +#define LVTSSPARE0_0 0x0F0 +#define LVTSSPARE1_0 0x0F4 +#define LVTSSPARE2_0 0x0F8 +#define LVTSSPARE3_0 0x0FC +#define THERMINTST 0xF04 + +/* LVTS register mask */ +#define THERMAL_COLD_INTERRUPT_0 BIT(0) +#define THERMAL_HOT_INTERRUPT_0 BIT(1) +#define THERMAL_LOW_OFFSET_INTERRUPT_0 BIT(2) +#define THERMAL_HIGH_OFFSET_INTERRUPT_0 BIT(3) +#define THERMAL_HOT2NORMAL_INTERRUPT_0 BIT(4) +#define THERMAL_COLD_INTERRUPT_1 BIT(5) +#define THERMAL_HOT_INTERRUPT_1 BIT(6) +#define THERMAL_LOW_OFFSET_INTERRUPT_1 BIT(7) +#define THERMAL_HIGH_OFFSET_INTERRUPT_1 BIT(8) +#define THERMAL_HOT2NORMAL_INTERRUPT_1 BIT(9) +#define THERMAL_COLD_INTERRUPT_2 BIT(10) +#define THERMAL_HOT_INTERRUPT_2 BIT(11) +#define THERMAL_LOW_OFFSET_INTERRUPT_2 BIT(12) +#define THERMAL_HIGH_OFFSET_INTERRUPT_2 BIT(13) +#define THERMAL_HOT2NORMAL_INTERRUPT_2 BIT(14) +#define THERMAL_AHB_TIMEOUT_INTERRUPT BIT(15) +#define THERMAL_DEVICE_TIMEOUT_INTERRUPT BIT(15) +#define THERMAL_IMMEDIATE_INTERRUPT_0 BIT(16) +#define THERMAL_IMMEDIATE_INTERRUPT_1 BIT(17) +#define THERMAL_IMMEDIATE_INTERRUPT_2 BIT(18) +#define THERMAL_FILTER_INTERRUPT_0 BIT(19) +#define THERMAL_FILTER_INTERRUPT_1 BIT(20) +#define THERMAL_FILTER_INTERRUPT_2 BIT(21) +#define THERMAL_COLD_INTERRUPT_3 BIT(22) +#define THERMAL_HOT_INTERRUPT_3 BIT(23) +#define THERMAL_LOW_OFFSET_INTERRUPT_3 BIT(24) +#define THERMAL_HIGH_OFFSET_INTERRUPT_3 BIT(25) +#define THERMAL_HOT2NORMAL_INTERRUPT_3 BIT(26) +#define THERMAL_IMMEDIATE_INTERRUPT_3 BIT(27) +#define THERMAL_FILTER_INTERRUPT_3 BIT(28) +#define THERMAL_PROTECTION_STAGE_1 BIT(29) +#define THERMAL_PROTECTION_STAGE_2 BIT(30) +#define THERMAL_PROTECTION_STAGE_3 BIT(31) + +#define CFG_REGISTER(reg, value) (reg << 8 | value) +#define STOP_COUNTING_V4 CFG_REGISTER(RG_TSFM_CTRL_0, 0x00) +#define SET_RG_TSFM_LPDLY_V4 CFG_REGISTER(RG_TSFM_CTRL_4, 0xA6) +#define SET_COUNTING_WINDOW_20US1_V4 CFG_REGISTER(RG_TSFM_CTRL_2, 0x00) +#define SET_COUNTING_WINDOW_20US2_V4 CFG_REGISTER(RG_TSFM_CTRL_1, 0x20) +#define TSV2F_CHOP_CKSEL_AND_TSV2F_EN_V4 CFG_REGISTER(RG_TSV2F_CTRL_2, 0x84) +#define TSBG_DEM_CKSEL_X_TSBG_CHOP_EN_V4 CFG_REGISTER(RG_TSV2F_CTRL_4, 0x7C) +#define SET_TS_RSV_V4 CFG_REGISTER(RG_TSV2F_CTRL_1, 0x8D) +#define SET_TS_EN_V4 CFG_REGISTER(RG_TSV2F_CTRL_0, 0xF4) +#define TOGGLE_RG_TSV2F_VCO_RST1_V4 CFG_REGISTER(RG_TSV2F_CTRL_0, 0xFC) +#define TOGGLE_RG_TSV2F_VCO_RST2_V4 CFG_REGISTER(RG_TSV2F_CTRL_0, 0xF4) + +#define SET_LVTS_AUTO_RCK_V4 CFG_REGISTER(RG_TSV2F_CTRL_6, 0x01) +#define SELECT_SENSOR_RCK_V4(id) CFG_REGISTER(RG_TSV2F_CTRL_5, (id)) +#define SET_DEVICE_SINGLE_MODE_V4 CFG_REGISTER(RG_TSFM_CTRL_3, 0x78) +#define KICK_OFF_RCK_COUNTING_V4 CFG_REGISTER(RG_TSFM_CTRL_0, 0x02) +#define SET_SENSOR_NO_RCK_V4 CFG_REGISTER(RG_TSV2F_CTRL_5, 0x10) +#define SET_DEVICE_LOW_POWER_SINGLE_MODE_V4 CFG_REGISTER(RG_TSFM_CTRL_3, 0xB8) + +#define HAS_FEATURE(lvts_data, feature) (lvts_data->feature_bitmap & (feature)) +#define GET_BASE_ADDR(lvts_data, tc_id) (lvts_data->base + lvts_data->tc[tc_id].addr_offset) +#define GET_CAL_DATA_BITMASK(index, lvts_data, h, l) (((index) < lvts_data->num_efuse_addr) ? \ + ((lvts_data->efuse[(index)] & GENMASK(h, l)) >> l) : 0) + +#define GET_TC_SENSOR_NUM(lvts_data, tc_id) (lvts_data->tc[tc_id].num_sensor) +#define ONE_SAMPLE(lvts_data) (lvts_data->counting_window_us + 2 * BUS_ACCESS_US) +#define NUM_OF_SAMPLE(lvts_data, tc_id) ((lvts_data->tc[tc_id].hw_filter < LVTS_FILTER_2) ? \ + LVTS_FILTER_SAMPLES_1 : ((lvts_data->tc[tc_id].hw_filter > LVTS_FILTER_16_OF_18) ? \ + LVTS_FILTER_SAMPLES_1 : ((lvts_data->tc[tc_id].hw_filter == LVTS_FILTER_16_OF_18) ? \ + LVTS_FILTER_SAMPLES_18 : ((lvts_data->tc[tc_id].hw_filter == LVTS_FILTER_8_OF_10) ? \ + LVTS_FILTER_SAMPLES_10 : (lvts_data->tc[tc_id].hw_filter * 2))))) + +#define PERIOD_UNIT_US(lvts_data, tc_id) ((lvts_data->tc[tc_id].tc_speed->period_unit * 256 \ + * CLOCK_26MHZ_CYCLE_NS) / 1000) +#define FILTER_INT_US(lvts_data, tc_id) (lvts_data->tc[tc_id].tc_speed->filter_interval_delay \ + * PERIOD_UNIT_US(lvts_data, tc_id)) +#define SENSOR_INT_US(lvts_data, tc_id) (lvts_data->tc[tc_id].tc_speed->sensor_interval_delay \ + * PERIOD_UNIT_US(lvts_data, tc_id)) +#define GROUP_INT_US(lvts_data, tc_id) (lvts_data->tc[tc_id].tc_speed->group_interval_delay \ + * PERIOD_UNIT_US(lvts_data, tc_id)) +#define SENSOR_LATENCY_US(lvts_data, tc_id) ((NUM_OF_SAMPLE(lvts_data, tc_id) - 1) * \ + FILTER_INT_US(lvts_data, tc_id) + NUM_OF_SAMPLE(lvts_data, tc_id) * ONE_SAMPLE(lvts_data)) +#define GROUP_LATENCY_US(lvts_data, tc_id) (GET_TC_SENSOR_NUM(lvts_data, tc_id) * \ + SENSOR_LATENCY_US(lvts_data, tc_id) + (GET_TC_SENSOR_NUM(lvts_data, tc_id) - 1) * \ + SENSOR_INT_US(lvts_data, tc_id) + GROUP_INT_US(lvts_data, tc_id)) + +#define CK26M_ACTIVE(lvts_data) (((lvts_data->feature_bitmap & FEATURE_CK26M_ACTIVE) \ + ? 1 : 0) << 30) +#define DEVICE_ACCESS (SCK_ONLY | DEVICE_ACCESS_STARTUS | READ_32BIT_ACCESS) +#define DEVICE_READ(lvts_data) (CK26M_ACTIVE(lvts_data) | DEVICE_ACCESS) +#define DEVICE_WRITE(lvts_data) (CK26M_ACTIVE(lvts_data) | DEVICE_ACCESS | WRITE_ACCESS) +#define RESET_ALL_DEVICES(lvts_data) (DEVICE_WRITE(lvts_data) | RG_TSFM_RST << 8 | 0xFF) +#define READ_DEVICE_REG(lvts_data, reg_id) (DEVICE_READ(lvts_data) | (reg_id) << 8 | 0x00) +#define READ_BACK_DEVICE_ID(lvts_data) (CK26M_ACTIVE(lvts_data) | DEVICE_ACCESS | \ + BROADCAST_ID_UPDATE | RG_DID_LVTS << 8) + +/* + * LVTS HW filter settings + * 000: Get one sample + * 001: Get 2 samples and average them + * 010: Get 4 samples, drop max and min, then average the rest of 2 samples + * 011: Get 6 samples, drop max and min, then average the rest of 4 samples + * 100: Get 10 samples, drop max and min, then average the rest of 8 samples + * 101: Get 18 samples, drop max and min, then average the rest of 16 samples + */ +enum lvts_hw_filter { + LVTS_FILTER_1, + LVTS_FILTER_2, + LVTS_FILTER_2_OF_4, + LVTS_FILTER_4_OF_6, + LVTS_FILTER_8_OF_10, + LVTS_FILTER_16_OF_18 +}; + +enum lvts_sensing_point { + SENSING_POINT0, + SENSING_POINT1, + SENSING_POINT2, + SENSING_POINT3, + ALL_SENSING_POINTS +}; + +struct lvts_data; + +/** + * struct lvts_speed_settings - A structure to hold the data related to polling rate + * @period_unit: Period unit is a base for all interval delays + * @group_interval_delay: Delay between different rounds + * @filter_interval_delay: Delay between two samples of the same sensor + * @sensor_interval_delay: Delay between two samples of differnet sensors + * + * Calculation is achieved with the following equations: + * For the period unit: (period_us * 1000) / (256 * clock_26mhz_cycle_ns) + * For the interval delays: delay / period_us + */ +struct lvts_speed_settings { + unsigned int period_unit; + unsigned int group_interval_delay; + unsigned int filter_interval_delay; + unsigned int sensor_interval_delay; +}; + +struct lvts_tc_settings { + unsigned int dev_id; + unsigned int addr_offset; + unsigned int num_sensor; + unsigned int ts_offset; + unsigned int sensor_map[ALL_SENSING_POINTS]; /* In sensor ID */ + struct lvts_speed_settings *tc_speed; + /* + * HW filter setting + * 000: Get one sample + * 001: Get 2 samples and average them + * 010: Get 4 samples, drop max and min, then average the rest of 2 samples + * 011: Get 6 samples, drop max and min, then average the rest of 4 samples + * 100: Get 10 samples, drop max and min, then average the rest of 8 samples + * 101: Get 18 samples, drop max and min, then average the rest of 16 samples + */ + unsigned int hw_filter; + /* + * Dominator_sensing point is used to select a sensing point + * and reference its temperature to trigger Thermal HW Reboot + * When it is ALL_SENSING_POINTS, it will select all sensing points + */ + int dominator_sensing_point; + int hw_reboot_trip_point; /* -274000: Disable HW reboot */ + unsigned int irq_bit; +}; + +struct lvts_formula_coeff { + int a; + int b; + unsigned int golden_temp; +}; + +struct lvts_sensor_cal_data { + int use_fake_efuse; /* 1: Use fake efuse, 0: Use real efuse */ + unsigned int golden_temp; + unsigned int *count_r; + unsigned int *count_rc; + unsigned int *count_rc_now; + unsigned int default_golden_temp; + unsigned int default_count_r; + unsigned int default_count_rc; +}; + +struct platform_ops { + void (*efuse_to_cal_data)(struct lvts_data *lvts_data); + void (*device_enable_and_init)(struct lvts_data *lvts_data); + void (*device_enable_auto_rck)(struct lvts_data *lvts_data); + int (*device_read_count_rc_n)(struct lvts_data *lvts_data); + void (*set_cal_data)(struct lvts_data *lvts_data); + void (*init_controller)(struct lvts_data *lvts_data); +}; + +struct lvts_data { + struct device *dev; + struct clk *clk; + void __iomem *base; /* LVTS base addresses */ + unsigned int irq_num; /* LVTS interrupt numbers */ + struct reset_control *reset; + int num_tc; /* Number of LVTS thermal controllers */ + const struct lvts_tc_settings *tc; + int counting_window_us; /* LVTS device counting window */ + int num_sensor; /* Number of sensors in this platform */ + void __iomem **reg; + struct platform_ops ops; + int feature_bitmap; /* Show what features are enabled */ + unsigned int num_efuse_addr; + unsigned int *efuse; + unsigned int num_efuse_block; /* Number of contiguous efuse indexes */ + struct lvts_sensor_cal_data cal_data; + struct lvts_formula_coeff coeff; +}; + +struct soc_temp_tz { + unsigned int id; + struct lvts_data *lvts_data; +}; + +extern void lvts_device_enable_and_init(struct lvts_data *lvts_data); +extern void lvts_device_enable_auto_rck_v4(struct lvts_data *lvts_data); +extern int lvts_device_read_count_rc_n_v4(struct lvts_data *lvts_data); +extern void lvts_set_calibration_data_v4(struct lvts_data *lvts_data); +extern void lvts_init_controller_v4(struct lvts_data *lvts_data); + +extern int lvts_probe(struct platform_device *pdev); +extern int lvts_remove(struct platform_device *pdev); +extern int lvts_suspend(struct platform_device *pdev, pm_message_t state); +extern int lvts_resume(struct platform_device *pdev); +extern void lvts_shutdown(struct platform_device *pdev); + +#endif /* __MTK_SOC_TEMP_LVTS_H__ */ diff --git a/drivers/thermal/mediatek/lvts_v4.c b/drivers/thermal/mediatek/lvts_v4.c new file mode 100644 index 000000000000..3dc00d2589f9 --- /dev/null +++ b/drivers/thermal/mediatek/lvts_v4.c @@ -0,0 +1,249 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2022 MediaTek Inc. + */ + +#include +#include +#include "lvts_thermal.h" + +enum mt8192_lvts_mcu_sensor_enum { + MT8192_TS1_0, + MT8192_TS1_1, + MT8192_TS2_0, + MT8192_TS2_1, + MT8192_TS3_0, + MT8192_TS3_1, + MT8192_TS3_2, + MT8192_TS3_3, + MT8192_NUM_TS_MCU +}; + +enum mt8192_lvts_ap_sensor_enum { + MT8192_TS4_0, + MT8192_TS4_1, + MT8192_TS5_0, + MT8192_TS5_1, + MT8192_TS6_0, + MT8192_TS6_1, + MT8192_TS7_0, + MT8192_TS7_1, + MT8192_TS7_2, + MT8192_NUM_TS_AP +}; + +static void mt8192_mcu_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + const unsigned int mt8192_ts[] = { MT8192_TS2_0, MT8192_TS3_0 }; + struct lvts_sensor_cal_data *cal_data = &lvts_data->cal_data; + unsigned int i, j; + + cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, lvts_data, 31, 24); + + for (i = 0; i < MT8192_NUM_TS_MCU; i++) + cal_data->count_r[i] = GET_CAL_DATA_BITMASK(i + 1, lvts_data, 23, 0); + + cal_data->count_rc[MT8192_TS1_0] = GET_CAL_DATA_BITMASK(21, lvts_data, 23, 0); + + for (i = 0; i < (ARRAY_SIZE(mt8192_ts)); i++) { + for (j = 1; j <= 18; j++) { + cal_data->count_rc[mt8192_ts[i]] = (GET_CAL_DATA_BITMASK(j, lvts_data, 31, 24) + << 16) + (GET_CAL_DATA_BITMASK(j, lvts_data, 31, 24) << 8) + + GET_CAL_DATA_BITMASK(j, lvts_data, 31, 24); + } + } +} + +static void mt8192_ap_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + const unsigned int mt8192_ts[] = { MT8192_TS4_0, MT8192_TS5_0, MT8192_TS6_0, MT8192_TS7_0 }; + struct lvts_sensor_cal_data *cal_data = &lvts_data->cal_data; + unsigned int i, j; + + cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, lvts_data, 31, 24); + + for (i = 0; i < MT8192_NUM_TS_AP; i++) + cal_data->count_r[i] = GET_CAL_DATA_BITMASK(i + 1, lvts_data, 23, 0); + + for (i = 0; i < (ARRAY_SIZE(mt8192_ts)); i++) { + for (j = 1; j <= 18; j++) { + cal_data->count_rc[mt8192_ts[i]] = (GET_CAL_DATA_BITMASK(j, lvts_data, 31, 24) + << 16) + (GET_CAL_DATA_BITMASK(j, lvts_data, 31, 24) << 8) + + GET_CAL_DATA_BITMASK(j, lvts_data, 31, 24); + } + } +} + +static struct lvts_speed_settings tc_speed_mt8192 = { + .period_unit = PERIOD_UNIT, + .group_interval_delay = GROUP_INTERVAL_DELAY, + .filter_interval_delay = FILTER_INTERVAL_DELAY, + .sensor_interval_delay = SENSOR_INTERVAL_DELAY, +}; + +static const struct lvts_tc_settings mt8192_tc_mcu_settings[] = { + [0] = { + .dev_id = 0x81, + .addr_offset = 0x0, + .num_sensor = 2, + .ts_offset = 0, + .sensor_map = { MT8192_TS1_0, MT8192_TS1_1 }, + .tc_speed = &tc_speed_mt8192, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(3), + }, + [1] = { + .dev_id = 0x82, + .addr_offset = 0x100, + .num_sensor = 2, + .ts_offset = 0, + .sensor_map = { MT8192_TS2_0, MT8192_TS2_1 }, + .tc_speed = &tc_speed_mt8192, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(4), + }, + [2] = { + .dev_id = 0x83, + .addr_offset = 0x200, + .num_sensor = 4, + .ts_offset = 0, + .sensor_map = { MT8192_TS3_0, MT8192_TS3_1, MT8192_TS3_2, MT8192_TS3_3 }, + .tc_speed = &tc_speed_mt8192, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(5), + } +}; + +static const struct lvts_tc_settings mt8192_tc_ap_settings[] = { + [0] = { + .dev_id = 0x84, + .addr_offset = 0x0, + .num_sensor = 2, + .ts_offset = 0, + .sensor_map = { MT8192_TS4_0, MT8192_TS4_1 }, + .tc_speed = &tc_speed_mt8192, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(3), + }, + [1] = { + .dev_id = 0x85, + .addr_offset = 0x100, + .num_sensor = 2, + .ts_offset = 0, + .sensor_map = { MT8192_TS5_0, MT8192_TS5_1 }, + .tc_speed = &tc_speed_mt8192, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(4), + }, + [2] = { + .dev_id = 0x86, + .addr_offset = 0x200, + .num_sensor = 2, + .ts_offset = 0, + .sensor_map = { MT8192_TS6_0, MT8192_TS6_1 }, + .tc_speed = &tc_speed_mt8192, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(5), + }, + [3] = { + .dev_id = 0x87, + .addr_offset = 0x300, + .num_sensor = 3, + .ts_offset = 0, + .sensor_map = { MT8192_TS7_0, MT8192_TS7_1, MT8192_TS7_2 }, + .tc_speed = &tc_speed_mt8192, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT2, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(6), + } +}; + +static const struct lvts_data mt8192_lvts_mcu_data = { + .num_tc = (ARRAY_SIZE(mt8192_tc_mcu_settings)), + .tc = mt8192_tc_mcu_settings, + .num_sensor = MT8192_NUM_TS_MCU, + .ops = { + .efuse_to_cal_data = mt8192_mcu_efuse_to_cal_data, + .device_enable_and_init = lvts_device_enable_and_init, + .device_enable_auto_rck = lvts_device_enable_auto_rck_v4, + .device_read_count_rc_n = lvts_device_read_count_rc_n_v4, + .set_cal_data = lvts_set_calibration_data_v4, + .init_controller = lvts_init_controller_v4, + }, + .feature_bitmap = FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr = NUM_EFUSE_ADDR, + .num_efuse_block = NUM_EFUSE_BLOCK_MT8192, + .cal_data = { + .default_golden_temp = DEFAULT_GOLDEN_TEMP, + .default_count_r = DEFAULT_CUONT_R, + .default_count_rc = DEFAULT_CUONT_RC, + }, + .coeff = { + .a = COEFF_A, + .b = COEFF_B, + }, +}; + +static const struct lvts_data mt8192_lvts_ap_data = { + .num_tc = (ARRAY_SIZE(mt8192_tc_ap_settings)), + .tc = mt8192_tc_ap_settings, + .num_sensor = MT8192_NUM_TS_AP, + .ops = { + .efuse_to_cal_data = mt8192_ap_efuse_to_cal_data, + .device_enable_and_init = lvts_device_enable_and_init, + .device_enable_auto_rck = lvts_device_enable_auto_rck_v4, + .device_read_count_rc_n = lvts_device_read_count_rc_n_v4, + .set_cal_data = lvts_set_calibration_data_v4, + .init_controller = lvts_init_controller_v4, + }, + .feature_bitmap = FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr = NUM_EFUSE_ADDR, + .num_efuse_block = NUM_EFUSE_BLOCK_MT8192, + .cal_data = { + .default_golden_temp = DEFAULT_GOLDEN_TEMP, + .default_count_r = DEFAULT_CUONT_R, + .default_count_rc = DEFAULT_CUONT_RC, + }, + .coeff = { + .a = COEFF_A, + .b = COEFF_B, + }, +}; + +static const struct of_device_id lvts_of_match[] = { + { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data, }, + { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data, }, + {}, +}; +MODULE_DEVICE_TABLE(of, lvts_of_match); + +static struct platform_driver soc_temp_lvts = { + .probe = lvts_probe, + .remove = lvts_remove, + .suspend = lvts_suspend, + .resume = lvts_resume, + .shutdown = lvts_shutdown, + .driver = { + .name = "mtk-lvts-thermal-v4", + .of_match_table = lvts_of_match, + }, +}; +module_platform_driver(soc_temp_lvts); + +MODULE_AUTHOR("Yu-Chia Chang "); +MODULE_AUTHOR("Michael Kao "); +MODULE_DESCRIPTION("MediaTek LVTS V4 Thermal Driver"); +MODULE_LICENSE("GPL"); From patchwork Wed Aug 17 08:07:55 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a54d610e5fsm1391992wmq.26.2022.08.17.01.08.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 01:08:50 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v9,5/7] arm64: dts: mt8195: Add efuse node to mt8195 Date: Wed, 17 Aug 2022 10:07:55 +0200 Message-Id: <20220817080757.352021-6-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220817080757.352021-1-bchihi@baylibre.com> References: <20220817080757.352021-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Alexandre Bailon Add efuse node. This will be required by the thermal driver to get the calibration data. Signed-off-by: Alexandre Bailon Co-developed-by: Balsam CHIHI Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 066c14989708..95967a0196d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -733,6 +733,18 @@ u2_intr_p3: usb2-intr-p3@189,2 { reg = <0x189 0x2>; bits = <7 5>; }; + + lvts_efuse_data1: lvts1-calib@1bc { + reg = <0x1bc 0x14>; + }; + + lvts_efuse_data2: lvts2-calib@1d0 { + reg = <0x1d0 0x38>; + }; + + svs_calibration: calib@580 { + reg = <0x580 0x64>; + }; }; u3phy2: t-phy@11c40000 { From patchwork Wed Aug 17 08:07:56 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balsam CHIHI X-Patchwork-Id: 598046 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 962EDC2BB41 for ; Wed, 17 Aug 2022 08:09:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234003AbiHQIJA (ORCPT ); Wed, 17 Aug 2022 04:09:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58376 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233916AbiHQIIz (ORCPT ); Wed, 17 Aug 2022 04:08:55 -0400 Received: from mail-wm1-x331.google.com (mail-wm1-x331.google.com [IPv6:2a00:1450:4864:20::331]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EF95C52806 for ; Wed, 17 Aug 2022 01:08:53 -0700 (PDT) Received: by mail-wm1-x331.google.com with SMTP id p12-20020a7bcc8c000000b003a5360f218fso590719wma.3 for ; Wed, 17 Aug 2022 01:08:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20210112.gappssmtp.com; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc; bh=vqBN/1lbDDUExS5IZ7DoqaWZVSkfYt/y1o6RlIQJrH0=; b=uf6YkzyFQ14zCs70XWWzM9dZH85T8/q1k7HQueBM2LvFHPbhfDqQ3HCMcckugNviMF F3NTw3U9cE6D3PKUY4SiDVjpZPa/l28lAxVKqhMxhJFRdj+TPItJoKMYa84Wb5Gs+61i 5quMuW8tDoJQE+FKH5KhTQif+vaYwz/xadhYpKJZbqwlXcscHpegS/HlXIfHsdK2uWiI YMaAR9BDfwnVGAd9HgjVPCBBymXtyUMZVC5AvYv3307rNL5mDFZATXExEwpBcsWeb6hB bRxJGncCU4QJ3pHX9TvxeDwLDuXSkwfKs9OTcDZ+Dhv8rcaYIAJa2oT4l5ToHsr2dz9Q CWbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc; bh=vqBN/1lbDDUExS5IZ7DoqaWZVSkfYt/y1o6RlIQJrH0=; b=vwA7+AYFUdQKa4wVSM/mMovT1gBWfrfvv2c+m1zW+0lFaiJaqM+3+ITQsqg5VULXWd GgHT4GQXLHSx9Wj+/lGg/v+eemYZc3MNZyyRh2g/tlP68Dc4pGcCF5tRgrwfpvmZj7aS 9eJp4X5W1rdWqE5UlVDwP46+DH0719OiTNqV70Ym0diJr0nGpxbuHyoXCF+Ktmez0gz2 qg4ilf6vrCF1L4tva2l1uLCVrcgAbTsfzkhYWPKpV12/sIRzkQB7U/eqllFNv+ctTUaz KRxtTTLGghI5aKqj7yWBlEVB4nLdbDdZ0W7d+4VgisSac15PaTMEGajXh9yAHHJYnjeg sRkQ== X-Gm-Message-State: ACgBeo1/7uceQOZJE51nkvFque13A2b7PXXfyw+Tpmri5yONxJp31qFA VTXbelxDXqm+y8Ug/9nm5MC6Ng== X-Google-Smtp-Source: AA6agR7xyAkug/0FUS2iV/tqnv/KSc31hp2N9qhVSWYwlEjmgU4SC/wDn1yaJLlWRb74RXcsko3bfA== X-Received: by 2002:a05:600c:1497:b0:3a5:f608:d765 with SMTP id c23-20020a05600c149700b003a5f608d765mr1264422wmh.19.1660723732364; Wed, 17 Aug 2022 01:08:52 -0700 (PDT) Received: from Balsam-ThinkPad-T480.civfrance.com (58.188.158.77.rev.sfr.net. [77.158.188.58]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a54d610e5fsm1391992wmq.26.2022.08.17.01.08.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 01:08:51 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v9,6/7] arm64: dts: mt8195: Add thermal zones and thermal nodes Date: Wed, 17 Aug 2022 10:07:56 +0200 Message-Id: <20220817080757.352021-7-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220817080757.352021-1-bchihi@baylibre.com> References: <20220817080757.352021-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Tinghan Shen Add thermal zones and thermal nodes for the mt8195. Signed-off-by: Tinghan Shen Co-developed-by: Ben Tseng Signed-off-by: Ben Tseng Co-developed-by: Alexandre Bailon Signed-off-by: Alexandre Bailon Co-developed-by: Balsam CHIHI Signed-off-by: Balsam CHIHI --- arch/arm64/boot/dts/mediatek/mt8195.dtsi | 111 +++++++++++++++++++++++ 1 file changed, 111 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 95967a0196d8..aafbbe83e6ba 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { compatible = "mediatek,mt8195"; @@ -452,6 +453,28 @@ spi0: spi@1100a000 { status = "disabled"; }; + lvts_ap: thermal-sensor@1100b000 { + compatible = "mediatek,mt8195-lvts-ap"; + #thermal-sensor-cells = <1>; + reg = <0 0x1100b000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST0_THERM_CTRL_SWRST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2"; + }; + + lvts_mcu: thermal-sensor@11278000 { + compatible = "mediatek,mt8195-lvts-mcu"; + #thermal-sensor-cells = <1>; + reg = <0 0x11278000 0 0x1000>; + interrupts = ; + clocks = <&infracfg_ao CLK_INFRA_AO_THERM>; + resets = <&infracfg_ao MT8195_INFRA_RST4_THERM_CTRL_MCU_SWRST>; + nvmem-cells = <&lvts_efuse_data1 &lvts_efuse_data2>; + nvmem-cell-names = "lvts_calib_data1", "lvts_calib_data2"; + }; + spi1: spi@11010000 { compatible = "mediatek,mt8195-spi", "mediatek,mt6765-spi"; @@ -1106,4 +1129,92 @@ vencsys_core1: clock-controller@1b000000 { #clock-cells = <1>; }; }; + + thermal_zones: thermal-zones { + cpu0-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 0>; + }; + cpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 1>; + }; + cpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 2>; + }; + cpu3-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 3>; + }; + cpu4-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 4>; + }; + cpu5-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 5>; + }; + cpu6-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 6>; + }; + cpu7-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_mcu 7>; + }; + vpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 0>; + }; + vpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 1>; + }; + gpu1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 2>; + }; + gpu2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 3>; + }; + vdec-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 4>; + }; + img-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 5>; + }; + infra-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 6>; + }; + cam1-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 7>; + }; + cam2-thermal { + polling-delay = <0>; + polling-delay-passive = <0>; + thermal-sensors = <&lvts_ap 8>; + }; + }; }; From patchwork Wed Aug 17 08:07:57 2022 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Balsam CHIHI X-Patchwork-Id: 598045 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id EC57CC32772 for ; Wed, 17 Aug 2022 08:09:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234035AbiHQIJB (ORCPT ); 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[77.158.188.58]) by smtp.gmail.com with ESMTPSA id u15-20020a05600c19cf00b003a54d610e5fsm1391992wmq.26.2022.08.17.01.08.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 17 Aug 2022 01:08:53 -0700 (PDT) From: bchihi@baylibre.com To: rafael@kernel.org, rui.zhang@intel.com, daniel.lezcano@linaro.org, amitk@kernel.org Cc: linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, khilman@baylibre.com, mka@chromium.org, robh+dt@kernel.org, krzk+dt@kernel.org, matthias.bgg@gmail.com, p.zabel@pengutronix.de, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, james.lo@mediatek.com, fan.chen@mediatek.com, louis.yu@mediatek.com, rex-bc.chen@mediatek.com, abailon@baylibre.com Subject: [PATCH v9, 7/7] thermal: mediatek: Add LVTS driver settings for mt8195 thermal zones Date: Wed, 17 Aug 2022 10:07:57 +0200 Message-Id: <20220817080757.352021-8-bchihi@baylibre.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220817080757.352021-1-bchihi@baylibre.com> References: <20220817080757.352021-1-bchihi@baylibre.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org From: Michael Kao Add LVTS v4 (Low Voltage Thermal Sensor) driver settings to report junction temperatures in MediaTek SoC mt8195 and register the maximum temperature of sensors and each sensor as a thermal zone. Signed-off-by: Michael Kao Co-developed-by: Ben Tseng Signed-off-by: Ben Tseng Co-developed-by: Alexandre Bailon Signed-off-by: Alexandre Bailon Co-developed-by: Balsam CHIHI Signed-off-by: Balsam CHIHI --- drivers/thermal/mediatek/lvts_thermal.h | 1 + drivers/thermal/mediatek/lvts_v4.c | 230 ++++++++++++++++++++++++ 2 files changed, 231 insertions(+) diff --git a/drivers/thermal/mediatek/lvts_thermal.h b/drivers/thermal/mediatek/lvts_thermal.h index a94ce46acccd..059b1eb98b1c 100644 --- a/drivers/thermal/mediatek/lvts_thermal.h +++ b/drivers/thermal/mediatek/lvts_thermal.h @@ -16,6 +16,7 @@ #define FEATURE_DEVICE_AUTO_RCK BIT(0) #define NUM_EFUSE_ADDR 22 #define NUM_EFUSE_BLOCK_MT8192 1 +#define NUM_EFUSE_BLOCK_MT8195 2 #define DEFAULT_GOLDEN_TEMP 50 #define DEFAULT_CUONT_R 35000 #define DEFAULT_CUONT_RC 2750 diff --git a/drivers/thermal/mediatek/lvts_v4.c b/drivers/thermal/mediatek/lvts_v4.c index 3dc00d2589f9..41473312b644 100644 --- a/drivers/thermal/mediatek/lvts_v4.c +++ b/drivers/thermal/mediatek/lvts_v4.c @@ -32,6 +32,31 @@ enum mt8192_lvts_ap_sensor_enum { MT8192_NUM_TS_AP }; +enum mt8195_lvts_mcu_sensor_enum { + MT8195_TS1_0, // cpu_big1 + MT8195_TS1_1, // cpu_big2 + MT8195_TS2_0, // cpu_big3 + MT8195_TS2_1, // cpu_big4 + MT8195_TS3_0, // cpu_little1 + MT8195_TS3_1, // cpu_little2 + MT8195_TS3_2, // cpu_little3 + MT8195_TS3_3, // cpu_little4 + MT8195_NUM_TS_MCU +}; + +enum mt8195_lvts_ap_sensor_enum { + MT8195_TS4_0, // vpu1 + MT8195_TS4_1, // vpu2 + MT8195_TS5_0, // gpu1 + MT8195_TS5_1, // gpu2 + MT8195_TS6_0, // vdec + MT8195_TS6_1, // img + MT8195_TS6_2, // infra + MT8195_TS7_0, // cam1 + MT8195_TS7_1, // cam2 + MT8195_NUM_TS_AP +}; + static void mt8192_mcu_efuse_to_cal_data(struct lvts_data *lvts_data) { const unsigned int mt8192_ts[] = { MT8192_TS2_0, MT8192_TS3_0 }; @@ -74,6 +99,60 @@ static void mt8192_ap_efuse_to_cal_data(struct lvts_data *lvts_data) } } +static void mt8195_mcu_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct lvts_sensor_cal_data *cal_data = &lvts_data->cal_data; + + cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, lvts_data, 31, 24); + + cal_data->count_r[MT8195_TS1_0] = GET_CAL_DATA_BITMASK(1, lvts_data, 23, 0); + cal_data->count_r[MT8195_TS1_1] = (GET_CAL_DATA_BITMASK(2, lvts_data, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(1, lvts_data, 31, 24); + cal_data->count_r[MT8195_TS2_0] = GET_CAL_DATA_BITMASK(3, lvts_data, 31, 8); + cal_data->count_r[MT8195_TS2_1] = GET_CAL_DATA_BITMASK(4, lvts_data, 23, 0); + cal_data->count_r[MT8195_TS3_0] = (GET_CAL_DATA_BITMASK(6, lvts_data, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(5, lvts_data, 31, 16); + cal_data->count_r[MT8195_TS3_1] = GET_CAL_DATA_BITMASK(6, lvts_data, 31, 8); + cal_data->count_r[MT8195_TS3_2] = GET_CAL_DATA_BITMASK(7, lvts_data, 23, 0); + cal_data->count_r[MT8195_TS3_3] = (GET_CAL_DATA_BITMASK(8, lvts_data, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(7, lvts_data, 31, 24); + + cal_data->count_rc[MT8195_TS1_0] = (GET_CAL_DATA_BITMASK(3, lvts_data, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(2, lvts_data, 31, 16); + cal_data->count_rc[MT8195_TS2_0] = (GET_CAL_DATA_BITMASK(5, lvts_data, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(4, lvts_data, 31, 24); + cal_data->count_rc[MT8195_TS3_0] = (GET_CAL_DATA_BITMASK(9, lvts_data, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(8, lvts_data, 31, 16); +} + +static void mt8195_ap_efuse_to_cal_data(struct lvts_data *lvts_data) +{ + struct lvts_sensor_cal_data *cal_data = &lvts_data->cal_data; + + cal_data->golden_temp = GET_CAL_DATA_BITMASK(0, lvts_data, 31, 24); + + cal_data->count_r[MT8195_TS4_0] = GET_CAL_DATA_BITMASK(9, lvts_data, 31, 8); + cal_data->count_r[MT8195_TS4_1] = GET_CAL_DATA_BITMASK(10, lvts_data, 23, 0); + cal_data->count_r[MT8195_TS5_0] = (GET_CAL_DATA_BITMASK(12, lvts_data, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(11, lvts_data, 31, 16); + cal_data->count_r[MT8195_TS5_1] = GET_CAL_DATA_BITMASK(12, lvts_data, 31, 8); + cal_data->count_r[MT8195_TS6_0] = (GET_CAL_DATA_BITMASK(14, lvts_data, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(13, lvts_data, 31, 24); + cal_data->count_r[MT8195_TS6_1] = (GET_CAL_DATA_BITMASK(15, lvts_data, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(14, lvts_data, 31, 16); + cal_data->count_r[MT8195_TS6_2] = GET_CAL_DATA_BITMASK(15, lvts_data, 31, 8); + cal_data->count_r[MT8195_TS7_0] = (GET_CAL_DATA_BITMASK(17, lvts_data, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(16, lvts_data, 31, 24); + cal_data->count_r[MT8195_TS7_1] = (GET_CAL_DATA_BITMASK(18, lvts_data, 7, 0) << 16) + + GET_CAL_DATA_BITMASK(17, lvts_data, 31, 16); + + cal_data->count_rc[MT8195_TS4_0] = (GET_CAL_DATA_BITMASK(11, lvts_data, 15, 0) << 8) + + GET_CAL_DATA_BITMASK(10, lvts_data, 31, 24); + cal_data->count_rc[MT8195_TS5_0] = GET_CAL_DATA_BITMASK(13, lvts_data, 23, 0); + cal_data->count_rc[MT8195_TS6_0] = GET_CAL_DATA_BITMASK(16, lvts_data, 23, 0); + cal_data->count_rc[MT8195_TS7_0] = GET_CAL_DATA_BITMASK(18, lvts_data, 31, 8); +} + static struct lvts_speed_settings tc_speed_mt8192 = { .period_unit = PERIOD_UNIT, .group_interval_delay = GROUP_INTERVAL_DELAY, @@ -81,6 +160,13 @@ static struct lvts_speed_settings tc_speed_mt8192 = { .sensor_interval_delay = SENSOR_INTERVAL_DELAY, }; +static struct lvts_speed_settings tc_speed_mt8195 = { + .period_unit = PERIOD_UNIT, + .group_interval_delay = GROUP_INTERVAL_DELAY, + .filter_interval_delay = FILTER_INTERVAL_DELAY, + .sensor_interval_delay = SENSOR_INTERVAL_DELAY, +}; + static const struct lvts_tc_settings mt8192_tc_mcu_settings[] = { [0] = { .dev_id = 0x81, @@ -171,6 +257,96 @@ static const struct lvts_tc_settings mt8192_tc_ap_settings[] = { } }; +static const struct lvts_tc_settings mt8195_tc_mcu_settings[] = { + [0] = { + .dev_id = 0x81, + .addr_offset = 0x0, + .num_sensor = 2, + .ts_offset = 0, + .sensor_map = { MT8195_TS1_0, MT8195_TS1_1 }, + .tc_speed = &tc_speed_mt8195, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(3), + }, + [1] = { + .dev_id = 0x82, + .addr_offset = 0x100, + .num_sensor = 2, + .ts_offset = 0, + .sensor_map = { MT8195_TS2_0, MT8195_TS2_1 }, + .tc_speed = &tc_speed_mt8195, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(4), + }, + [2] = { + .dev_id = 0x83, + .addr_offset = 0x200, + .num_sensor = 4, + .ts_offset = 0, + .sensor_map = { MT8195_TS3_0, MT8195_TS3_1, MT8195_TS3_2, MT8195_TS3_3 }, + .tc_speed = &tc_speed_mt8195, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(5), + } +}; + +static const struct lvts_tc_settings mt8195_tc_ap_settings[] = { + [0] = { + .dev_id = 0x84, + .addr_offset = 0x0, + .num_sensor = 2, + .ts_offset = 0, + .sensor_map = { MT8195_TS4_0, MT8195_TS4_1 }, + .tc_speed = &tc_speed_mt8195, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(3), + }, + [1] = { + .dev_id = 0x85, + .addr_offset = 0x100, + .num_sensor = 2, + .ts_offset = 0, + .sensor_map = { MT8195_TS5_0, MT8195_TS5_1 }, + .tc_speed = &tc_speed_mt8195, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(4), + }, + [2] = { + .dev_id = 0x86, + .addr_offset = 0x200, + .num_sensor = 3, + .ts_offset = 0, + .sensor_map = { MT8195_TS6_0, MT8195_TS6_1, MT8195_TS6_2 }, + .tc_speed = &tc_speed_mt8195, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT1, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(5), + }, + [3] = { + .dev_id = 0x87, + .addr_offset = 0x300, + .num_sensor = 2, + .ts_offset = 0, + .sensor_map = { MT8195_TS7_0, MT8195_TS7_1 }, + .tc_speed = &tc_speed_mt8195, + .hw_filter = LVTS_FILTER_2_OF_4, + .dominator_sensing_point = SENSING_POINT0, + .hw_reboot_trip_point = HW_REBOOT_TRIP_POINT, + .irq_bit = BIT(6), + } +}; + static const struct lvts_data mt8192_lvts_mcu_data = { .num_tc = (ARRAY_SIZE(mt8192_tc_mcu_settings)), .tc = mt8192_tc_mcu_settings, @@ -223,9 +399,63 @@ static const struct lvts_data mt8192_lvts_ap_data = { }, }; +static const struct lvts_data mt8195_lvts_mcu_data = { + .num_tc = (ARRAY_SIZE(mt8195_tc_mcu_settings)), + .tc = mt8195_tc_mcu_settings, + .num_sensor = MT8195_NUM_TS_MCU, + .ops = { + .efuse_to_cal_data = mt8195_mcu_efuse_to_cal_data, + .device_enable_and_init = lvts_device_enable_and_init, + .device_enable_auto_rck = lvts_device_enable_auto_rck_v4, + .device_read_count_rc_n = lvts_device_read_count_rc_n_v4, + .set_cal_data = lvts_set_calibration_data_v4, + .init_controller = lvts_init_controller_v4, + }, + .feature_bitmap = FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr = NUM_EFUSE_ADDR, + .num_efuse_block = NUM_EFUSE_BLOCK_MT8195, + .cal_data = { + .default_golden_temp = DEFAULT_GOLDEN_TEMP, + .default_count_r = DEFAULT_CUONT_R, + .default_count_rc = DEFAULT_CUONT_RC, + }, + .coeff = { + .a = COEFF_A, + .b = COEFF_B, + }, +}; + +static const struct lvts_data mt8195_lvts_ap_data = { + .num_tc = (ARRAY_SIZE(mt8195_tc_ap_settings)), + .tc = mt8195_tc_ap_settings, + .num_sensor = MT8195_NUM_TS_AP, + .ops = { + .efuse_to_cal_data = mt8195_ap_efuse_to_cal_data, + .device_enable_and_init = lvts_device_enable_and_init, + .device_enable_auto_rck = lvts_device_enable_auto_rck_v4, + .device_read_count_rc_n = lvts_device_read_count_rc_n_v4, + .set_cal_data = lvts_set_calibration_data_v4, + .init_controller = lvts_init_controller_v4, + }, + .feature_bitmap = FEATURE_DEVICE_AUTO_RCK, + .num_efuse_addr = NUM_EFUSE_ADDR, + .num_efuse_block = NUM_EFUSE_BLOCK_MT8195, + .cal_data = { + .default_golden_temp = DEFAULT_GOLDEN_TEMP, + .default_count_r = DEFAULT_CUONT_R, + .default_count_rc = DEFAULT_CUONT_RC, + }, + .coeff = { + .a = COEFF_A, + .b = COEFF_B, + }, +}; + static const struct of_device_id lvts_of_match[] = { { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data, }, { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data, }, + { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data, }, + { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data, }, {}, }; MODULE_DEVICE_TABLE(of, lvts_of_match);