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[81.133.38.158]) by smtp.gmail.com with ESMTPSA id z9sm22283025wrs.63.2019.02.04.05.12.35 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 04 Feb 2019 05:12:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 4 Feb 2019 13:12:25 +0000 Message-Id: <20190204131228.25949-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190204131228.25949-1-richard.henderson@linaro.org> References: <20190204131228.25949-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32a Subject: [Qemu-devel] [PATCH v3 1/4] fixup! target/arm: Cache the GP bit for a page in MemTxAttrs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" We talked about changing this, but missed when applying to target-arm.next. --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/helper.c b/target/arm/helper.c index 2edf84b898..be0ec7de2a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10757,7 +10757,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, } /* Merge in attributes from table descriptors */ attrs |= nstable << 3; /* NS */ - guarded |= extract64(descriptor, 50, 1); /* GP */ + guarded = extract64(descriptor, 50, 1); /* GP */ if (param.hpd) { /* HPD disables all the table attributes except NSTable. */ break; From patchwork Mon Feb 4 13:12:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157410 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3913741jaa; Mon, 4 Feb 2019 05:25:16 -0800 (PST) X-Google-Smtp-Source: AHgI3IbEPRzq4SfoL3KXsv0LQf4J3dCQdElodwLic4MlvA3KxGKj16rFdYDGfXIFXqAWNV9yiYwh X-Received: by 2002:a25:da12:: with SMTP id n18mr4968867ybf.236.1549286716372; Mon, 04 Feb 2019 05:25:16 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549286716; cv=none; d=google.com; s=arc-20160816; b=UhTQiUkqm7FnWH1icZ+bBcjkm0zV1cBXAKAdc4hamBCI2L6LZduXSaWaqLl7hhk4M3 D+OpesQtX76Lxg0MZXXY8zxwqZfM9Gxk6YdaWlB5iPFs821+CIvnKrrfO+rhbiNxfG95 6wBdrAiydg+tQuyvOmd+EW3Pm9ns+LO1coSYgVEDNfpDEVKcEdNw79GPoAFl5EQDA370 eZMgDJUo+IBNqVmUSjFvi0CaaEoNa8PL/usKMGVJlSq8CkFJrIW4C0tlxbg0Hzc1AHqQ KpHk4/sWS4blOiK0qJhelfQJgVlD3FDYWiCrDn4OvLkblz0psi1vH3v/NhjtHlINSA5j X/Fw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=gn75mc+OMgblL2fopLWb2r86Mz9qxLDmnmE1KtGd/sQ=; b=bYrYrm0MQIqQIrMN5I3fwYcy5WTQSugD5USfzvbT3A2qT7heqkDvUZJC/4gKW6C3xp eI3LxSpfutFl6PIb/kKkTW9jH7MsZTEVqnxVKHXt9CHwgCt59SodmeRznSXpXm43J6D7 4AWIF/NDG+worrFO2+sazUPFOsQ5b2h1/tr1JWFq6TUQvgNXbMcj9KQgpIaewtrSA3eH YtPcAvCoLriVe7Pgl5kpJmQ9u2Ylmb0VCDDPXxKmfJOLDkmibBYpVURTqqmQjG54pCLc OACqE32gA6VERLpp6ey2lsuLmL25JYmfbCPVcZfU6FdLPcFaqeyypWwws21MIliCmn8c yAQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=D8POpQhm; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.133.38.158]) by smtp.gmail.com with ESMTPSA id z9sm22283025wrs.63.2019.02.04.05.12.36 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 04 Feb 2019 05:12:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 4 Feb 2019 13:12:26 +0000 Message-Id: <20190204131228.25949-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190204131228.25949-1-richard.henderson@linaro.org> References: <20190204131228.25949-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 Subject: [Qemu-devel] [PATCH v3 2/4] target/arm: Add x-guarded-pages cpu property for user-only X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" While waiting for a proper userland ABI, allow static test cases to be written assuming that GP is set for all pages. Signed-off-by: Richard Henderson --- v2: Renamed the property with x- prefix --- target/arm/cpu.h | 4 ++++ target/arm/cpu64.c | 20 ++++++++++++++++++++ target/arm/translate-a64.c | 8 +++++++- 3 files changed, 31 insertions(+), 1 deletion(-) -- 2.17.2 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1ff7197efd..366ab97db3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -900,6 +900,10 @@ struct ARMCPU { */ bool cfgend; +#ifdef CONFIG_USER_ONLY + bool guarded_pages; +#endif + QLIST_HEAD(, ARMELChangeHook) pre_el_change_hooks; QLIST_HEAD(, ARMELChangeHook) el_change_hooks; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eff0f164dd..c5675fe7d1 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -281,6 +281,20 @@ static void cpu_max_set_sve_vq(Object *obj, Visitor *v, const char *name, error_propagate(errp, err); } +#ifdef CONFIG_USER_ONLY +static bool aarch64_cpu_get_guarded_pages(Object *obj, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + return cpu->guarded_pages; +} + +static void aarch64_cpu_set_guarded_pages(Object *obj, bool val, Error **errp) +{ + ARMCPU *cpu = ARM_CPU(obj); + cpu->guarded_pages = val; +} +#endif + /* -cpu max: if KVM is enabled, like -cpu host (best possible with this host); * otherwise, a CPU with as many features enabled as our emulation supports. * The version of '-cpu max' for qemu-system-arm is defined in cpu.c; @@ -360,6 +374,12 @@ static void aarch64_max_initfn(Object *obj) */ cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */ cpu->dcz_blocksize = 7; /* 512 bytes */ + + object_property_add_bool(obj, "x-guarded-pages", + aarch64_cpu_get_guarded_pages, + aarch64_cpu_set_guarded_pages, NULL); + object_property_set_description(obj, "x-guarded-pages", + "Set on/off GuardPage bit for all pages", NULL); #endif cpu->sve_max_vq = ARM_MAX_VQ; diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7375ebf7a9..37077138e3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -13817,7 +13817,13 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) static bool is_guarded_page(CPUARMState *env, DisasContext *s) { #ifdef CONFIG_USER_ONLY - return false; /* FIXME */ + /* + * FIXME: What is the userland ABI for this? + * For the moment this is controlled by an attribute: + * -cpu max,guarded_pages=on. + */ + ARMCPU *cpu = arm_env_get_cpu(env); + return cpu->guarded_pages; #else uint64_t addr = s->base.pc_first; int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); From patchwork Mon Feb 4 13:12:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157416 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3922432jaa; Mon, 4 Feb 2019 05:34:05 -0800 (PST) X-Google-Smtp-Source: ALg8bN54gBKbxPGs5ll+C5ZhjzJ+62Bm+Tf/tlmJon2lZbyc+91xXDXwk4jLHLvJMe2w/rT0sfV1 X-Received: by 2002:a81:9ad8:: with SMTP id r207mr47355494ywg.72.1549287245782; Mon, 04 Feb 2019 05:34:05 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549287245; cv=none; d=google.com; s=arc-20160816; b=yyeARcIpxgxdXcol0sADgPzEZtQDIrS1/mr7rCAe8mPmrW0D1/XnUDMjVp3O+Ma48T Q3/6rZI6lObpKjjhi8jX8Ui7MkldaGlIZ93R9oYSxY62edy/qao3sYVhQBvv2hxDF+MX 7aamAEk/85WBtchhz6ELmUYCKBdLb95/VfI3q96rNe719VUANpw0f5dQUhP81X1VJz0u QV92975KhxDPSN702GdOq9Vb7CoSII0/m4pK43hBx6FQ9gxkVvhPoZJMkr+HTLzvbNTz w8hRacpntHMBBWyC/9ihRYQS9CuU0Yh0tQf0m2inmJO5n3zZQn0llty90sPXihI/xlcC Py7Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=1yNoac1ShBnXw/zdOxjpmLH8NTh7CPRm4nWUT3FtlnU=; b=LpNjxmJEIlTo/azTfcxFqfbMQq+H9iW2PN/gsxFaKMzR7TBopEaT24cju3Rx2ytEml +pc/csfifG9xkueEUlv9uqPxmkdMdYmg6/XW14Y8oVZRyGQNuVTOEHcOuXvfAOatURlA 81IybxhKeBF2Oe/i7oil4jJ3llEnf1wYSWvkeADeIbhbZY9her4DLj8wIzzxELe5ewqG VX5Gc/HBUeSc757QXtbcpuGeguUJP/SMFyxR21qLqDGa8E+4Tj+cAqVMeXOgMocC5JrF 17HijoJMmM4pk5q5itmwBqdn41g5r9afpVLrkZf1eu0ttPtTPaQvyrqi2YoMvD3WIDjT v2CA== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=X4aMjpUz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.133.38.158]) by smtp.gmail.com with ESMTPSA id z9sm22283025wrs.63.2019.02.04.05.12.37 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 04 Feb 2019 05:12:38 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 4 Feb 2019 13:12:27 +0000 Message-Id: <20190204131228.25949-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190204131228.25949-1-richard.henderson@linaro.org> References: <20190204131228.25949-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 Subject: [Qemu-devel] [PATCH v3 3/4] linux-user/aarch64: Reset btype for syscalls and signals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The value of btype for syscalls is CONSTRAINED UNPREDICTABLE, so we need to make sure that the value is 0 before clone, fork, or syscall return. The value of btype for signals is defined, but it does not make sense for a SIGILL handler to enter with the btype set as for the indirect branch that caused the SIGILL. Clearing the value early means that btype is zero within the pstate saved into the signal frame, and so is also zero on (normal) signal return, but also allows the signal handler to adjust the value as seen after the sigcontext restore. This last is a guess at a future kernel's user-space ABI. Signed-off-by: Richard Henderson --- v3: Do not clear btype for semihost. --- linux-user/aarch64/cpu_loop.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) -- 2.17.2 diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index d75fd9d3e2..3f046dbbd7 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -83,8 +83,19 @@ void cpu_loop(CPUARMState *env) cpu_exec_end(cs); process_queued_cpu_work(cs); + /* + * The state of BTYPE on syscall and interrupt entry is CONSTRAINED + * UNPREDICTABLE. The real kernel will need to tidy this up as well. + * Do this before syscalls and signals, so that the value is correct + * both within signal handlers, and on return from syscall (especially + * clone & fork) and from signal handlers. + * + * The SIGILL signal handler, for BTITrap, can see the failing BTYPE + * within the ESR value in the signal frame. + */ switch (trapnr) { case EXCP_SWI: + env->btype = 0; ret = do_syscall(env, env->xregs[8], env->xregs[0], @@ -104,6 +115,7 @@ void cpu_loop(CPUARMState *env) /* just indicate that signals should be handled asap */ break; case EXCP_UDEF: + env->btype = 0; info.si_signo = TARGET_SIGILL; info.si_errno = 0; info.si_code = TARGET_ILL_ILLOPN; @@ -112,6 +124,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: + env->btype = 0; info.si_signo = TARGET_SIGSEGV; info.si_errno = 0; /* XXX: check env->error_code */ @@ -121,6 +134,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_DEBUG: case EXCP_BKPT: + env->btype = 0; info.si_signo = TARGET_SIGTRAP; info.si_errno = 0; info.si_code = TARGET_TRAP_BRKPT; From patchwork Mon Feb 4 13:12:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 157415 Delivered-To: patch@linaro.org Received: by 2002:a02:48:0:0:0:0:0 with SMTP id 69csp3918929jaa; Mon, 4 Feb 2019 05:30:58 -0800 (PST) X-Google-Smtp-Source: ALg8bN7Yra/7fInGkr3MYgghukcj03H7UeGOBbn5mbWpBK6NUjGCENCqj6aRDzg67jzLxi83PYa9 X-Received: by 2002:a81:78cc:: with SMTP id t195mr49051891ywc.387.1549287058061; Mon, 04 Feb 2019 05:30:58 -0800 (PST) ARC-Seal: i=1; a=rsa-sha256; t=1549287058; cv=none; d=google.com; s=arc-20160816; b=Jd3h7NJSbn/vDhO7AKNTdPbrVwwNs9HYiOtbkTweuadl9ZjWsHPUSSKFreYxUP+UUi dpT/4DGDO9h3Zd7EHMTD+GklPKbYlGYIMspJJmwEqp3Q1ubz/EC/aES5n/kAvz39mVst Xl6lVseY26sECbLTA7mIEHEpqB9RLREiE6lKRffPk/DTkS25aiVGXWYyrG5Vg1VfDH3V ljcZ3zqKVeJB1QXB6lxFnj7lgaAmzjiuLyqIQgee+ezeT7aTlvN3VxpHiN8V6EASYhUe fG0Qa9xfOXuIdpDUqNOJ0aMZkVhSzjdryAvApFv8zubcQ4MaSG9la3duhjBUUvL+usIF uNRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=y0k/H38xJNqLR/HphofIOtky77ujQ33o+YBmpOTNSTs=; b=lbyy/bsGi0fyNQlbAg/fxtjNLMInEXPLl5dNrnW4OCZCtXl0yW38RIIXQGAMw5rdzT 0Ns9KsT2Pn4RkOTswSlFHI8DjFw1e2nIqIv5RP5o2HMwlmEjCc47AODpKHRKg11SXnc7 r/gTidJBlXhExvr0EKHozMF/JDay2O0cHBkQoveNh8XJ9FlAjuhxJgFu2sM42JQq9cnS CL9DWU48NLDFw/Vt8eN/uvOh1JgzypFNGmKEJUu6j0gtVho7r2o6h5WI3rtwJOfycUZb QsNVeF9Otn5yQdKYkfxbDQnlM1foG5PatwpG+i51it8QKFuJvjW5YTBNdKjoZ49IUSDT cetg== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=DF6goOZP; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[81.133.38.158]) by smtp.gmail.com with ESMTPSA id z9sm22283025wrs.63.2019.02.04.05.12.39 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 04 Feb 2019 05:12:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Date: Mon, 4 Feb 2019 13:12:28 +0000 Message-Id: <20190204131228.25949-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.2 In-Reply-To: <20190204131228.25949-1-richard.henderson@linaro.org> References: <20190204131228.25949-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 Subject: [Qemu-devel] [PATCH v3 4/4] tests/tcg/aarch64: Add bti smoke test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Richard Henderson --- tests/tcg/aarch64/bti-1.c | 61 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/bti-crt.inc.c | 51 ++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 7 +++- 3 files changed, 118 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/bti-1.c create mode 100644 tests/tcg/aarch64/bti-crt.inc.c -- 2.17.2 diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c new file mode 100644 index 0000000000..fa8a521a47 --- /dev/null +++ b/tests/tcg/aarch64/bti-1.c @@ -0,0 +1,61 @@ +/* + * Branch target identification, basic notskip cases. + */ + +#include "bti-crt.inc.c" + +static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) +{ + uc->uc_mcontext.pc += 8; +} + +#define NOP "nop" +#define BTI_N "hint #32" +#define BTI_C "hint #34" +#define BTI_J "hint #36" +#define BTI_JC "hint #38" + +#define BTYPE_1(DEST) \ + asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x16") + +#define BTYPE_2(DEST) \ + asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x16", "x30") + +#define BTYPE_3(DEST) \ + asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x15") + +#define TEST(WHICH, DEST, EXPECT) \ + do { WHICH(DEST); fail += skipped ^ EXPECT; } while (0) + + +int main() +{ + int fail = 0; + int skipped; + + /* Signal-like with SA_SIGINFO. */ + signal_info(SIGILL, skip2_sigill); + + TEST(BTYPE_1, NOP, 1); + TEST(BTYPE_1, BTI_N, 1); + TEST(BTYPE_1, BTI_C, 0); + TEST(BTYPE_1, BTI_J, 0); + TEST(BTYPE_1, BTI_JC, 0); + + TEST(BTYPE_2, NOP, 1); + TEST(BTYPE_2, BTI_N, 1); + TEST(BTYPE_2, BTI_C, 0); + TEST(BTYPE_2, BTI_J, 1); + TEST(BTYPE_2, BTI_JC, 0); + + TEST(BTYPE_3, NOP, 1); + TEST(BTYPE_3, BTI_N, 1); + TEST(BTYPE_3, BTI_C, 1); + TEST(BTYPE_3, BTI_J, 0); + TEST(BTYPE_3, BTI_JC, 0); + + return fail; +} diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.inc.c new file mode 100644 index 0000000000..ef7831ad76 --- /dev/null +++ b/tests/tcg/aarch64/bti-crt.inc.c @@ -0,0 +1,51 @@ +/* + * Minimal user-environment for testing BTI. + * + * Normal libc is not built with BTI support enabled, and so could + * generate a BTI TRAP before ever reaching main. + */ + +#include +#include +#include +#include + +int main(void); + +void _start(void) +{ + exit(main()); +} + +void exit(int ret) +{ + register int x0 __asm__("x0") = ret; + register int x8 __asm__("x8") = __NR_exit; + + asm volatile("svc #0" : : "r"(x0), "r"(x8)); + __builtin_unreachable(); +} + +/* + * Irritatingly, the user API struct sigaction does not match the + * kernel API struct sigaction. So for simplicity, isolate the + * kernel ABI here, and make this act like signal. + */ +void signal_info(int sig, void (*fn)(int, siginfo_t *, ucontext_t *)) +{ + struct kernel_sigaction { + void (*handler)(int, siginfo_t *, ucontext_t *); + unsigned long flags; + unsigned long restorer; + unsigned long mask; + } sa = { fn, SA_SIGINFO, 0, 0 }; + + register int x0 __asm__("x0") = sig; + register void *x1 __asm__("x1") = &sa; + register void *x2 __asm__("x2") = 0; + register int x3 __asm__("x3") = sizeof(unsigned long); + register int x8 __asm__("x8") = __NR_rt_sigaction; + + asm volatile("svc #0" + : : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory"); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 08c45b8470..b529a8c9c9 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -8,10 +8,15 @@ VPATH += $(AARCH64_SRC) # we don't build any of the ARM tests AARCH64_TESTS=$(filter-out $(ARM_TESTS), $(TESTS)) AARCH64_TESTS+=fcvt -TESTS:=$(AARCH64_TESTS) fcvt: LDFLAGS+=-lm run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) + +AARCH64_TESTS += bti-1 +bti-1: LDFLAGS += -nostartfiles -nodefaultlibs -nostdlib +run-bti-1: QEMU += -cpu max,x-guarded-pages=on + +TESTS:=$(AARCH64_TESTS)